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UNIT-2 Data Representation

This document discusses computer arithmetic and signed number representations. It covers fixed point and floating point representations. For signed numbers, it describes signed magnitude, 1's complement, and 2's complement representations. It provides details on the hardware implementation for signed magnitude addition and subtraction, including registers, sign flip flops, a parallel adder, and complementer. Flowcharts show the processes for addition and subtraction using this hardware.

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Ankit Jindal
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69 views11 pages

UNIT-2 Data Representation

This document discusses computer arithmetic and signed number representations. It covers fixed point and floating point representations. For signed numbers, it describes signed magnitude, 1's complement, and 2's complement representations. It provides details on the hardware implementation for signed magnitude addition and subtraction, including registers, sign flip flops, a parallel adder, and complementer. Flowcharts show the processes for addition and subtraction using this hardware.

Uploaded by

Ankit Jindal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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UNIT-2

COMPUTER ARITHMETIC
Data Representation
• Fixed point representation
• Floating point representation
Fixed point representation
• It have limited range of values and have relatively
simple hardware.
• Unsigned number- +ve integer including zero
• Signed number- -ve integer including zero.
• Computer hardware recognize all 1’s and 0’s.
• The unsigned number is represented with only
the magnitude field.
• Signed number representation- +ve – 0
-ve- 1
Signed Numbers
• Need to be able to represent both positive
and negative numbers

• - Following 3 representations
• Signed magnitude representation
• Signed 1's complement representation
• Signed 2's complement representation
Addition and Subtraction of signed
magnitude numbers
Hardware for signed magnitude
addition and subtraction
• AVF- add overflow flip flop
BS B Register

AVF Complementer M (Mode Control)

Output
E Parallel adder Input carry
carry

S
AS A Register Load Sum
Hardware Implementation
• It consists of registers A and B and sign flip flops As and Bs.
• Subtraction is done by adding A to the 2’s complement of B.
• The output carry is transferred to flip flop E, where it can be
checked to determine the relative magnitudes of the two
numbers. The add-overflow flip-flop AVF holds the overflow
bit when A and B are added.
• The A register provides other micro operations that may be
needed when we specify the sequence of steps in the
algorithm.
Hardware Implementation (cont..)
• The addition of A plus B is done through the parallel adder.
The S (sum) output of the adder is applied to the input of the
A register.
• The complementer provides an output of B or the
complement of B depending on the state of the mode control
M.
• The complementer consists of exclusive-OR gates and the
parallel adder consists of full-adder circuits.
• The M signal is also applied to the input carry of the adder.
When M = 0, the output of B is transferred to the adder, the
input carry is 0, and the output of the adder is equal to the
sum A + B.
• When M = 1, the l's complement of B is applied to the adder,
the input carry is 1, and output S = A + B +1. This is equal to A
plus the 2's complement of B, which is equivalent to the
subtraction A - B.
Flow chart for add and subtract
operations
Subtract operation Add operation

Minuend in A Augend in A
Subtrahend in B Addend in B

=0 =1 =1 =0
A S + BS AS + BS
AS ≠ B S
AS = B S AS ≠ B S AS = B S

EA ← A + B + 1
AVF ← 0 EA ← A + B

=0 =1
A<B E A≥B AVF ← E
≠0 =0
A←A A

A←A+1 AS ← 0
AS ← A S

END
(Result in A and AS)
Signed 2’s complement addition and
subtraction
Hardware : Flowchart :
References
Text Book
• M. M. Mano, Computer System Architecture,
Prentice-Hall,2004

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