Program : B.

Tech
Subject Name: Analog Circuits
Subject Code: EC-405
Semester: 4th
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RGPV University
Department of Electronics and Communication Engineering
Subject Name: Analog Circuits Subject Code: EC405
Subject Notes
Operational Amplifier: Differential amplifier and analysis, Configurations- Dual input balanced
output
differential amplifier, Dual input Unbalanced output differential amplifier, Single input balanced output
differential amplifier, Single input Unbalanced output differential amplifier . Introduction of op-amp, Block
diagram, characteristics and equivalent circuits of an ideal op-amp, Power supply configurations for OP-AMP.

Differential Amplifier: An amplifier which amplifies the difference between the two input signals is
differential amplifier. It is the basic building block of operational amplifier.
Figure 3.1 shows the circuit diagram of emitter coupled
+VC
differential amplifier. Emitters of transistor Q1 and Q2 are
C

IC1 RC IC2 connected to a single resistor RE. It has two input terminals,
R
Vo1 C inverting and non-inverting inputs. Amplifier output is a
Vo2
IB1 Vo IB2 function of the difference of the two input signals.
Q1 Q2 Differential amplifier is capable of handling very low
Rin Rin frequency signals and DC signals also because no
1 2 coupling capacitors are used. A few basic assumptions
IE1 IE2
have to be made to understand the analysis and
Vin1 Vin2 operation of a differential amplifier. It is assumed that
IE RE
Q1 and Q2 are matched on the basis of their
─VE Differential
Figure 3.1: Emitter coupled transconductance curve and current gain β. It is also
Amplifier
E assumed that transistors are operating at same
temperature and the supply voltages VCC and VEE are equal in
magnitudes. Also assumed that the value of resistors
are same
Operation of transistor differential amplifier: The operation of ifa their subscript are
transistorised same. amplifier can be
differential
understood by considering different operating conditions existing in the circuit. Figure shows the circuit diagram
of an emitter coupled differential amplifier. It consists of two identical NPN transistors biased by +VCC and -VEE supply voltages of
equal magnitudes and common to both. Both the collector resistors are identical and the emitter resistance is
common to both the transistors. The value of RE is quite large to ensure that in conjunction with -VEE. It behave like a constant current

source. The current through RE is almost constant and is given by the relation: IE = [VEE /RE]. As the two transistors are identical their

emitter currents IE1=IE2 and IE1+IE2=IE. Vin1 and Vin2 are the two input signal sources with Rin1 and Rin2 as the source resistances. The

input signals are applied at the base of the two transistors Q1 and Q2. The output voltage can be taken either between the two

collectors or between any one of the two collectors and the ground. In this circuit the output voltage is proportional
to the difference of the two input voltages, ie. the output voltage will be zero if the two input voltages are
equal.
When Vin1 = Vin2, IB1 = IB2 and IC1 = IC2, since both the collector resistances are equal the collector voltages of both the transistors will be

equal ie. VO1 = VO2. This results in an output voltage VO = 0.

When Vin1 > Vin2, IB1 > IB2 and IC1 > IC2, as both the collector resistances have equal values the output voltage VO will be proportional
to the difference of the two input voltages.
When the input voltage Vin1 is applied at the base of Q1 with the base of Q2 grounded, transistor Q1 acts like a common-emitter

amplifier and an amplified , inverted output voltage VO1 is obtained at the collector of Q1 ie VO1 = AD(Vin1 ). Thus the input voltage Vin1

produces
amplifier.output voltages ofinequal
It is observed amplitudes but
a differential with opposite
amplifier polarities
that when because
a positive thevoltage
input base-emitter voltages of both the
Vin1 is independently
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at the base of Q1, it produces a negative output voltage at VO1 and this input terminal is known as the Inverting input terminal. When a

positive input voltage Vin2 is independently applied at the base of Q2, it produces a positive output voltage at VO1 and this input terminal

is known as the Non-Inverting Input terminal. This is known as Differential Input. When the same input signal (same phase)
is applied at both the inputs, then the amplifier is said to have a Common Mode Input. In this case the
differential amplifier produces a zero output and is said to be perfectly balanced.
h-PARAMETER ANALYSIS OF EMITTER COUPLED DIFFERENTIAL AMPLIFIER:
The performance of the differential amplifier is evaluated by knowing the values of the differential mode
gain, Common mode gain and the common mode rejection ratio.
Differential mode gain (ADM):
+VCC +VCC
iB iC
IC1 RC RC IC2 IC B C
Vo1 Vo2 RC

IB1 Vo C hfe.iB
IB + hie
IB2 Q1 Q2
E
Rin1 Vo1
RC
IE1 IE2 B
+
Q1
V o1

VD ─ Rin V /2 ─
IE RE D
─VEE + E
When Figure 3.2: Differential
a differential modeMode
inputGain
is applied
as shownVD/2in figure 3.2, the input signals
Figureappearing at themodel
3.4: h-parameter base of the
─
two transistors are out of phase with oneFigure
another (ie. Input signal is applied at one input while the other input
3.3: Differential
Mode
is grounded), hence transistor Q1 gets a positive going signalHalf
while Q2 gets a negative going signal. This means that the forward bias on
Circuit
the base-emitter junction increases to produce an increase in base current iB1 and thereby an increase in collector current iC1 and

emitter current iE1. At the same time the forward bias on the base-emitter junction decreases to produce a decrease in base current iB2

and thereby a decrease in its collector current iC2 and emitter current iE2. An increase in transistor currents iB1 and iC1 (also iE1) of Q1 is

exactly equal to the decrease in transistor currents iB2 and iC2(also iE2) of Q2 because the sum of the two transistor currents is always a

constant & equal to the emitter current iE. The value of emitter current iE through RE remains unchanged irrespective of increase or
decrease in the two transistor currents. This results in a constant emitter voltage. Thus for small signal h-
parameter analysis we consider only the half circuit of the differential mode as shown in Figure 3.3 and assume
that the emitter is at ground potential without any emitter resistance (ie. RE = 0). The approximate small signal equivalent circuit or
the approximate h-parameter model of the differential mode half circuit is as shown in Figure 3.4.

From the base-emitter input circuit we have: VD/2 = iB.hie

From the collector-emitter output circuit we have: VO1 = – iC.RC−h hi
= –fe fe.iB RCC
B.R ie. VO1 = – hfe.iB.RC
V0
The differential mode gain, ADM forAunbalanced
DM ie. ended
or single ADM = output
−h2i (Q1) ie
. A
RC given by: DM
feh
is
= 1D B ie
=
V ie 2h
Similarly the differential mode gain for the other unbalanced or single ended output (Q2) is given
by:
ADM V02 i e. ADM = . ADM hfeR
ie
D 2iB ie C2 i
= h i =R
The differential mode gain for balanced or double endedhoutput is given
fe B C he
by: V −hfeiBRC − −hfeR
ADM = V01 − ie. ADM = ie. ADM
VD hfeiBR 2iCBhie C
V02 ie =
h
Common Mode Gain (ACM): When a common mode input is applied as shown in Figure 3.5 (Input signal VC is applied simultaneously at

base of transistor Q1 as well as the base of transistor Q2) the input signals appearing at the base of the two transistors are in phase with

one another. With this type of input both transistors Q1 and Q2 simultaneously get either a positive going signal or a
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negative going signal. This means that the forward bias on
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the base-emitter junction of transistors Q1 and Q2 increases or decreases simultaneously thereby causing a simultaneous increase or

decrease in collector currents iC1 and iC2 (also emitter currents iE1 and iE2). The value of emitter current iE through RE will be equal to

the sum of the two emitter currents iE1 and iE2 ie. iE = [iE1 + iE2], since iE1 = iE2= i the net emitter current iE = (2.i). Thus the emitter

current gets doubled and results in a doubled emitter voltage .

+VCC
iB iC
+VCC B C
IC1 RC RC IC2
Vo1 Vo2 hfe.iB
IC + hieE
IB1 Vo RC RC V
o
IB2 Q1 Q2 V ─
IB C
Rin1
C iE 2RE
Vo
IE1 IE2 B Q1 Figure 3.7: h-parameter
VC +
model
Rin
─ IE RE IE
VC + E
─VEE
Figure 3.5: Common Mode E ─ IE 2R
In order to Gain
carry out the small signal h-parameter analysis we consider only the half circuit of the common
mode configuration as shown in Figure 3.6 and also consider that the emitter resistance is doubled (2.RE) to take care of the
Figure 3.6: Common Mode Half
doubled emitter current and voltage. The approximate small signal equivalent circuit or the approximate h-
Circuit
parameter model of the common mode half circuit is as shown in Figure 3.7.
From Figure 3.7 , we have : iE = (iB + iC) = (iB + iB.hfe) = iB(1 + hfe) ie. : iE

=[iB(1 + hfe)]

From the base-emitter input circuit we have: VC = [iB.hie + iE.(2.RE)] =

[iB.hie + iB(1 + hfe).(2.RE)]

Vo
−hfeiBRC
AC ie.C A ie. ACM=
ie. VC = iB.[hie + (1 + hfe).(2.R
C E)] B ie −h R fe E ie
= M 1 M i [h f
e c
+ (1 +fe h )
Similarly
From the commonV
the collector-emitter mode
output
E gain for
circuit we the
haveother
:VO1 = unbalanced
– iC.RC = – or single ended output (Q2) is given
= [h
hfe.iB.RC
by: (2R ) ]−hfeiB + −h
(1fe +Rh)2R
AC Vo ie.C A ie. ACM=
ie. VO1 = [– hfe.i=
M
B.RC]
2C M iB[hieR+
] C (
1 + hfe)(2RE)] ie+c(1 +fe h)2R
E
V =unbalanced or single ended output [ h
The commonMode
Common mode gain , ACM for
Rejection Ratio (CMRR):
] CMRR represents the performance factor of an op-amp. An op-amp
(Q1) is given by the expression:
should not amplify noise signals appearing at its input terminals. A measure of this noise rejecting capability of
an op-amp is known as the Common Mode Rejection and a numerical value assigned to this capability is known
as the CMRR. The CMRR of an op-amp gives an idea about how well a differential mode signal is amplified and
how well a common-mode signal is rejected. Thus for an ideal op-amp the CMRR should be infinite. CMRR is a
frequency dependent parameter and its value reduces with an increase in frequency, which means that the
noise rejecting capability of an op-amp is poor at higher operating frequencies.
CMRR is also defined as the ratio of the Differential Mode Gain (ADM) to the Common Mode Gain (ACM), ie. CMRR =
[ADM/ACM].
Expressed in dB, CMRR is given by the expression: CMRR = [20. log10 .(ADM/ACM)].

CMRR = [ADM/ACM]. On substituting the expression of ADM and ACM we get,

−hfeRC ÷
CMRR ie. CMRR [hie + (1 +
−hfehRc [ h + (1 + h )
2R ] hi
= = hfe)2RE]
ie ie fe E e
But (1 + hfe) is approximately equal to (hfe) because (hfe >> 1), hence,
CMRR [ hi e+ ie. CMRR = 1 (hfe)2RE≈
hi hie h
= ( hf +
e)2R
e E] (hfei)
e 2RE

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∴ ≈ (hfe)2
REhi
e

DIFFERENTIAL AMPLIFIER CONFIGURATIONS : Differential amplifiers can be used in different configurations to

suit different requirements. Variation in differential amplifier configurations is based on the number of input
signals used and the way in which output voltage is measured. When one input signal is used, it is known as a
single input or single ended configuration and when two inputs are used it is known as a dual input or double
ended configuration. When the output voltage is taken across any one of the collectors and the ground, it is
known as unbalanced output and when the output voltage is taken across the two collectors, it is known as the
balanced output configuration. Based on these conditions, there are four important differential amplifier
configurations, they are : a) Single input balance output differential amplifier. b) Single input unbalance output
differential amplifier c) Dual input balance output differential amplifier d) Dual input unbalance output
differential amplifier.
A) Single Input Balance Output Differential Amplifier: In this amplifier as shown in figure 3.8, input is applied to
one of the base of transistor, say Q1 and base of Q2 is grounded. The output is measured between two collectors, which are at the
same DC potential. Therefore the output is said to be balanced output.
AC analysis of amplifier: AC equivalent circuit of the Single Input Balance Output differential amplifier with a
small signal T-equivalent model is shown in figure 3.9 below.

+VC VO +
C ie1
RC C1 Ic1 re E1 , 2 re Ic2
IC1 IC2 C VC2
Vo1 R VC1
C2 E ie2
2
B1 IB1 Vo2 C
─Vo + IB2 B1 + B2 +
C Q2
Q1
1 RC iC1 R i R
Rin iC2
B2 + Rin E E II C
1 ib1 ib2
+ E1 IE1 IE2 E
Vin + I
─
2 +
RE
IE Vin
Figure 3.8: Single Input
─VBalance
E
Output E Figure 3.9: AC Equivalent Circuit of Single Input
Balance Output
Voltage gain: Kirchhoff’s voltage equation for loop I & II gives-
Vin − Rinib1 − reie1 − REiE = 0 − − − − − − − − − − − −
− −3.1
Vin − Rinib1 − reie1 − reie2 = 0 − −i−e1 − − − − − − − − −ie2
Substituting current relations E = e1
i (i e2− b1 i ), i ≅ βac , and i ≅ and
Rin
− −3.2 b2 βac
neglecting very small we get βac
( re + R E ) ie
1 − ( R E ie
) 2 = Vi n −−−−−−−−−−−
− − 3.3

(re)i1
e + (re)ie
2 = Vi
n −−−−−−−−−−−−−
−RE 3.4
(re + RE)Vin
| r
i Vi = −−−−−−−
e rV ei+ Re
n |E
= 1 |
Equation 3.3 and 3.4 solved simultaneously n − 3.r5 ( r +
−RforE
ie1 and ie2 by using e
cramer’s
e rule-
re
re 2RE)
|
Similarly,
r +
|e Vi
R r (RE)
ie E V
n in
2
re e+ RE = e −−−−−
= | | | r Vi n+ 2R E)
−Rr e
E
e
−3.6
re (r
The output voltage is, Vo = VC2 – VC1 = RC.iC2 –(−RC.iC1) = RC (iC1 + iC2)
Page no: 4 since ie = ic hence, Vo = FRoCl(lieo1w+iue2s)-o-n-f-a-c-e-b-o-o-k-t-o-g-e-t-r-e-a-l---t-i3m.e7
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Substituting the ie1 and ie2 in equation 3.7, we get

R€
Vo = e Vin − − − − − − − − − − − − − − −
r
3.8
Therefore
, V0
Ad =V
Rin
C
= − − − − − − − − − − − − − 3.
independent of RE and this equation is identical to the voltage gain equation of
Equation 3.9 is the voltage gain equation and is e
common emitter amplifier.
b) Differential input resistance: Input resistance Ri seen from the input signal source is determined as follows-
Vin = βac
Ri =b1 = e1 ac
i ⁄β
Substituting the value of ie1 from equation 3.5, we get Ve1 in Vin
i
Ri = 2i
a
c
e i
≫
f R
e E− − − − − −3. 10
c) Output Resistance: Output resistance RO is the equivalent resistance , measured at collector of either transistor Q1 or Q2 with respect

to ground and is given by the equation RO1 = RO2 = RC

B) Single Input Unbalance Output Differential Amplifier: In this amplifier shown in figure 3.10, input is applied
to one of the base of transistor, say Q1 and base of Q2 is grounded. The output is measured at either collector with respect to ground,
say output is measured at collector of Q2 with respect to ground.
AC analysis of amplifier: AC equivalent circuit of the amplifier with a small1signal T-equivalent
2
model is shown in
+VC C I ie1 Ic2
figure 3.11 below. 1 c1 + re E , 2
C
E VC2
IC1 R R IC2 C
Vo2C
B1 + + B2 +
C
C 2
B1 IB1 Vo+
─ IB2 RC
1
Q1 Q2 iC1 R i iC2 RC
C
+ Rin E E IIre
Rin ib1 ib2
B2 VO
1 + ie2
+ E1 IE1 IE2 E + I
Vin 2
─ IE Vin
RE

Figure 3.10: Single Input

─VUnbalance
E Figure 3.11: AC Equivalent Circuit of Singe Input Unbalance
Output E Output Differential Amplifier

The output voltage is, Vo = VC2 = RC.iC2

since ie = ic hence, Vo = RC ie2-------------------------------------------3.11

Substituting the ie2 from equation 3.6 in equation 3.11, and if RE >> re we get,
Vo = R Vi − − − − − − − − − − − − − − −
2€
3.12 e n
r
Therefore
, V0
Ad =V
Rin
C
= − − − − − − − − − − − − − 3.
2
e
13
b) Differential input resistance: Input resistance Ri seen from the input signal source is determined as follows-
Vin βac
Ri =b1 = e1 ac= e1
i ⁄β
Substituting the value of ie1 from equation 3.5, we get Vin Vin
i
Ri = 2i
a
c
e i
≫
f R
e E− − − − − −3. 14
c) Output Resistance: Output resistance RO is the equivalent resistance , measured at collector C2 of transistor Q2 with respect to ground

and is given by the equation RO = RC

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C) Dual Input Balance Output Differential Amplifier: In this amplifier as shown in figure 3.12, input signals (Vin1 and Vin2) are applied to

the base of transistors Q1 and base of Q2. The output (Vo) is measured between two collectors, which are at the same DC
potential. Therefore the output is said to be balanced output.
AC analysis of amplifier: AC equivalent circuit of the Dual Input Balance Output differential amplifier with a
small signal T-equivalent model is shown in figure 3.13 below.
+VCC VO +
Ic1 ie1 Ic2
C re E, E  r C
IC1 RC VC1
1 1 2 e + 2
+  VC2
2 ie2
B RCB1
─Vo +IC2 B1 B2
C1 IB2 + 
I 
B2 RC
Vo1 iC1  RE 2iE RC
+ 
Vo2 iC2 Rin1 
Rin2
i
+
C b1 i
b2

1
E E + II
Q1 +
Q2 t + I
+
Rin1 Vin2
Vin1
Voltage gain: Kirchoff’s
Rin2 voltage equation for loop I & II gives-
Vin E1 − Ri
I1 n1ib 1 − reie 1 − RE(ie 1 + ie 2) = 0 − − − − − − − − − − − −
−
IE2 − 3 .15 V i
n
2 − R i
n i
2 b2 − r i
e e2 − R E ie
( 1 + ie
2) = 0 − − − − − − − −
− −relations
Substituting Ecurrent
2
− − − −3i .16 e1 , and i ≅ e2 and neglecting Rin1 and Rin2 very
b1 ≅
i i
+
βac βac βac
small we get in1 b2
(re + REβ)acie
1 + ( RE ) ie
2 = Vi
1 −−−−−−−−−−−
n
Vin2
─ − 2I
− 3.17
R
─VEE
(| RVE
) ie1 R+ (re + RE)ie2 = Vin2 − − − − − − − − − − −
in
−1 V
− 3.18 eE +
in r
Figure 3.12: DualiInput Balance = (re + RE)Vin1 − −−−−−−−
outpu e
1
r2 e+ |R Figure 3.13:2ACE
Equivalent Circuit of Dual Input Balance output
Equation 3.17 and | R
=solved simultaneously
3.18 − 3.
E for ie1 and (1 9
ie2R ( e
rVin+
byEusing
) R rule-
)
cramer’s −
Differential Amplifier RERE reE+ R E 2
2
Similarly, |E R Differential Amplifier
r +
|e Vin
ie RER Vin2
1 = (re + RE)Vin2 − −−−−−
2
r + R
= |e E | ()
( RE rVein1+ RE)2 − −3.20
RERE rEe +
RE2
RE|
The output voltage is, Vo = VC2 – VC1 = −RC.iC2 –(−RC.iC1) = RC (iC1 − iC2)

since ie = ic hence, Vo = RC (ie1 − ie2)-------------------------------------------3.21

R€
Vo= 3.21, in1
Substituting the ie1 and ie2 in equation we get
− V ) −−−−−−−−−−−−−−−
r in2
Therefore (V e 3.22
, V0
Ad =V
Rid
C
= − − − − − − − − − − − − − 3.
e is independent of RE since RE and this equation is identical to the voltage gain
Equation 3.23 is the voltage gain equation and
23
equation of common emitter amplifier.
b) Differential input resistance: Differential Input resistance Ri1 and Ri2 is defined as the equivalent resistance that would be measured at

either input terminal with the other input terminal grounded. Means that Ri1 seen from input signal source Vin1 is determined and

other source Vin2 is set at zero. Usually source resistance Rin1 and Rin2 are very small and be ignored. In equation form-
Vin1 βacVin
Ri1 = b1 = e1 ac= 1
i ⁄β
Substituting the value of ie1 from equation 3.5, we get Vei 1n1
i
Ri1 = 2ace i
f R E ≫ re , i
then (re + 2RE ≅ 2RE)and (re + RE)≅ RE − −
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Similarly, Ri2 = 2ace − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − 3. 25

c) Output Resistance: Output resistance is defined as the equivalent resistance that would be measured at either
output terminal with respect to ground. Output resistance RO is the equivalent resistance, measured between collector C1 and ground

is equal to that of collector resistance and is given by the equation RO1 =RO2 = RC

D) Dual Input Unbalance Output Differential Amplifier: In this amplifier as shown in figure 3.14, input signals
(Vin1 and Vin2) are applied to of the base of transistorsQ1 and base of Q2. The output (Vo) is measured at either of the two

collectors C1 or C2, with respect to ground.

AC analysis of amplifier: AC equivalent circuit of the Dual Input Unbalance Output differential amplifier with a
small signal T-equivalent
+VCC model is shown in figureC13.15Ic1below. ie1 r + Ic2
VC1 e E1, E2 C
+ VC2
IC1 R R ie2
2
IC2 re
C B1 + B2
IB1 C C2
C + Vo IB2
B1 1 Vo 2Q2 RC iC1 RE 2iE R
Q1 ─ B2 iC2
ib1 Rin ib2 C
Rin + Rin
Rin 1
II 2
+ VO
1
+ IE1 IE2
2
I ++
E E + ++
Vin1 Vin2 2 Vin2
1 Vin1
─ RE
2IE ─VEE Figure 3.15: AC Equivalent Circuit Of Dual Input Unbalance Output
Figure 3.14: Dual Differential Amplifier
Input Unbalance
Output
Voltage gain: Kirchoff’s voltageAmplifier
Differential equation
for loop I & II gives-
Vin1 − Rin1ib1 − reie1 − RE(ie1 + ie 2) = 0 − − − − − − − − − − − −
− −3.26 Vin2 − Rin2ib2 − reie2 − RE(ie1 + ie 2) = 0 − − − − − − − −
− −relations
Substituting current − − − −3i.27
b1 ≅
i e
1
, and i ≅ i e
2
and neglecting Rin1 and Rin2 very
βac βac βac
small we get b2
(re + REβ)acie
1 + (RE)ie
2 = Vi
1 −−−−−−−−−−−
n
− − 3.28

(RE)ie
1 + ( r e + R E ) ie
2 = Vi
2 −−−−−−−−−−−
n
−| − 3.29 R
V
Vi n
in re E+
ie 1 = (re + RE)Vin1 − −−−−−−−
1
r2 + R
Equation 3.28 and 3.29
e
RE|for ie1 and
=solved|simultaneously −3. 3R
ie20byE re + R)2 −E
(using cramer’s rule-
RERE reE+ R ( )EVin2
2
Similarly, |E R
r +
|e Vin
R R
ie E V
1 in2 = (re + RE)Vin2 − −−−−−
2
re + E R
= | | ( RE ()rVein1+ RE)2 − −3.31
RERE r
eE + R
|E RE2
The output voltage is, Vo = VC2 = Vo2= −RC.iC2

since ie ≈ ic hence, Vo = −RC

R€
( ie2)-------------------------------------------3.32
Vo= in1
2r − V ) −−−−−−−−−−−−−−−
in2
Substituting the ie2 in (
Therefore V e 3.32, and3.33
equation
, V
generally RE ≫re, t
hn (rd
e e +2R0E ≅
A =V Rid
C
= − − − − − − − − − − − − − 3.
2
2R )an
d
Thus the voltage (r + R )≅
gaine is half R we
E the gain get
34E of the dual input balanced output differential
E e
amplifier.

Ri1 = Ri1 = 2ace − − − − − −3.

b) Differential
Page no: 7 input resistance: Differential Input resistance Ri1 and R
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c) Output Resistance: Output resistance is defined as the equivalent resistance that would be measured at
either output terminal with respect to ground. Output resistance RO is the equivalent resistance, measured at collector C2 and ground
is equal to that of collector resistance and is given by the equation RO = RC
INTRODUCTION TO OP-AMP: An op-amp is a direct coupled high-gain amplifier. It consists of one or
more
differential amplifiers and followed by a level translator and output stage. It can amplify DC as well as AC
signals.
By addition of suitable +V
external
CC feedback components, op-amp is designed to perform mathematical operations
V1 = Voltage at non-inverting input (volts) V2 =
2
such as addition,
V2 subtraction,
 7 multiplication, integration, differentiation, active filters, oscillators, comparators,
6
Voltagesymbol
regulators and others.A Figure 3.16 shows the schematic at inverting input (volts)
of Op-amp.
V1 3 + 4 VO Vo = Output Voltage (volts)
VEE All these voltages are measured with
Figure 3.16: Schematic Symbol of OP-AMP
respect to ground.
Block diagram representation of op-amp: A = large-signal voltage gain.
The block diagram of a typical op-amp is as shown in figure 3.17. It has four important stages which are as listed
below.

Non-Inverting Input
Intermediate Level Shifting Output Stage
Input Stage
Stage Stage Output
Inverting
Dual input, balanced Dual input, Emitter follower using Complementary
Input symmetry push-
output differential unbalanced output constant current
amplifier differential source pull amplifier
amplifier
Figure 3.17: Block Diagram Representation of OP-AMP
The first stage is the input stage which is a dual input, balanced output differential amplifier. This stage generally
provides most of the voltage gain of the amplifier and also establishes the input resistance of the op-amp.
The second stage is the intermediate stage which is usually another differential amplifier which is driven by the
output of the first stage. In most of the op-amps the intermediate stage is a dual input, unbalanced (single
ended) output.
Cascaded differential amplifier are used to provide a required voltage gain. The net gain is the product of the
voltage gains of individual differential amplifier. Thus a very high voltage gains with a very low noise levels are
obtained.
In op-amps the amplifier stages are directly coupled (coupling capacitors are not used) to make them handle all
frequencies from 0 to several MHz, hence there is no DC isolation. This direct coupling results in a high level of
DC voltage at the output of the amplifiers. Thus a level shifter or level translator is used to shift the DC level to
zero volts with respect to ground. The level shifter circuit is basically an emitter follower circuit.
The final stage ie. the output stage is usually a complementary symmetry push-pull power amplifier. This stage is
mainly used to increase the output voltage swing and also to increase the current supplying capability of the op-
amp. A well designed output stage also provides a low output resistance.

Ideal Op-Amp characteristics:

Ideal op-amp characteristics:

+VCC
Ib2=0 2
1)Infinite voltage gain AV. V2  7 AV=Infinite
2)Infinite input resistance Ri. Vid=0 AV
6

3) Zero output resistance Ro. V1 3

+ 4 VO
VEE
4) Zero output voltage when input voltage is zero. Ib1=0
Figure3.18: Equivalent circuit of an ideal OP-
5) Infinite bandwidth.
AMP
6) Infinite common-mode rejection ratio.
7) Infinite slew rate.

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Equivalent circuit of op-

amp: Equivalent Circuit of op-amp is shown in figure 3.19. The
Inverting Input V2 +VC voltage Vid is the differential input voltage Vid =(V1 −V2). Ri is the input
─ C

resistance of the device. The gain parameter A is called the

+ Outpu
Vid Ri R open loop gain. The output voltage is Vo = AVid = A (V1 −V2) Which
o t function of the difference between the input voltages V1and
A.Vid
Vo indicates that the output voltage Vo is a
Noninverting V2. Note that the AVid is an equivalent thevenin voltage source and Ro
+ is the thevenin equivalent resistance looking back into the
Input V1 −VEE output terminal of an OpAmp. The equivalent circuit is
Figure3.19: Equivalent circuit of OP- useful in analyzing the basic operating principles of op-amps
AMP and in observing the effects of feedback arrangements.
Power Supply Configurations of Op-
Amp:
+VCC = +VS / 2
Inverting +VCC
2 + R C
I/P V2  7 6 VS
741
V1 
3
+ 4 VO R C
Noninverting VEE
I/P VEE = VS /
Figure3.21(a) : Arrangement for
2 obtaining
Figure3.20: OP-AMP Power Supply
Connections positive and negative Supply voltages for an
Opamp
+VCC = +VZ1 +VCC = +VS / 2
R
D1
+ D1 + C
S VZ1
VS VS R
 
P C
D2 D2
VEE = VEE = VS /
Figure3.21(b) : Arrangement
VZ2 for obtaining
VZ2 for an Figure3.21(C) : Arrangement for
2 obtaining
positive and negative Supply voltages
positive and negative Supply voltages for an
Opamp
As opamp uses one or more differential amplifier stagesOpamp
and differential amplifier requires both positive and
negative power supply for proper operation of the circuit. The two power supplies required for a linear IC are
usually equal in magnitudes, +15V and 15V respectively. These power supply voltages must be reference to a
common point or ground. Figure 3.20 shows power supply connections for the 741 opamp. Pin 7 is a positive
supply and pin 4 is a negative supply pin. Instead of using two separate power supplies, we can use a single
power supply to obtain +VCC and VEE as shown in figure 3.21 (a), (b) and (C). In figure 3.21 (a) the value of total
resistance (2R) should be S10kΩ for not to draw much current from the supply VS. The two capacitors (range from 0.01µF to 10µF)

provides for decoupling (bypass) of the power supply. In figure 3.21 (b) zener diodes are used for obtaining
symmetrical power supply voltages. The value of RS is chosen such that it supplies sufficient current for the diodes to operate in

avalanche mode. In figure 3.21 (C) the potentiometer RP is used to assure equality

between +VCC and VEE values. Diodes D1 and D2 are used to protect the IC, if the negative and positive terminals of VS are accidentally

reversed.

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Characteristics of op-amp: Ideal and Practical, Input offset voltage, offset current, Input bias current,
Output offset voltage, thermal drift, Effect of variation in power supply voltage, common-mode rejection ratio
(CMRR), Slew rate and its Effect, PSRR and gain bandwidth product, frequency limitations and compensations,
transient response, analysis of TL082 datasheet.

CHARACTERISTICS OF A PRACTICAL OP-AMP:

+VCC
IB2 2
7
V2  6
Vid=0
V1 AV 3
+ 4
IB1 VEE
Figure V
4.1:
O
OP-AMP
a)Input Offset Voltage (Vio): The voltage that must be applied between two input terminals of op-amp to nullify the output ie. Vo =0V

is input offset voltage. This voltage could be positive or negative. The smaller the values of Vio, better the input terminals are matched.

For IC741C, Vio = 6mV maximum.

b)Input Offset Current (Iio): The difference between the separate input currents entering into the two input terminals is referred as

input bias current and given by equation Iio = [IB1 – IB2] with Vo = 0. For IC741C, Iio = 200nA maximum.

c)Input Bias Current (IB): The average of the separate input currents entering into the two input terminals is referred to as input bias
current and is given by equation: IB = [(IB1 + IB2)/2]. For IC741C, IB = 500nA maximum.

d)Output Offset Voltage (VOO): The output offset voltage is the DC voltage between the output terminal and ground of an amplifier,
when the two inputs are grounded ie. V1 = V2 = 0 V. For IC741C, VOO = ±15V maximum.

e)Thermal Drift : The average rate of change of input offset voltage (ΔVIO) or change of input offset current (ΔIIO) or change in input
bias current (ΔIB) per unit change in temperature (ΔT) is called thermal drift.

ΔVIO / ΔT = thermal voltage drift (μV/°C); ΔIIO / ΔT = thermal current drift (pA/°C)

f)Common-Mode Rejection Ratio (CMRR): It is defined as the ratio of differential voltage gain(ADM) to the common mode voltage

gain(ACM) ie. CMRR = ADM/ ACM. The higher the value of CMRR, the better is the matching between two input terminals and the
smaller is the output common-mode voltage. For the 741C, CMRR is 90dB typically.
g)Power Supply Rejection Ratio (PSRR): The change indVan op-amps input offset voltage ΔVio caused by variation
0
in supply voltages ΔV
Expressed in V/μS.
is called power In equation
supply sensitivityform:
(PSS).SR The=d . The Opamp
reciprocal of the741PSShas a slew
is PSRR or rate
supplyof voltage
0.5 rejection ratio (SVRR)
V/µs. This means
PSRR= ΔVcannot that
/ΔVio. Expressed the
output rise orinfall
V/µV
atora inrate
decibels (dB).V
of 0.5 Forinthe
1 741C,
µs ie.SVRdistortion
R= 150μV/V.will
Lower the value
occur of SVRR,
at voltages
greater than
the better for0.5 V when
op-amp performance.
operating
h) at an
Slew Rate unity
(SR): gain
Slew with
rate an output
is defined frequency
as the maximum of 1rate
MHz.of change of output voltage with respect to time.
Slew rate indicates how rapidly the output of an op-amp can change in response to the changes in the input
frequency. Also known as output voltage swing, as a function of frequency or as a voltage follower large-signal
pulse response. For 741C, slew rate is 0.5V/μs. The slew rate of an op-amp is fixed, therefore if the slope
requirements of the output signal are greater than the slew rate, then distortion occurs. One of the drawback of
IC741C is its low slew rate (0.5V/μs), which limits its use in high frequency applications, such as oscillators,
comparators and filters.
i) Gain-Bandwidth product: Gain-Bandwidth product is the bandwidth of the op-amp when the voltage gain is
1. From the open loop voltage gain versus frequency graph it can be found to be approximately 1MHz.
Causes of Slew Rate limitation : Slew rate is caused by current limiting and the saturation of internal stages of
an op-amp when a large amplitude signal of high frequency is applied. Thus the slew rate is a large signal
phenomenon. The resulting maximum current is available to charge the capacitance compensation network. As
the capacitor requires a finite amount of time to charge and discharge, hence the internal capacitors prevent the
output voltage from responding immediately to a fast changing input. Thus the slew rate limiting is caused by
this
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The slew rate equation is given by the expression: SR = 2fVP V/Sec = 2fVP /106 V/Sec
Where, f = input signal frequency in Hz, VP = peak value of the output sine wave in volts.

Slew rate determines the maximum frequency fmax of operation for a desired output swing. If the right hand side value of the slew
rate equation is less than the slew rate of the op-amp, the output waveform will always be undistorted. If the
value exceeded, the output waveform will be distorted.
Effect of Slew Rate in Applications: Slew rate has effect on both open and closed loop configurations. In open
loop configuration, using IC741C, open loop gain is very large. Output will swing between +14V to -14V each
time the input sine wave crosses zero volts as shown in figure 4.2 (a).
+VP
INPU +15
T 2
0  7
t A 6
741
C 4
−VP B
3
+ VO
1
+14 OUTPU VIN 5
V T RIN ≈0Ω
0 t
─14V

56μs Figure 4.2 (b): Open loop

Figure 4.2 (a): Input and output Waveforms configuration
The time taken by the output to go from +14V to -14V can be determined by slew rate value of 741C. Slew rate
can be calculated from the slope of the output waveform. The 741C has a typical slew rate of 0.5V/μs. Therefore
we have (28V / 0.5V/μs) = 56μs. This means that 56μs is the minimum time between the two zero crossings.
Hence the maximum input frequency fmax at which the output will be distorted is given by

fmax = (1/(2x 56μs) = 8.93kHz.

Therefore at fmax, the output will be triangular wave instead of a square wave. Thus, to get a square wave output, input frequency

should keep below fmax or choose an opamp with a faster slew rate. RF = 10 kΩ, RIN = 1 kΩ;
Figure 4.2 (c), shows closed loopIO configuration where the opamp used
So, Gain as an inverting
of Inverting amplifier
amplifier is equalwith
to: a gain of 10.
RIN (RF / RIN ) = (10 k / 1 k) = 10.
ARF 6 The amplifier will operate with a gain of 10 up to about
Ii 741
VIN +VCC 91 kHz.
B 2+ 74 VO
3 
VEE BW with feedback, fF = [Unity Gain Bandwidth xK] / AF

Figure 4.2 (C): Close loop where, UGB = 1 MHz, K= RF / (RIN + RF) and AF,
configuration Amplifier gain = 10.

On substituting we get, BW with feedback, fF ≈ 91kHz. Since,

SR = 2fVP V/Sec = 2fVP /106 V/Sec
Substituting the value of fF and 0.5 V/µS (SR of opamp 741C) in

the above equation

We get, VP = 0.874 Vpeak (Undistorted) Or VO = 2 x 0.874 Vpeak =

Effect of variation in power supply voltages on offset voltage: Due to poor regulation and filtering, the supply
1.75 Vpeak-peak (Sinewave).
voltages (+VCC and –VEE) changes. This change results in a change in the input offset voltage, which in turn causes change in output
Hence, for
offset the output
voltage. Thistochange
be a sinewave, the maximum
in input input is specified in datasheet by variety of terms as input offset
offset voltage
voltage sensitivity,
signal VINMAX should bepower
less than-supply
1.75/10voltage
= 175mVrejection
p-p
ratio, power supply sensitivity and supply voltage rejection
ratio. Terms are expressed in μV/V or in decibels (dB). Example: For the 741C, SVRR = 150μV/V maximum and
typically 20 log (ΔV/ΔVio) = 76.48dB
20 log(1/SVRR) = 20 log (1/(ΔVio/ΔV) = 20 log (1/150μV/V) = 20 log (106 / 150) = 76.48dB. Lower the
value of SVRR, the better the op-amp performance.
Relationship
Page no: 11between the change in output offset voltage
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Where, ΔVOO = change in output offset voltage (volts); ΔV = change in supply voltages (+VCC and –VEE); ( ΔV/ΔVio) =

Supply voltage rejection ratio (V/µV)

FREQUENCY LIMITATIONS AND COMPENSATIONS:

Frequency Response plot: Manner in which the gain of the op-amp responds to the different frequencies is
frequency response. A graph of magnitude of gain versus frequency is called frequency response plot.
Limitation: Some of the characteristics of op-amp such as voltage gain, input resistance, output resistance,
output
voltage swing, input noise voltage and noise current and CMRR are frequency dependent parameters. Most
important voltage gain A decreases as the operating frequency increases. This variation in gain as a function of
frequency imposes a limitation on performance of op-amp and also when op-amp used in AC applications.
Compensating networks:
Change in gain and phase shift between input and output as a function of frequency is credited to the internally
integrated capacitors as well as stray capacitances.To modify
These the rate ofare
capacitances change of the
due to gainphysical
as well characteristics
as phase shift by
of
C using a specific component
semiconductor devices (BJTs or FETs) and internal construction of the op-amp.
2 network (components are
V2  5 62 R2
709
resistors and capacitors) with op-amp is called a
8
VO
compensating network. The phase lead (contributes a
V1 +
3 1
R1
positive phase angle) and phase lag (contributes a negative
phase angle) are the most compensating networks in op-
C1
amp. Two types of compensating networks : internal
compensating network and external compensating network.
Figure 4.3(c): Frequency compensation circuit
of op-amp 709

IC741C is an internally compensated op-amp and op-amp 709 is a noncompensated op-amp ( ie. External
discrete components are added at the designated terminals of op-amp. The open-loop frequency response
curves and the connection diagram of IC709 for the external compensating components is shown in figure
4.3(a,b and c).
AOL(dB) AOL(dB) Vs =±15V
+120 +10
+106 0
+8 C1=10pF, R1
+80
0 =0Ω,C2=3pF
+60
+60
+40
+40 C1=5000pF, R1
+20
+20
0 =1.5kΩ,C2=20
0
-20 -20 0
F, frequency 1
5 10 100 1k 10k 100k 1M UGB
in Hz pF
fo 0
Break frequency 0
1
Figure 4.3(a): Frequency Response of
internally compensated op-amp 741 1
K

1
Transient Response: The response of any practically useful network
0 to a given input is composed of two parts:
the transient and steady state response. The transient responsek is that portion of the complete response before
the output attains some fixed value (steady state value). Transient response is time variant. Rise time and the
1
percent of overshoot are the characteristics of transient response. The time required by the output to go from
0
10 % to 90% of its final value is called rise time. Overshoot0 is the maximum amount by which the output
deviates from the steady state value. The transient response test circuit for
k the 741C for Vin = 20mV, rise time is 0.3μs and overshoot

is 5%. Transient response is one of the important considerations

1 in selecting op-amp in ac applications. Rise
time is inversely proportional to the unity gain bandwidth of op-amp.
M This means that the smaller the value of
Page
rise no:
time 12
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Thermal Drift: The average rate of change of some of the characteristics of op-amp such as input offset voltage
(Vio), input offset current (Iio) and input bias current (Ib) due to the change in temperature is thermal drift.

ΔIio/ΔT = thermal drift in the input offset current (pA/°C) [Thermal Current Drift]
ΔIb/ΔT = thermal drift in the input bias current (pA/°C) [Thermal Current Drift] ΔVio/ΔT =
thermal drift in the input offset voltage (μV/°C) [Thermal Voltage Drift]

ANALYSIS OF TL082 DATASHEET: IC TL082 is a wide bandwidth dual JFET input operational
amplifier manufactured by Texas instruments. It is low
cost, high speed with an internally compensated input
offset voltage. It maintains a large gain-bandwidth
product and fast slew rate. JFET input devices provide
very high input impedance and very low input bias and
input offset currents. It has very low noise level and
offset voltage drift hence not sensitive to temperature
variations.

Features of TL082C:
: Low Power Consumption. : Low Input Offset Current: 5 pA Typical.
: Wide Common-Mode and Differential Voltage : Output Short-Circuit Protection.
ranges. : Low Total Harmonic Distortion: 0.003% Typical.
: Low Input Bias Current: 30 pA Typical. : High Slew Rate: 13 V/μs Typical.
: High Input Impedance: JFET Input Stage.
: Common-Mode Input Voltage Range Includes VCC+

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IC-741C IC-TL082
1) BJT input operational amplifier. 1) JFET input operational amplifier.
2) Not compensated internally the input offset voltage. 2) Internally compensated input offset voltage.
3) CMRR- 90 dB Typical. 3) CMRR- 86 dB Typical.
4)Differential input voltage, VID : ±15V (max.) 4)Differential input voltage, VID : ±30V (max.)
5) Input resistance: 2 MΩ (BJT Input Stage). 5) Input resistance: 1012 Ω (JFET Input Stage).
6) Input Offset Current: 1 mA Typical. 6) Offset Current: 5 pA Typical.
7) Output Short-Circuit Protection. 7) Output Short-Circuit Protection.
8) Rise Time overshoot factor: 0.3μS Typical. 8) Rise Time overshoot factor: 0.05μS Typical
9)Slew Rate at unity: 0.5 V/μs Typical. ( VI = 10 V, 9)Slew Rate at unity: 13 V/μs Typical. ( VI = 10 V,
CL = 100 pF, RL = 2 kΩ) CL = 100 pF, RL = 2 kΩ)
10)Unity gain bandwidth- 1MHz 10)Unity gain bandwidth- 3MHz

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OP-AMP applications: Inverting and non-inverting amplifier configurations, Summing amplifier, Integrators
and differentiators, Instrumentation amplifier, Differential input and differential output amplifier, Voltage-
series feedback amplifier, Voltage-shunt feedback amplifier, Log/ Antilog amplifier, Triangular/rectangular wave
generator, phase-shift oscillators, Wein bridge oscillator, analog multiplier-MPY634, VCO, Comparator, Zero
Crossing Detector.

OP-AMP AS INVERTING-AMPLIFIER:

Circuit diagram of Inverting amplifier with feedback is

IO RF shown in Figure 5.1. Input voltage VIN in series with input resistance
RIN
+VCC RIN is connected to input inverting terminal (pin2) of op-amp.
 7 6
2 V2 741
IIN Non-inverting terminal (pin3) is grounded. Feedback resistor
VIN + 4
V1 3 VO
VEE
RF is connected in between inverting terminal and output terminal

(pin6) VO of op- amp.

Due to high input impedance, the op-amp input current
Figure 5.1: Inverting Amplifier with
is
feedback
zero, means that point V1 and V2 are at the same potential. Point V1
From the 5.2 is also at ground potential.
is at ground potential means that point V
IIN ≈ IO
circuit; That is, 1
Thus point V2 is said to be at virtual ground.
VIN − V2 −
= ……………………………
V2RI V0RF
….
N
Due to virtual ground concept, V1 = V2 = 0V 5.2
Therefore, equation 5.2 becomes,
−V
VI = ……………………………
R
NI 0RF
….
Ie. N
5.3
V0
= …………………………. .5.4
V
−RF RI
N
IN

Hence from equation 5.4, VO / VIN is the Voltage gain AV, by definition.
Therefore
V0
AV= =
V
−R
INF R
IN
The output voltage VO for inverting amplifier is given by:
−R
V0 = F(IN )
R
VIN
The negative sign indicates that the input and output signals are out of phase by 180°. Gain of the amplifier is

set by selecting the ratio of feedback resistance RF to the input resistance RIN.

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OP-AMP AS NON-INVERTING
AMPLIFIER:
Circuit diagram of non- Inverting amplifier with feedback is
IO RF
shown in Figure 5.2. Input voltage VIN is applied to non- inverting
RIN 2 7+V
V2  CC
6 terminal of op-amp. Input resistance RIN is connected to
741
IIN
3
+ 4 VO inverting terminal of op-amp and it is grounded. Feedback
V1
VEE
resistor RF is connected in between inverting terminal and output
VIN
terminal VO of op-amp.
Figure 5.2: Non-Inverting Amplifier with Due to high input impedance, the op-amp input current
is
feedback
zero, means that point V1 and V2 are at the same potential. Point V1
From the circuit, the entire current passes through RIN as the input current of op-amp is zero. From the circuit;
is at ground potential means that point V2 is also at ground potential.
V2−0 V0−V2
That is, = ……………… I ≈
IN……OI …………. 5.5
Thus point V 2 is said to be at virtual ground ie. V1 = V2 = VIN
5.6 RIN R F
Due to virtual ground concept, V1 = V2 = VIN
Therefore, equation 5.6 becomes,
VI =
V0 −
……………………………
R
NI VINRF
….
Ie. N
5.7
V0 R
VIN = 1 +FR
I
…………………………. .5.8
VO / VIN is the Voltage gain AV, by definition. N
Hence from equation 5.8,
V0 R
AV= =1 +
VIN FI
The output voltage VO for non- inverting amplifier is given by: N
R
RF
V0 = (1 +IN
R
The positive sign indicates that the input and output signals
are in phase. )
VIN
OP-AMP AS SUMMING AMPLIFIER (ADDER CIRCUIT):
Inverting Summing Amplifier : Figure 5.3 shows the op-amp as an adder (Inverting
IO Summing Amplifier). It is used to add voltages V1 and V2 which are
I1 RI RF +VCC connected to inverting terminal through resistor R1 and R2.
A 2  7 6
741 Current I1 and I2 are the input currents and I0 is the output current.
VI V2 R2 I2 B + 4 Non-inverting terminal is grounded.
3 VO
VEE Total input current ,Ii = I1 + I2 ...........................5.9

Output current, IO = VO / RF ..............................5.10

Figure 5.3: Op-amp as an For op-amp in inverting mode, Ii =V− 2IO ..............5.11
Adder (Inverting) Therefore, equation 5.11
R1 +becomes
−V
R 0 RF
V21
=
V1 +V2
If R1=R =R then; −V
0 =
2 R F −
Therefore, output voltage
RF of an adder is : V
0 =R(
R
)V
1 + V ……………………………5
. 12
2
If (RF/R) = 1 then, the output voltage, VO = − (V1 + V2).
The output voltage is equal to sum of the input voltages with a negative
sign.
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Non-inverting Summing Amplifier :

Figure 5.4 shows the op-amp as an non-inverting adder
IO RF (non- Inverting Summing Amplifier). It is used to add voltages V1 and V2

IIN RIN A which are connected to non-inverting terminal through resistors R

2  +VCC
6
R 7417 and also by selecting of appropriate values of resistors RIN and
B 4
VO
I1 RF. Current I1 and I2 are the input currents and I0 is the output current.
R VEE
32 + I Recall that the input impedance of non-inverting amplifier is
VI V2 very large. Therefore by using superposition theorem, the
voltage at R non-inverting
R
Voltage at point
point B
B at the V 1 V2 terminal
……….is5.
R+ R+
Figure 5.4: Op-amp as an = R + R 13
Adder (Non-Inverting) 1 1
Voltage at point B =2 V1 + V2 V1+ ………. 5.
V2 14
=
RF V1+V2
2
Therefore, output voltage of an adder is : V0= (1 + R ) ( ) ……………………………5. 2
15
If [ 1+ (RF / R) ] = 2 then, the output voltage, VO = (V1 + V2). 2
Hence, the output voltage is equal to sum of the input voltages, the circuit is called as non-inverting summing
amplifier.

OPAMP AS AN INTEGRATOR:
Circuit diagram of basic integrator is shown in Figure 5.5.
A circuit in which output is the integral of input is the
IO CF
integrator or the integration amplifier. Integrator circuit is
RIN 2 +VCC obtained by using a basic inverting amplifier
V2  7 6
741 configuration
IIN
VIN + 4
V1 3 VO if the feedback resistor is replaced by a capacitor CF. VIN is the
VEE
input voltage applied to the inverting terminal and non
inverting terminal is grounded. IO is the output current and VO is the
Figure 5.5: Basic
Integrator output voltage.

When
Output voltage VO is the voltage across the capacitor CF and the Vby
is given IN is applied,
the a current IIN flows through RIN and is given
relation:
1 by equation: IIN = VIN / RIN ------------------5.16 For the op-amp in
VO = V€ =F ∫ O dt ………………………………….5.18
inverting mode: IIN = − IO ------------5.17
Since, IIN = − IO; we have:
1
VO = V€ =F ∫ −IN dt ………………………………….5.19
From the equation 5.16 we have:
1 VIN
VO = ∫ − dt ………………………………….5.20
F
RI
1 N
Therefore, V0 = ∫ VI d ………………………………………………………. 5
. 21
INC
F N
−R
Here, RIN and CF are constant. Hence, V0 ∝ ∫ VIN d
In Integrator, if input is sine wave then cosine wave output or if input is square wave then triangular wave
output.
FREQUENCY RESPONSEOF INTEGRATOR: Frequency response of basic integrator is shown in figure 5.6, here fb is
the frequency at which the gain is 0dB and is given by, fb = (2RC
1
IN F
) the stability and the low-frequency roll-off problems can be corrected by the addition of the resistor RF as shown in the
Bothe
practical integrator circuit of figure 5.7.

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RF
Gain in
dB IO CF
100 Basic Integrator
RIN 2
Response 
V2 +VCC
6
80 Ideal Response of
IIN
7417
Practical Integrator VIN + 4
60 (RF/R IN) dB V1 3 VO
VEE
40 Actual Response of
20 Practical Integrator
Figure 5.7: Practical
10 102 103 105 Frequency in
=fa =fb Integrator
Hz
Figure 5.6: Frequency response of
Practical Integrator

The frequency response of an ideal practical integrator is shown by broken lines in figure 5.6. In this case , f is
some relative operating frequency, and for frequencies f to fa the gain RF / RIN is constant. After fa the gain decreases at a rate of 20

dB/decade. 1
integrator.This
The means
gainthat between
limiting fa and fb, fa
frequency theispractical
given by integrator
f = behaves)as an
a 2R C
F
( F
Usually the value of fa and in turn (RIN.CF) and (RF.CF) values should be selected such that fa < fb. The input signal
will be integrated properly, if the time period T of the signal T S(RF.CF) where RF.CF = 1/ 2π.fa
Integrator is most commonly used in analog computers and analog to digital converters and signal-wave shaping
circuits.

OP-AMP AS DIFFERENTIATOR:
Figure 5.8 shows the basic differentiator or differentiation amplifier. The circuit which performs the mathematical
operation of differentiation ie. the output waveform is the derivative of the input is the differentiator. Circuit
may be constructed from a basic inverting amplifier if an input resistor RIN is replaced by capacitor CIN.
CF
IO RF
CI +VCC IO
2 RF
N V2  7 RIN CI 2
741 6 N V2  6
VIN IIN = + 4 741+VCC
V1 3 VO
IIN = V1 + 47
IC VEE VIN 3 VO
IC VEE

Figure 5.8: Basic Figure 5.9: Practical

Differentiator Differentiator
When VIN is applied, a current IC flows through CIN and is given by equation: IIN = IC =CIN d/dt (VIN) --------5.22 For the op-amp in

inverting mode: IIN = − IO ------------5.23 and output current, IO = VO/RF ----------------- 5.24 Using equations 5.23 and 5.24 in
equation 5.22, we−V
have:
O d d
RF . =(V
IN.)
d
t IN ie. V0= −(CI.
N RF)
d
IN d
Since RFand C are constant, therefore
( V ) V0 ∝ d I
IN N
OV
This relationship indicates that the output voltage V( of an)op-amp differentiator circuit is proportional to the derivative of the input

voltage. If the constant of proportionality is made equal to 1, then VO will be equal to the derivative of the input voltage VIN. In

differentiator, if input is cosine wave then sine wave is the output or a triangular wave input will produce a square wave
output.
The differentiator is most commonly used in wave shaping circuit to detect the high-frequency components in an
input signal and also as a rate-of-change detector in FM modulators.
FREQUENCY RESPONSE OF DIFFERENTIATOR:
However the differentiator in figure 5.8 will not perform the differentiation because of certain instability in
the no: 20
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input impedance XCIN decreases with increase in frequency, which makes the circuit susceptible to high frequency noise. When
amplified, this noise completely override the differentiated output signal.

Frequency
Gain in differentiator is shown in figure 5.10. Here, fa is the
100
dB frequency at which the gain is 0dB and is given by:
response
80 Basic Differentiator Response: 1
20dB/Decade fa= (
60 of 2R C F
Actual Response of )
Also, fc is the unity gain-bandwidthIN of the op-amp.
40 Practical Differentiator:
Both
basic the stability and high frequency noise problems
20 can be corrected by the addition of two components:
fb
fa and
RIN and CF as shown in figure 5.9 and the frequency response
0
-20 is shown by dashed lines in figure 5.10. From frequency
practical
f 10 10 2 10
3
10 4 105
f to fb, the gain increases at 20dB/decade, after fb, gain
Frequency in
Hz decreases by the same rate. This 40db/decade change in
Figure 5.10: Frequency response of
gain is caused by the (RIN.CIN) and (RF.CF) combinations.
Practical Differentiator
1
This gain limiting frequency fb is given by: fb = (2R INC ) where (RIN.CIN) =(RF.CF). Thus (RIN.CIN) and (RF.CF) help
to reduce the effect of high-frequency input, amplifier
IN noise and offsets. It makes circuit more stable by
preventing the increase in gain with frequency. Generally the value of fb and in turn (RIN.CIN) and (RF.CF) should be selected such that fa

< fb < fc f = 1 1
Where a 1 ); fb = (2RC ) = ) ; fc = unity gin-
2RCF IN IN IN 2R C
F
( F ( bandwidth
The input signal will be differentiated properly if the time period, T S (RF. CIN )

OP-AMP AS AN INSTRUMENTATION AMPLIFIER:

Instrumentation amplifier is intended for precise, low level signal amplification where low noise, low thermal
and time drifts, high input resistance and accurate closed loop gain are required.
RT ± ΔR R
+VCC
F
 R1
R A1 +VCC
C 
+ + A3
VDC - VAB
VB VA VEE + VO
R VEE
R
B VAB  +VCC
A
A2 Mete
RL r
+ R2=R1 R3 F
VEE
=R
Figure 5.11: Differential Instrumentation Amplifier using a Transducer bridge

Besides, low power consumption, high CMRR and high slew rate are desirable for performance. Figure 5.11
shows the differential instrumentation amplifier using transducer bridge. A resistive transducer is connected in
one arm of the bridge (RT±ΔR) whose resistance changes as a function of some physical energy, where RT is the transducer
resistance and ΔR is the change in resistance.RBThe
.VD€bridge is DC excited but can also be AC excited.
R€ ForRT the bridge
be balanced the condition is that: V = RA.VD€ on solving the equation we have: =
to A
ie. R€+RB = RT+RA RB
V B
Generally RA =RB=RC=RT when the bridge is balanced.RWhen
A the physical quantity to be measured changes, the transducer resistance also

changes and the bridge is unbalanced ie. VA ≠ VB . The output voltage of the bridge can be expressed as a function of the change
in transducer
Therefore resistance.
by voltage divider rule, we have: V A D€
and
A B=
R+(R
RA .VT+∆R)
= V RB.VD€
RB+R€
Therefore the voltage VAB across the output terminal of the bridge is, VAB = VA - VB
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If RA=R=R
B =R
C then we have the expression for the output voltage as: V A = −∆R.
2.
T B
The negative sign indicates that VB >VA due to increase in value of RT. (V(2R+∆
€)
D
R)
The output voltage of the bridge is applied to the differential instrumentation amplifier consisting of three op-
amp
as shown inamplifier
differential figure 5.11. Two
is: (−RF/ R
voltage followers help to avoid loading
1 ). Therefore the output voltage O V=V of the bridge circuit. The gain of the
AB (−RF/ R ) ie 0 = −∆R.(VDC)
basic 2.
V 1
(−RF ()
2R+∆R).R1
Since ΔR is very small (2R+ΔR)≈ (2R), therefore, 0 = ∆R.(VDC)
(4R).R
V
From this equation it is observed that VO is directly proportional
(RFto
)1change in resistance ΔR, hence a change in
physical energy can be easily measured.
Applications of Instrumentation Amplifier:
1. Temperature Indicator.
2. Temperature controller.
3. Light intensity meter.
4. Measurement of flow and thermal conductivity.
5. Analog weight scale.

DIFFERENTIAL INPUT AND DIFFERENTIAL OUTPUT AMPLIFIER:

This amplifier is most commonly used as a preamplifier and in driving push-pull arrangements. Figure 5.12
shows the circuit diagram of differential input and differential output amplifier.
Circuit consist of two identical op-amps. The analysis of
R1 circuit can be accomplished by determining the output of
+VCC each op-amp due to differential input.
RF 
A1 VOX Using superposition theorem, output VOX due to inputs VX
+ R
+VX + and VY is given as- O = (1 +R ) X − ( ) F
R1 R1
VEE X
Similarly, the output VO is- OF = (1 + ) F− (R)
R

VO Y R1
X
VIN R1
R1 R However, the differential output VO is- VO =
F
+VCC
 ─ VOX ─ VOY
A2
VOY 2 F
─ + Therefore substituting V )
V0 = (1 + 2RF)X
R1 Vand
(OX −VV
Y OY in
) above
=R(1 +
VY IN
VEE This means
equation Rthat
we get-
1 the differential input)and output are in
Figure 5.12: Differential input phase. This amplifier is useful in noisy environment,
(V
and Differential output especially if the input is relatively smaller, because it rejects
amplifier the common mode noise voltages.

VOLTAGE SERIESFEEDBACK AMPLIFIER:

This is basically a practical non inverting amplifier with feedback also called as closed loop non inverting
amplifier.
Op-amp is in forward path while the feedback circuit
+VCC consists of the resistances R1 and RF. Input is applied to non-
V1 +
A
Vi + inverting terminal. Voltage across R1 is the feedback voltage Vf.
-
V2
VEE Vf is given to inverting terminal which opposes the input
V R voltage by 180° which ensures that feedback is
VO
S
+ R
F
L negative.
Vf R1
- - Closed loop voltage gain, Af = VO / VS Open

Feedback circuit loop voltage gain, A = VO / Vi

Figure 5.13: Voltage Series where Vi (Difference of input voltage) = V1
feedback amplifier
– V2

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Closed Loop Voltage gain of voltage series feedback amplifier:

As defined, Af = VO / VS

R1.
The output voltage Vo = A.Vi = A (V1 −V2) ...............................................................
VO ……………………………5.25 ……………5.26
From figure 5.13, V1 = VS and V2 = Vf = R1+R
F
Substituting the value of V1 and V2 in equation 5.25 and rearranging, we get
= . S(1 + ) O
1 + +1
Thus
,
=O = . (1 + )
S 1+
…1………………….5.27
+

Generally, A is very large (typically 105). Therefore (A.R1)>> (R1+RF) and (R1+RF+A.R1)≈ A.R1
Thus,
= VO = 1 + R1(Ideal) .............................................................................5.28
f
VS
RF
Since the feedback factor, β = Vf / VO
Thus from equation 5.26, β =VOVF = R1………………………………………. .5.29
1
Comparing equation 5.27 and R 1+RF
5.28, we can conclude that: = (Ideal) .......................5.30

Closed loop voltage gain in terms of open loop gain A and feedback factor, β as follows:
Rearranging the equation 5.27 we get:
V R +
( R11 +
f= O
V= R R RFF
1 +FR R1
) F +R1
S
R 1 + R +
Using equation 5.29, we RF
get: V0
Af =A VS = 1 + (A ……………………………5. 31
.)
Where, A = open loop voltage gain; Af = closed loop voltage gain; β= gain of feedback circuit; (A.β)= loop gain

Input Resistance with feedback(Rif) of voltage series feedback amplifier:

Figure shows the voltage series feedback amplifier with the op-amp equivalent circuit.

+ Ri= Open loop input resistance of op-amp

V1
Ii
+ + RiF= input resistance with feedback
+ +
Vi ─
VS Ri
─ ─ R
─ A.Vi o

V2
─ +
Vo R
─ L
+ R
Vf
F
─ R1
Rif
Figure 5.14: Voltage Series Feedback with op-amp equivalent circuit (Input
Resistance)

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The input resistance with feedback is defined as- i = VS = VS

Ii
R VO f
However, Vi =AA and V VS (ViR ⁄ i)
= O 1+Aβ
Therefore, Rif = Ri (1+Aβ)........................................................................5.32
From equation 5.32 we conclude that the input resistance of op-amp with feedback is (1+Aβ) times that
without
feedback.
Output Resistance with feedback (Rof) of voltage series feedback amplifier:
Output resistance is the resistance determined looking back into the feedback amplifier from the output
terminal as shown in figure 5.15.

+
Ri = Open loop input resistance of op-amp RoF =
V1
+ + Ia Output resistance with feedback
VS =0V +
i
─ R Ro ─
V ─ A.Vi IO
i Ib B
+
V2
─
Vo
─

+ R
Vf Ro
F
R1
─ f

Figure 5.15: Voltage Series Feedback with op-amp equivalent circuit (Output Resistance)

Output resistance is obtained by using Thevenin’s theorem, by making VS = 0V, and by applying external voltage Vo.

Rof is defined as; Rof = VO / IO .....................................................................5.33

Applying KCLat output node B, we get IO = Ia + Ib

Since, Ia >> Ib. Therefore, IO ≈ Ia

Applying KVLfor the output loop- we get, VO ─RO.IO ─A.Vi = 0
Therefore, VO − .
O =
ViRO
However, Vi = V1 ─V2 = 0 ─Vf (since, VS = V1 = 0V and V2 = Vf )
Therefore,
R1.
Vi = − = −βVO
V +
1O
Therefore FR
R
, VO + β.
O =
VO RO
Substituting the value of IO in equation 5.33, we get
R0
Rof = ………………………. 5. 34
1+A .
Equation 5.34 shows that the output resistance with feedback is [1/(1+Aβ)] times the output resistance RO of the op-amp ie. the
output resistance with feedback is much smaller than the output resistance without feedback.

VOLTAGE SHUNT FEEDBACK AMPLIFIER:

It is also called as inverting amplifier with feedback. Figure 5.16 shows the voltage shunt feedback amplifier.
Input voltage is applied to inverting terminal and amplified as well as inverted output signal is applied to
inverting input
via feedback resistor RF and this arrangement forms a negative feedback. Non inverting terminal is grounded.

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Closed Loop Voltage gain of voltage shunt

+VCC feedback amplifier:
V1 +
A From figure 5.13, writing KCLat input node V2,
R1 V2 Vi - ─ IS = IB + If ......................................................... 5.35
+
I VEE Input bias current is very small because very high
V IB input
─ S R VO
S
If R L
F impedance
VS−V2 V(R i). 0
2−V
+ = ..............................................5.36
R1 RF
Therefore , IS ≈ If
Since, the output voltage Vo = A.Vi = A (V1 −V2) ............. 5.37 (V1 −V2) =
Feedback circuit
Figure 5.16: Voltage Shunt Vo / A Since, V1 = 0V
feedback amplifier
Substituting the equation 5.38 in equation 5.36, we Therefore , (V2) = ─(Vo / A) ....................................5.38
get O
= =− (ec) ……………………………. 5.39
S 1 + + 1
Since, the internal gain A of op-amp is very large, A.R1 >>R1 + RF Hence,
equation 5.39 can be rewritten as-
O
= =− (ide) …………………………….
5.40
S 1
This equation shows that gain of inverting amplifier is set by values of feedback and input resistors. The
negative sign indicates that input and output is out of phase by 180°.

Input resistance with feedback of voltage shunt feedback amplifier:

R1 ─ Ri= Open loop input resistance of op-amp

V2
+ + + RiF= input resistance with feedback
Vi
+
V Ri
─ ─ Ro ─
S
─ A.Vi
1+ V1
+ .
R
1+ L

Ri
f

Figure 5.17: Inverting amplifier with Millerized feedback resistor

Millerize the feedback resistor RF; ie. splitting the RF into two miller components as shown in figure 5.17 to find the input
resistance.
RF
From the circuit, the input resistance with feedback Rif is then , if R= R + 1+ //( )i
1
Output resistance with feedback of voltage shunt feedback A
amplifier:
The equivalent circuit for output resistance with feedback Rof of inverting amplifier is same as that for non inverting amplifier
because the output resistance of inverting amplifier must be same to that of the non inverting amplifier.
R0
Rof = ………………………. 5. 41
1+A
.

LOGARITHMIC AMPLIFIER:
Figure 5.18 shows the circuit diagram of logarithmic amplifier. The output voltage is always proportional to
the natural logarithm of the input voltage, hence called as logarithmic amplifier. Basically circuit is an
inverting
amplifier in which feedback resistor RF is replaced by a p-n junction diode D. For satisfactorily operation of this amplifier, diode
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has to be forward biased, so the input signal must have positive values only.
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Mathematically, diode current equation is given as:

D = R. [(e(VDV⁄ T))− 1]
IO
R 2 +VCC Where, I is diode current, IR is diode reverse saturation current,
i V2  7 6
741 VD is the applied voltage and VT is the volt equivalent of
VIN Ii
3
+ 4 VO temperature.
V1
VEE
When diode is forward biased, VD >>> VT, hence
(e(VDV⁄ T)) ≫ 1
Figure 5.18: Logarithmic Therefore,
Amplifier = R. [(e(VDV⁄ T))] ………………………5.42 From
the circuit diagram, using the virtual ground concept, we
(VD V
⁄ ))
So, = − R. ] ………………………………….5.43
R T
[(e have: Ii = ─ IO
But,
V
voltage across diode D is equal to output voltage V O. Hence, equation 5.43 becomes
I
N
R
=− R . (VOT V ⁄ )
)] ………………………………….5.44
i
[(e
Taking natural logarithm on both sides, we
have V
VI
ln [Ni
] =−
OT[ ]
R V
Hence R
………………………………….5.45
,
V0 = −V . nV[I ] ……………………. .
R i
5.46
T N
IR
From equation 5.46, since VT, IR and Ri are constants, then VO is directly proportional to natural logarithm of VIN.

ANTILOGARITHMIC AMPLIFIER or EXPONENTIAL AMPLIFIER:

Antilogarithmic amplifier is obtained by changing the position of diode D and resistor Ri in a logarithmic amplifier, as shown in
figure 5.19. The output voltage of this amplifier is always proportional to the antilogarithmic of the input
voltage. For satisfactorily operation of this amplifier, diode has to be forward biased, so the input signal must
have positive values only. Mathematically, diode current equation is given as:
R = R. [(e(VDV⁄ T))− 1]
IO
D Where, I is diode current, IR is diode reverse saturation current,
2 +VCC
V2  7 6
741 VD is the applied voltage and VT is the volt equivalent of
VIN ID
3
+ 4 VO temperature.
V1
VEE
When diode is forward biased, VD >>> VT, hence
(e(VDV⁄ T)) ≫ 1
Figure 5.18: Antilogarithmic Therefore,
Amplifier = R. [(e(VDV⁄ T))] ………………………5.47
Therefore,
N = D = R. [(e
(
VDV⁄ T))] ………………………5.48
But the diode voltage VD is equal to the input voltage VIN, therefore
I

N
I = D = R. [(e(VINV⁄ T))]
From the circuit diagram, using
⁄ ) the virtual Oground concept, we have: IIN = ─ IO
V
Therefore, R. (VIN V
T )] = − ( R ) i e.0V= −(I . R)(e(VINV⁄ T))…………………….
[(e R
5. 4
From equation 5.49, Since VT, IR and Rare constants, we have output voltage VO is directly proportional to antilog of VIN.
TRIANGULAR WAVE GENERATOR:
Triangular wave generator, as shown in figure 5.19 can be formed by connecting the output of square wave
generator to an integrator. The frequencies of the square wave and triangular wave are the same.
The frequency of triangular wave will increase or decrease as resistor R increases or decreases. Although
the
amplitude of the square wave is constant (±Vsat); the amplitude of the triangular wave decreases with an increase
Paigneitsnofr:equ2e6ncy and vice versa as shown in fiFguolrelo5w.21u.s Tohne ifnapcuetbtoookthteoingteetgrarteoarli-staim
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output is a triangular wave. For a perfect triangular wave output the circuit time constant (5.R3.C2) > T/2, where T is the time
period of the square wave input. The output frequency is limited by the slew rate of the op-amp. Therefore, for
generation of relatively higher frequencies, high slew rate op-amp are used.
C R
C2 +VCC C1
2 +VCC 7
7
–
– 2 + 2 +
2 A1 R1
V 6 V
3 R C C
3 6 + 4 VO’
A1 3 7
C VO 3 7
C VO
– 3  –
+ 4
R1 VO ’ A2
P V
A2

VEE 6 E 6
R R2 E
+ 4 + 4
O
M
 R3 
R2
Another triangular wave generator, with fewer V V
components is shown in figure 5.20. Op-amp A1 operates as a comparator and A2 as an
E E
E E
integrator. The voltage drop
Fig across R2 appears at the point Pwhich is the actual input appearing at the non-inverting terminal of op-amp
Figure 5.20
A1. This voltage at pointure
P continuously compared with the voltage at inverting terminal of op-amp A1, which is at ground potential.
5.1
9 Pis positive and greater than the potential at inverting terminal, the output voltage swings
When the potential at point
to positive saturation, where as potential P is negative the output voltage
Circuit swings
operation: Let to
thenegative
output of saturation.
op-amp A1 is at +VSAT
VO’ VO
(+VCC). This +VSAT is an input to integrator A2. The output
+Vsat of A2, therefore will be negative going ramp. This
+VRamp means that the one end of the voltage divider R2-
R3 is at +VSAT of A1 and the other end is the negative
0 t going ramp of A2. When negative going ramp
attains a certain value
─VRamp , point P potential becomes negative and the
─VRamp
output amplifier A1 swings from positive saturation to
─Vsat
Figure 5.21 negative saturation. The output of op-amp A2 will
now start increasing until it reaches a voltage level equal
This process repeats and the triangular wave output gets generated
to +Vas shown
Ramp in figure
. At this 5.21.ofThe
value thetriangular
output, and
the
square wave output frequencies are same and the amplitudes ofpotential
square wave is proportional to the saturation
at point P becomes positive forcing the
voltages ─VSAT and +VSAT. The amplitude of triangular wave is given as: ─VRampoutput
= ─(R2/Rof
3)(op-amp
+VSAT) andAsimilarly,
1 from ─VSAT to +VSAT.
+VRamp = ─(R2/R3)( ─VSAT) .
Hence the peak to peak (PP) output amplitude of triangular wave is:
VO(PP) = +VRamp ─ (─VRamp) = 2(R2/R3)(VSAT) where VSAT = |+ST | = |−ST |

Above equation indicates that amplitude of triangular wave decreases with an increase in resistor R3. The time period

T of the triangular wave is given by the expression: T = [ (4.R1.R2.C1) / (R3) ]

The frequency of oscillation of the triangular wave is given by: f = 1/ T = [ (R3) / (4.R1.R2.C1) ]

PHASE SHIFT OSCILLATOR: Figure 5.22 shows the phase shift oscillator, which consists of op-amp as the
amplifying stage and three RC cascaded networks as the feedback circuit. Phase shift of 180° is provided by op-
amp which is used in inverting mode whereas additional 180° phase shift is provided by the cascaded RC
networks. Thus the total phase shift around the loop is 360°.

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At some specific frequency, when phase shift of RC network is

R
F
exactly 180° and gain of amplifier is sufficiently large, oscillation
R1 2 7
+VCC occurs at that frequency. The frequency of oscillation is given as:
6 1
741 fo
+ 4 VO
3 = 2RC√6 R
ROM VEE At this frequency, the gain of amplifier must be 29. ie.R|
1
|=
29. the circuit will produce a sinusoidal waveform of
Means,
C C frequency
C fo if the gain is 29 and the total phase shift around the loop is
R 360°.
R R

Figure 5.22: Phase shift

Oscillator

WEIN BRIDGE OSCILLATOR: Oscillator used to generate audio frequency is the

R wein bridge oscillator as shown in figure 5.23. It
C provides frequency stability. Wein bridge is connected
R between the amplifier input terminals and the output
terminals. Bridge has RC series and RC parallel
C + network in two
741 arms and in remaining arms R1 and RF resistors are connected
 VO as shown in figure.
Total phase shift of 360° around the circuit occurs only
when the bridge is balanced ie. at resonance.
R R
1
The frequency of oscillation is given by:
F
1
fo =
2RC
Figure 5.23: Wein Bridge At this frequency the gain required for sustained
Oscillator oscillation is given by A = 1/β = 3
Ie. 1+ (RF/R1) =3 or RF = 2R1.
ANALOG MULTIPLIER-MPY634:
Analog multiplier IC is commonly used to perform various mathematical operations such as voltage divider,
frequency doubling squaring, square rooting etc.
Basic multiplier and its characteristics:
+15V ─15V
Basic multiplier is an active circuit in which output voltage is
proportional to the product of input signals.
Output of multiplier is : VO = K.V1.V2 where, K= 1/(Vref) Usually
x+V ─V Vref is set to 10V internally, hence,

V1 y X OUT
VO = (V1.V2) / 10 .................................. 5.50
VO
V2 GND If, (V1.V2) < Vref, the output of multiplier will not saturate.
Depending upon the polarity restriction of the inputs, the IC
operation is called as-
Figure 5.24: Multiplier IC a)One Quadrant multiplier: In such operation, polarity of
Symbol inputs must
b)Two quadrant Multiplier: This multiplier functions properly, always
if one inputbe
is positive.
held positive and the other is
allowed to swing in both positive and negative.
c)Four Quadrant Multiplier: This multiplier functions properly, if both the inputs are allowed to swing in both
positive and negative directions.

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1) In communication, it is used in amplitude modulation, frequency modulation, phase modulation etc.

2) In instrumentation and control, to measure velocity, acceleration, automatic gain control etc.
3) For voltage controlled applications.
4) It is used for voltage divider, true RMS calculation etc.
5) Used for frequency converters, frequency doubling etc.
6) It is used for squaring, square root calculations and solving non-linear equations.
7) It is used in oscillators.

Voltage Divider using Multiplier:

Figure 5.25 shows the voltage divider circuit using multiplier. Voltage divider is the circuit in which the output is
the division of two input signals. As shown in figure the multiplier is used in feedback loop. Denominator is
applied to X input of multiplier and denominator at inverting input of op-amp.
Node A and B is at same potential, due to virtual
VZ x V2
R ground concept ie VA = VB = 0V. As input is applied to
X Denomina
IN
y inverting terminal, so, IN = ─IZ .
R IZ tor
VN  Therefore, (VN/R) = ─(VZ/R) Since ,
Numerator B V1
A + VO VZ = K.V1.V2 and V1 = VO

Hence, (VN/R) = ─[K.VO.V2 /R]

Figure 5.25: Voltage Divider Circuit Therefore, VO = ─[ VN / (K.V2)]
using Multiplier Thus the output is
proportional to the division
of
Squaring Circuit using Multiplier: two input voltages VN and V2. Input voltage V2 is negative,
Figure 5.26 shows the circuit diagram of squaring circuit using
hence divider circuit are two quadrant circuits.
multiplier. Squaring circuit gives the square of the input
+15V ─15V
voltage applied.
From figure, same input voltage (V1) is applied to both the
x+V ─V input terminals of multiplier. Hence the output
y X OUT
2 voltage is given as, VO = K. (V1)2
V1
VO = K(V1)
G Thus the output is proportional to the square of
N the input.
D
Figure 5.26: Squaring Circuit using
Multiplier
VOLTAGE CONTROLLEDOSCILLATOR (VCO):
In some applications such as frequency modulation, frequency shift keying, where the frequency is controlled by
an input voltage (also called control voltage). Such type of frequency control is achieved in voltage controlled
oscillator (also called voltage to frequency converter).

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+V 1: Ground
2: NC
3: Square Wave Output
R1 4: Triangular Wave
Output
Square Wave 5: Modulation input
Modulation 6 8 6: R1
3
5 Current Schmitt 7: C1
Buffer 8: +V
Triangular Wave
4

Buffer

7 1
C1

Figure 5.27 showsFigure

the block diagram
5.27: of 566 VCO.
Block diagram Triangular
of 566 VCO wave output is generated by charging and
discharging of capacitor C1 ,by current sources. A charge and discharge level are determined by Schmitt trigger
and also provides square wave output. Both the output waveforms are buffered so that the output impedance
of each will be equal.
+V Pin3
O/P
R R
2 C2 1

6
4
Triangular Wave
566 VCO
C 8
V 5
Modulatio C Pin4
n
R 3 O/P
3 Square Wave
7 1

C
1
t

Figure 5.28: Connection diagram of 566 Figure 5.29: Output Waveforms of 566
VCO VCO
Figure 5.28 is the connection diagram. R1C1 combination provides the free running frequency. Control voltage VC is set by voltage divider

formed by R2 and R3. The modulating signal is ac coupled with capacitor Cand must be less than 3VP-P. The frequency of oscillation of

output waveforms is given by:

fO ={ [ 2 (+V ─ VC)] / [R1C1(+V)] }

where, 2kΩ < R1 < 20kΩ and [ ( ¾)(+VC)] SVC S+V. For the fixed value of VC and constant C1, fO can be carried over a 10:1 frequency

range by choosing R1 between 2kΩ and 20kΩ. Similarly, for constant R1C1 product, fO can be modulated over a 10:1 range by the

control voltage VC.

If VCO has to drive standard logic circuitry, dual supply of ±5V is used, so that square wave output has a proper
DC
level.
Applications of VCO:
1) FM modulation. 2) Frequency Shift Keying. 3) Signal generation (Square and Triangular) 4) Function
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COMPARATOR:
An open loop op-amp, which compares a signal voltage on one input with the known voltage (reference voltage)
on other input of op-amp is called a comparator. Output of comparator may be +VSAT and ─VSAT, depending on which input is
largest. Comparators are used in circuits such as Schmitt triggers, voltage level detectors, oscillators and digital
interfacing.

+VCC +VREF INPUT

─ INPUT
D1 D2 0 0
−VREF t
741 t
+
VIN>+VREF
+VSAT
VO +VSAT VIN>+VREF OUTPUT
R =R OUTPUT 0
─VEE 0 t
OM R
+ t ─VSAT
+ ─VSAT
VREF VIN<+VREF
─ VIN
─ VIN<+VREF
Figure 5.32: Output for ─VREF
Figure 5.31: Output for +VREF
Figure5.30
Figure 5.30:shows
Non-Inverting
the circuit diagram of non-inverting comparator. From the circuit diagram, a fixed reference
Comparator
voltage is applied to inverting terminal of op-amp and a time-varying sinusoidal signal is applied to non-inverting
input, hence the circuit is called as non-inverting comparator. Here the reference voltage VREF is positive. When the VIN < VREF (ie. voltage

at inverting input is higher than non-inverting input), the output VO is at ─VSAT (≈─VEE). On the other hand, when the VIN > VREF (ie.

voltage at non- inverting input is higher than inverting input), the output VO is at +VSAT (≈+VCC). Thus the output voltage VO changes

from one saturation level to another whenever VIN ≈ VREF,as shown in figure 5.31. Hence, we can say that the comparator is a type of

ADC converter. Diodes D1 and D2 are called clamping diodes because the difference input voltage, Vi of op-amp is clamped to either +0.7V

and

─0.7V. These diodes also protect the op-amp from damage due to excessive input voltage VIN. Resistance R is used to limit the current

through diodes. To minimize the offset problems, ROM≈ Ris connected in between VREF and inverting input of op-amp. Figure 5.32 shows
+VCC +VREF INPUT
─ INPUT
the input and output waveformsDwhen the reference voltage (VREF) is negative.
D1 2 741 0 0
+ t −VREF t

VO +VSAT +VSAT
OUTPUT OUTPUT
─VEE 0 0
R ROM=R t t
+ ─VSAT ─VSAT
VIN +
VIN>─VREF
─ ─VREF VIN >VREF

Figure 5.34: Output for +VREF Figure 5.35: Output for ─VREF
Figure 5.33: Inverting Comparator

Figure 5.33 shows the inverting comparator. Here VIN is applied to inverting terminal of op-amp and Vref is applied to non-inverting
terminal of op-amp. With sinusoidal input waveform, the output waveform for negative reference and positive
reference voltage is shown in figure 5.34 and 5.35.
ZERO CROSSING DETECTOR:
Inverting or non-inverting comparator can be used as a zero crossing detector provided that reference voltage ,Vref is set to zero volts

(Vref = 0V) as shown in figure 5.36. The output voltage VO switches and saturates positively and negatively, whenever input signal VIN

crosses zero volts. Output voltage VO is driven into negative saturation when the input signal VIN passes through zero volts in positive

direction and VO is driven into positive saturation when the input signal VIN passes through zero volts in negative direction as shown in
Page
figureno: 31 output waveform is a square wave.Follow
5.37. The Hence us
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INPU
─ +VCC T
741 0
D1 D2 t
+ VO

R + ─VEE
OUTPU
ROM=R +VSA
T T
VIN ─
Vref = 0V 0
t
Figure 5.37: Input and
Figure 5.36: Zero Crossing ─
Detector output Waveforms
V
S
For low frequency input signal (slowly changing waveform), VIN take more timeA to cross 0V, hence switching at the output will also
T

take time. On the other hand, because of noise at the op-amps input terminals, output fluctuates between +VSAT
and –VSAT, detecting zero reference crossing for noise as well as input VIN. These problems can be cured by the use of positive
feedback or regenerative feedback, that causes the output to change faster and eliminate any false output
transitions due to noise at the input.

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OP-AMP AS FILTERS: Characteristics of filters, Classification of filters, Magnitude and frequency response,
Butterworth 1st and 2nd order Low pass, High pass and band pass filters, Chebyshev filter characteristics, Band
reject filters, Notch filter; all pass filters, self-tuned filters, AGC, AVC using OP-AMP.
TIMER: IC-555 Timer concept, Block pin configuration of timer. Monostable, Bistable and astable
Multivibrator
using timer 555-IC, Schmitt Trigger, Voltage limiters, Clipper and clampers circuits, Absolute value output
circuit, Peak detector, Sample and hold Circuit, Precision rectifiers, Voltage-to-current converter, Current-to-
voltage converter.
Voltage Regulator: Simple OP-AMP Voltage regulator, Fixed and Adjustable Voltage Regulators, Dual Power
supply, Basic Switching Regulator and characteristics of standard regulator ICs.

OP-AMP AS FILTERS (ACTIVE FILTERS):

Filter is a frequency selective circuit that passes a specific band of frequencies and blocks the frequencies outside
this band. Depending on the type of elements used in their construction, filters are classified as active or passive.
Passive filters used passive components such as resistors, capacitors and inductors whereas active filters used
active components such as transistors or op-amps in addition to resistors and capacitors. The type of elements
used dictates the operating frequency of the filter. RC filters are used for low or audio frequency operation,
whereas LC filters are used for RF or high frequency operation. In audio frequencies, inductors are not used
because they are very large, costly and dissipate more power. Inductors also produce magnetic fields.
Advantage of active filter over passive filter:
1. Gain and frequency adjustment flexibility: Active filter containing active components such as op-amp, is capable
of providing a gain, hence the input signal is not attenuated as in passive filter. In addition, active filter is easier
to tune or adjust.
2. No loading problems: Because of high input impedance and low output impedance of op-amp, active filter does
not cause loading of source or load.
3. Cost: Because of absence of inductors and use of cheaper op-amp in filter circuit, active filters are more
economical than passive filters.

TYPES OF FILTERS:
Most commonly type of active filter used are:
(1)Low-pass filter (2) High-pass filter (3) Band-pass filter (4) Band-reject filter (5) All-pass filter

MAGNITUDE AND FREQUENCY RESPONSE OF FILTERS:

All these filters use op-amp as the active element and resistors and capacitors as passive elements. Active
element
Gai improves the filter performance through their increased
Gai slew rates and higher unity gain-bandwidths.
n n Ideal
Ideal Response
1 Response 1

Pass Stop Band Stop Pass Band

Band Frequen Band
fH f Frequen
cy
Figure 6.01: Low pass filter frequency Figure 6.02: High pass cy
L filter frequency
response response

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Gai Ideal Gai

n n Ideal
Response
Response
1 1
Stop Stop Stop
0.70 Band Band Band
Pass Pass Pass
7 0.707
Band Band Band

fL fC fH fL fC fH
Frequency Frequency
Figure 6.03: Band pass filter frequency Figure 6.04: Band reject filter frequency
response response

All type of filter frequency responses are shown from figure 6.01 to
Voltag 6.04 except all pass filters. A dashed curve indicates the response of
e Vin ideal filter whereas solid lines indicate practical filter response.
1 VO Figure
6.01 shows the frequency response of low pass filter. A low pass
filter
t
has a constant gain from 0Hz to fH (high cutoff frequency). Therefore bandwidth is
─1
also fH. After fH the gain decreases by 3dB ie. f > fH the gain decreases with
ᶲ
increase in input frequency. Hence, frequencies between 0Hz and fH are
Figure 6.05: All Pass
Filter known as pass band frequencies, whereas beyond fH includes stop band frequencies.

An ideal filter has zero attenuation in pass band and infinite attenuation
Some of the commonly used practical filters thatband.
in stop approximate thecircuits
Practical ideal filter
cannotresponse are:the
produce (i) ideal
Butterworth filter
response,
(ii) Chebyshev filter (iii) Cauer filter
but a close ideal response can be obtained by using special design
Butterworth filter also called as flat-flat filter becauseprecise
techniques, it has flat stop andvalues
component pass band. Chebyshev
and high filter has a ripple
speed op-amps.
pass band and flat stop band, while the cauer filter has ripple pass and stop band.
Figure 6.02 shows a high pass filter with stop band is from frequency (f >0) to frequency (f<fL) while pass band is for frequencies (f > fL)

where, fL is low cut off frequency and f is the operating frequency.

Figure 6.03 shows a band pass filter with pass band is between the two cut off frequencies fH and fL here (fH>fL). The two stop bands are

for frequencies (f>0) to (f< fL) and (f > fH). The bandwidth of the band pass filter, therefore,
is equal to (fH ─fL). fC is the center frequency.
Figure 6.04 shows a band reject or band-stop or band-elimination filter with stop band is between the two cut
off
frequencies fH and fL here (fH<fL). The two pass bands are from frequencies (f>0) to (f< fH) and (f > fL). fC is the center frequency.

Figure 6.05 shows the input (Vin) and output (VO) signals of all pass filter where there is a phase shift (ф) between input and output
signals as a function of frequency. This filter passes all frequencies keeping input and output voltages amplitude
equal for all frequencies. The highest frequency up to which the input and output amplitudes remain equal is
dependent on the unity gain-bandwidth of the op-amp. At this frequency, the phase shift between input and
output is maximum.
The rate at which the gain of the filter changes in the stop band is determined by the order of the filter. For
example, for first order filter, the roll-off rate in stop band is 20dB/decade, on the other hand, for second order
filter, the roll-off rate in stop band is 40dB/decade.

FIRST ORDER LOW PASS BUTTERWORTH FILTER:

Figure 6.06 (a) and (b) shows the circuit diagram of first order low pass butterworth filter and frequency response
plot. Here op-amp is used in non-inverting mode and RCnetwork for filtering. Resistance RIN and RF determine the gain of the filter.
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R Gai
RIN F +VCC
2 7 n ─20dB/ deca
V2  6 de
741 AF
R V1 0.707AF
3
+ 4 VO
C
VEE
VIN Pass Stop Band
Band Frequen
fH
cy
Figure 6.06(a): First order low pass Figure 6.06(b): Frequency
filter response
According to the voltage divider rule, the voltage at the non-inverting terminal (across the capacitor
C)=is −jX Where, j = √-1 and −j = therefore =
1 1 N
R−jX j2 1+j2R
1
And the output voltage, VO = [1 + (RF/RIN)] V1 ie. VO = [1 + (RF/RIN)] [VIN / (1+j2π.f.R.C)] OR
VO/VIN = AF / (1+j2π.f.R.C) = AF / [(1+j(f/fH)] where, (VO/VIN ) is the gain of the filter as a function of frequency. AF = [1 +
(RF/RIN)] = pass band gain of the filter, f is the frequency of input signal.

fH = 1/(2π.R.C) = high cutoff frequency of the filter.

The gain magnitude and phase angle equation is obtained by converting equation (VO/VIN ) into its equivalent polar form, as
V0
follows- | |=
AF
VIN √1 +
f
and ∅ = − an ( ) where ф is the(phase
−
1
f⁄fH)angle
2 in
fH
degrees.
The low pass filter operation can be varied from the gain magnitude equation as
shown:
(i) At very low frequencies, ie, f < Hf , |VIV0 | F
≅ N
(ii) At f = f H, |VVION| = AF = F

0.707 H √2
(iii) At f > f , |VVINO | <F
A low pass filter has a constant gain AF from 0Hz to the cutoff frequency fH. At fH the gain is 0.707AF, and after fH it decreases at a
constant rate with an increase in frequency ie, when the frequency is increased tenfold (one decade), the
voltage gain is divided by 10 ie the gain decreases 20 dB (= 20 log 10) each time the frequency is
increased by 10. Frequency fH is known as high cutoff frequency or ─3dB frequency or break frequency or corner frequency.
FIRST ORDER LOW PASS FILTER DESIGN STEPS:
(i)Choose a value of high cutoff frequency fH.
(ii) Select the value of C less than or equal to 1μF. Mylar or tantalum capacitors are used for better
performance.

(iii)Calculate the value of Rusing : R= 1 / (2π. fH. C)

(iv)Select the values of RIN and RF depend on the desired pass band gain AF using AF = [1 + (RF/RIN)] Example:
Design a low pass filter at a cutoff frequency of 1 kHz with a pass band gain of 2. Solution: fH = 1

kHz. Assume C= 0.01μF. Then, R= 1 / (2π. fH. C) = 1 / (2π)(103)(0.01μF) = 15.9kΩ Since the pass band gain is 2, resistors

RIN and RF must have equal values. Let RIN and RF is 10 kΩ.
Original cutoff frequency
FREQUENCY SCALING: Frequency1scaling
kHz is the procedure used to convert an original cutoff frequency fH to a new cutoff frequency fH’.
= 0.625 . Therefore, new resistor R = (15.9 kΩ)(0.625) = 9.94 kΩ.
new cutoff frequency 1.6
=kHz
Scalinthe
Thus g is done by multiplying
new cutoff frequencyRor C,’ but
is fH = 1 /not both,
(2π. R. C)by
=1the
/ ratio of the original
(2π)(9.94x10 = 1.6 frequency
cutoff
3)(0.01μF) kHz. to the new cutoff frequency.
For example,
Page no: 35 to change a cutoff frequency from 1kHz us
Follow to 1.6kHz, multiplyto15.9
on facebook getkΩreal-time
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SECOND-ORDER LOW PASS BUTTERWORTH

FILTER:
R Gai
F
RIN 2 +VCC n ─40dB/decad
V2  7 6 e
741 AF
R2 V1 + 4 VO
R1 C1 VEE 0.707AF
VIN 3
C2 Pass Stop Band
Band Frequen
fH
cy
Figure 6.07(a): Second order low pass Figure 6.07(b): Frequency
filter response
Figure 6.07 (a) and (b) shows the circuit diagram of second order butterworth low pass filter and frequency
response plot. It consists of two RCnetworks for filtering and op-amp used in non-inverting mode. Resistance RIN and RF determine the

gain of the filter. Roll off of 40dB/decade is obtained in frequency response of second order low pass filter. The high cut off frequency fH

is determined by R1,C1,R2,C2, as follows-

fHV0
|A= |1 / 2π.√( RF1. C1. R2. C2) If R1= R2=R and C1 = C2= C, then fH = 1 / (2π.R.C)
H4 where AF = [1 + (RF/RIN)] = pass band gain of the filter and f is the frequency of input signal.
For
=VINa second-order low pass butterworth filter response, the voltage gain magnitude equation is
√1+(f⁄ )

SECONDORDER LOW PASS FILTER DESIGN STEPS:

Design steps of second order low pass filter is same as first order low pass filter, except having twice RC network.

(i)Choose a value of high cutoff frequency fH.

(ii) Select the value of C S 1μF. Mylar or tantalum capacitors are used for better performance. To simply design
calculations, set R1= R2=R and C1 = C2= C

(iii)Calculate the value of Rusing : R= 1 / (2π. fH. C)

(iv)Because of the equal resistor and capacitor values, the pass band gain AF using AF = [1 + (RF/RIN)] of second

order low pass filter has to be equal to 1.586 ie. RF = 0.586 RIN. This pass band gain is necessary for butterworth response. Hence select

the value of RIN S100kΩ and calculate the value of RF.

Example: Design a second order low pass filter at fH = 1kHz.

Solution: fH = 1 kHz. Assume C1 = C2= C= 0.0047μF.Then, R1= R2= R= 1/(2π.fH.C) = 1/(2π)(103)(0.0047μF) = 33.86kΩ

Since the pass band gain is 1.586, hence RF = 0.586 RIN and let RIN = 27 kΩ. Therefore RF = 15.82 kΩ. Hence, the

required components are RF = 15.82 kΩ, RIN = 27 kΩ, C1 = C2= C = 0.0047μF and R1= R2= R= 33.86kΩ.
FREQUENCY SCALING: Frequency scaling method of second order low pass filter is same as of first order low pass
filter.

FIRST ORDER HIGH PASS BUTTERWORTH FILTER:

Figure 6.08 (a) and (b) shows the circuit diagram of first order high pass butterworth filter and frequency
response plot. High pass filter is formed by interchanging frequency determining resistors and capacitors in low
pass filter. Here op-amp is used in non-inverting mode and RCnetwork for filtering. Resistance RIN and RF determine the gain of the
filter.

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R Gain
RIN F +VCC
2 7 20dB/decade
V2  6
741 AF
V1
+ 4 VO
C 3
0.707AF
R
VIN VEE
Stop Band
Pass
fL Band Frequen
cy
Figure 6.08(a): First order high pass Figure 6.08(b): Frequency
filter response
Figure 6.08(b) shows a frequency response of first order butterworth high pass filter with a low cutoff frequency
of fL. At fL the magnitude of gain is 0.707AF. All frequencies higher than fL are pass band frequencies with the highest frequency
determined by the close loop bandwidth of the op-amp. The gain increases at a rate of 20db/decade.
O
Output voltage VO is given by expression: VO = [1 + (RF/RIN)] [(j2π.f.R.C .VIN) / (1+j2π.f.R.C)]
R
VO/VIN = AF / (1+j2π.f.R.C) = AF { j(f/fL) / [(1 + j(f/fL)]

where, (VO/VIN ) is the gain of the filter as a function of frequency.

AThe
F =gain
[1 + magnitude
(RF/RIN)] =equation
pass bandisgain of theby
obtained filter, f is theequation
converting frequency
(Vof
O/Vinput signal
IN ) into its(Hz). fL = 1/(2π.R.C)
equivalent polar form, as follows-

= low cutoff frequency of the filter (Hz).

V0 AF
| |=
VIN (f⁄fL)
√1 + (f⁄fL)2
Designing and frequency scaling procedure of first order high pass filter is same as of first order low pass
filter.
SECONDORDER HIGH PASS BUTTERWORTH FILTER:
Figure 6.09 (a) and (b) shows the circuit diagram of second order high pass butterworth filter and frequency
response plot. Here two RC networks are used for filtering and op-amp is used in non-inverting mode .
Resistance RIN and RF determine the gain of the filter.
R Gai
RIN F +VCC
2 7 n 40dB/decade
V2  6
741 AF
V1 + 4 0.707AF
3 VO
C VEE
R1 R2
VIN 1
C2 Stop Band Pass
Band Frequen
fL
cy
Figure 6.09(a): Second order low pass Figure 6.09(b): Frequency
filter response
Figure 6.09(b) shows a frequency response of second order butterworth high pass filter with a low cutoff
frequency of fL. At fL the magnitude of gain is 0.707AF. All frequencies higher than fL are pass band frequencies with the highest
frequency determined by the close loop bandwidth of the op-amp. The gain increases at a rate of 40db/decade.
AF = [1 + (RF/RIN)] = pass band gain of the filter, f is the frequency of input signal (Hz). fL = 1/(2π.R.C)

= low cutoff frequency of the filter (Hz).

The gain magnitude equation is obtained by converting equation (VO/VIN ) into its equivalent polar form, as follows-

V0
| |=
A
VIN F √1 + (fL⁄f)4
Where, AF = 1.586 = pass band gain for the second order butterworth response.
Designing and frequency scaling procedure of high pass filter is same as of low pass filter because the circuits of
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HIGHER ORDER FILTERS:

Since the gain of filter in the stop band of first and second order filters, changes at a rate of 20 db/decade and
40 db/decade, means that, as the order of filter is increased, the actual stop band response of the filter
approaches its ideal stop band characteristic. Higher order filters, such as third, fourth and so on are formed
by using first and second order filters.
─60dB/decade
Gain
ist order ii nd order iind order iind order
low pass low pass VO low pass low pass AF
VO
VIN VIN ─80dB/decade
filter filter filter filter
0.707AF

Figure6.10: Third order Filter Figure6.11: Fourth order

Filter
Pass Band
Stop Band
fH
Figure 6.10 shows the block diagram of third order low pass filter, formed by cascading first order filter with
second order filter whereas figure 6.11 shows the block diagram of fourth order low pass Frequencyfilter, formed by
cascading two second order filters. Although there is no limit to theFigure
order 6.12:
of theFrequency
filter, as the order increases,
response
size of filter increases and its accuracy turns down. Also as the order of the filter increases, the difference
between the actual and the theoretical stop band response increases. The overall gain of the higher order filter
is equal to the product of the individual voltage gains of the filter sections. Since the value of resistors and
capacitors used in higher order filter are equal, the high cutoff frequency of higher order filter is given as: fH = 1 / (2π.R.C)

BAND PASS FILTERS:

A filter that passes only a band of frequencies lying in between lower cut off frequency (fL) and upper cutoff frequency (fH) and block

frequencies above fH and below fL is known as band pass filter. There are two types of band pass filter: wide band pass and
narrow band pass.
Wide band pass filter has a figure of merit or quality factor Q <10 whereas, Q>10 for a narrow band pass filter.
Quality factor Q is a measure of selectivity, means that higher the value of Q, the more selective is the filter or
narrower its bandwidth (BW). The relationship between Q, BW and center frequency fC is given as:

Q = (fC / BW)=[ fC/( fH ─ fL ).

For wide band pass filter, fC = √( fH . fL ) where, fH and fL are the high and low cutoff frequencies (Hz). Important is that upper

cutoff frequency fH should always be greater than lower cutoff frequency fL ie. fH > fL Wide Band Pass Filter:
Wide band pass filter is formed by cascading high pass and low pass filter as shown in figure 6.13(a), and
(b) shows The voltage gain magnitude of the
RF band filter is equal to the product
its frequency response. To obtain a ±20db/decade roll off, first order high pass filter is cascaded with first order
RFdepends of the voltage gain magnitudes of
low pass filter ie. the order of band pass filter ’ on the order of the high and low pass filter.
RIN’
the high pass and low pass.
RIN +VCC +VCC
2 2 Therefore,
V A (f⁄f ) 0 FT L
2 6 | |=
2
6
V1 741 R’ V1 741 VIN √[(1 + (f⁄fL)2 )
[1 +
]
+ 4
3 (f⁄fH)2]
3
+ 4 VO
Where, AFT = total pass band gain
C VEE C’ VEE
VIN R f = frequency of the input signal (Hz)
fL = low cutoff frequency (Hz) fH =
high cutoff frequency (Hz)
First order High Pass Filter First order Low Pass Filter Figure

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Gain
+20dB/decade ─20dB/ deca
de
AF
0.707AF

Stop Band Pass Stop

Band Band
fL Frequen
Figure 6.13(b): Frequency Response cy

fH
Narrow Band Pass Filter:
Figure 6.13(a) and (b) shows the circuit diagram and frequency response of narrow band pass
filter.
Gai
C
R3 2 n Band
R1 C 2 +VCC Width
1 V2  7 6 AF
741
V1 + 4
VIN 3 VO 0.
VEE
Stop Pass Band Stop Band
R2
R3 70 Band
R3 fL fC fH Frequency
7A
F
Figure 6.14(a): Narrow Band Pass Figure 6.14(b): Frequency
Filter Response
Narrow band pass filter using multiple feedback as shown hence the name multiple feedback filter. Op-amp
used is in inverting mode. This filter is designed for specific values of center frequency fC and quality factor Q or fC and bandwidth.
Design of narrow band pass filter:
(i)Choose C1 = C2 = C.
(ii)Determine the value of R1, R2 and R3 by the following expressions:
R1 = Q / (2π.fC.C.AF); R2 = Q / [2π.fC.C.(2Q2─AF]; and R3 = Q / (π.fC.C) where Q is the quality factor, fc is the center frequency (Hz), AF

is the gain at fc , is given by : AF = (R3)/(2R1)

(iii) Important is that, the gain must satisfy the condition: AF < 2Q2
Advantages of narrow band pass filter:
(1) Only single op-amp is used.
(2)Center frequency fC can be changed to new frequency fC’ without changing the gain or bandwidth. This can be
done by changing resistor R2 to R2’ so that R2’ = R2 (fc/fc’)2

BAND REJECT FILTERS :

In band reject filters, band of frequencies from fH to fL is attenuated ie. stop band whereas frequencies are passed outside this band
ie. pass band. Band reject filters are also called as band stop or band elimination filters. This filters are classified
as (i) Wide band reject filter (ii) Narrow band reject filter.
Wide band reject filter:
Figure 6.15(a) and (b) shows the circuit diagram and frequency response of wide band reject filter. This filter has
a high pass filter, a low pass filter and a summing amplifier. Condition to realize the band reject filter response
is that the low cutoff frequency fL, of high pass filter must be larger than the high cutoff frequency fH, of low pass filter. Also the pass
band gain of high and low pass filters must be same. Center frequency fc = √( fH. fL)

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R Gai
F
R1 2 +VCC n
V2  7 6
C 741 R4
V1 A
+ 4 R2 F
3 +VCC
A 2 Stop
R  7 6 Pass Band Pass
VEE 741
0.70

B + 4 7AF Band Band

RF R3
3 VO
fH fC fL Frequen
VIN R1’ 2 ’ +VCC VEE
cy
V2  7 6
741
R V1
’ 3
+ 4
C’ VEE

Figure 6.15(a): Wide Band Reject Filter Figure 6.15(b):

Frequency Response

From figure 6.15(b), the voltage gain changes at the rate of 20dB/decade above fH and below fL, with a maximum attenuation
occurring at fc.
Narrow Band Reject Filter (Notch Filter):
For rejection of only a single frequency, the notch filter is used. Active notch filter commonly uses a twin-T
network and a op-amp as voltage follower. One T network has two resistors and a capacitor while the other uses
two capacitors and a resistor. The quality factor Q of T network is low and can be increased, if it is used with
voltage follower as shown in figure 6.16(a) and figure 6.16(b) shows the frequency response of filter.
R R
+ Gai
C C 741 n Bandwidth
VIN ─ VO
A
R/
2 0.707AF
Sto
2C Pass p

Pass

fH fN fL

Frequency

Figure 6.16(a): Narrow Band Pass Filter Figure 6.16(b): Frequency Response

To design a notch filter for a desired notch out frequency fN, choose the value of capacitor CS1μF and then calculate the value of resistor

using the expression: R = 1/ (2π.fN.C). Notch filters are used in communications and biomedical instruments to eliminate
undesired frequency.

ALL PASS FILTER:

A filter which passes all frequency components of input signal without attenuation is known as all pass filter. All
pass filters is also called as delay equalizers or phase correctors. Figure 6.17(a) and (b) shows the circuit diagram
and input and output waveforms. In this filter, the pass band covers the entire frequency, hence has a flat
amplitude response characteristics. All pass filter produces an output that is phase shifted relative to the input
signal.

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RF =RIN
Voltag
RIN e Vin
+VCC VO
 7 6 1
2 2
741
R VV1
+ 4 VO
C
3 t
VIN
VEE
─1
ᶲ
Figure 6.17(a): All Pass Figure 6.17(b): Input and Output
Filter Waveforms
The output voltage Vo is given by the expression- Vo = [(1─j2π.f.R.C)/ (1+j2π.f.R.C)].VIN

Where, f is the input signal frequency (Hz). From the above equation, amplitude of (Vo/VIN) is unity ie. Vo = VIN throughout the
useful frequency range and the phase shift between input and output is a function of input frequency f. From
figure 6.17(b), the output signal lags the input signal by 90° ie. there is a phase shift of 90° between input and
output. The circuit causes a change in phase angle ф from 0° to (─180°) for a frequency
variation from 0 Hz to ∞.
The phase lag introduced by the circuit is given by the expression: ф = [─2.tan─1 (2π.f.R.C)] where ф is in degrees,
f is in hertz, R in ohms and C in farads. If the position of R and C are interchanged, then the output signal leads
the input signal and the phase angle introduced by the circuit is given by: ф = [2.tan─1 {1/(2π.f.R.C)}]

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IC-555
TIMER:
Figure 7.01 shows the functional block
Control diagram of IC-555 timer. It consists of a
VCC Discharge Threshol
7 d
voltage divider network, which provides
8 Voltag
6 bias voltage of (2/3)Vcc to the inverting
e input of the comparator-1 and (1/3)Vcc to
5
the non-inverting input of the
5kΩ + Q1 comparator-
Comparator-1 2. These two voltages fix the
─ comparator
(2/3)VCC
R threshold voltage and also determine the
Q’
F/F timing interval. Electronically, possible to
(1/3)VCC + S vary time by applying a modulation
5kΩ Comparator-2 Q2 voltage to the control voltage input (pin-
5kΩ ─ 5). If no such modulation is proposed, a
Vref 0.01μF capacitor is connected between
control voltage and ground to bypass
Output Stage noise and ripple from supply. The other
2 3 4 two inputs to the comparator are
1
Groun Trigger Outpu Rese threshold and trigger inputs. The output
d t t of these two comparators, SET or RESET
Figure 7.01: Functional block diagram of IC-555 the flip flop, whose Q’output is fed to
Timer between pin 7 and
base of transistor Q1ground)
. When Q’will discharge.
= high, Q1 is ON
The output stage is basically an inverting buffer stage used to provideand
a low output resistance
capacitor and
(externally invert
also to
connected
the flip flop output. Output stage has a capability of sourcing and sinking 200mA current. Q2 (PNP transistor) whose emitter is connected

to an internal reference voltage which is less than Vcc. When Vref > Vcc (Pin-4 potential is less than Vcc), Q2 is ON, which causes Q1 to

turn ON and output at pin-3 is brought to ground level.

Applications include oscillator, pulse generator, ramp and square wave generator, voltage monitor and may
more
applications.

IC-555 AS MONOSTABLE MULTIVIBRATOR:

Figure 7.02 (a) shows the circuit diagram of IC-555 as monostable multivibrator and (b) shows the waveform of
trigger pulse, capacitor voltage and output pulse. Since it has only one stable state (output low), hence name
monostable. Trigger
R VCC
8 4
VCC 0
7 t
VCC Capacit
555 3
VC 6 or
VO
2/3V
0 CC
C t

2 Outpu
1 5 tP
t
C1 0 t
Figure 7.02(a):
Figure 7.02(a): Monostable
Waveforms
Multivibrator
It is also called as one-shot multivibrator. From the circuit diagram, Pin-8 is connected to Vcc and pin-4 (reset
pin) also connected to Vcc so that reset condition is disabled. The time interval for which the output remains high (tP, pulse width)
is decided by the external RC network. The capacitor C is connected between pin 7 and 1 so that it charges through
the resistance Rwhen the transistor Q1 is OFF.
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Operation: Initially, trigger pulse is high (Vcc), this drives the output of comparator-2 to low condition. As the
capacitor C is in discharged state, pin-6 and 7 are at ground potential. The inputs to the flip flop will be S=R=0,
hence Q’ = high, so, Q1 is ON, and C discharges to 0V ie. Vc = 0V. Since Q’ = 1, output pin-3 = 0 is actually the stable state of
multivibrator.
When the trigger input (negative trigger pulse) goes low (from Vcc to 0), comparator-2 output = high ie. S = 1.
The comparator-1 output continue to be 0 ie. R=0, hence the flip flop is in set condition ie. Q’ = 0, pin-3 = 1(High
state).
Since Q’ = 0, transistor Q1 is OFF and the capacitor Cstarts charging exponentially towards Vcc through the resistor
R. When Vc becomes greater than ((2/3) Vcc), comparator-1 output changes form low to high ie. R = 1. Since
the
trigger input has returned back to Vcc from 0, comparator-2 output is equal to zero ie. S =0. So, S = 0 and R=
1, RS
flip flop get RESETand Q’ = 1. AS Q’ = 1, transistor Q1 = ON and capacitor Cstarts discharging towards zero through the transistor Q1 and

capacitor voltage Vc becomes zero. While discharging, when Vc < ((2/3) Vcc), the comparator-1 output goes to zero ie. R=0.
Since the trigger input = Vcc, the comparator-2 output will be = 0 ie. S=0. Hence, S=0 and R=0, so no change in
the Q’ output condition and hence continuous to be High. Thus, pin-3 output = LOW (0-state).
The monostable multivibrator, thus goes from stable state into quasistable state and then returns back to the
stable state after a time, tP = (1.1)R.C
The output remains to be in LOW state until the next trigger pulse is applied to change the state.

IC-555 AS ASTABLE MULTIVIBRATOR:

Figure 7.03 (a) shows the circuit diagram of IC-555 as astable multivibrator and (b) shows the waveform of
Output
R and output
capacitor voltage 4 Since no stable state, hence Vname
8 pulse. C
astable.
A C Voltag
7 TON TOFF
VCC 0 e
R
B 555 3 T
6
VO
t
Capacit
C 21 5
VCC or
2/ 3VC Voltage
C1 C t
Figure 7.03(a):
Figure 7.03(a): Astable 1/3V
Waveforms
CC
Multivibrator
Astable multivibrator does not requires an external trigger pluse 0 to change the output state, hence called as
free- running multivibrator. The time duration for which the output will remain high or low is decided by the
externally connected two resistors (RA and RB) and a capacitor (C).
Operation: Initially, when output is high (pin-3 = High), Flip flop output Q’ = 0, hence transistor Q1 is OFF. Now the capacitor C starts

charging towards Vcc through RA and RB. As soon as the voltage across the capacitor Vc, becomes equal to[ (2/3)Vcc], the

comparator-1 output is high and will RESET the flip flop ie. Q’ = 1. Hence the output = 0. As, Q’ =1 , transistor Q1 = ON
and the capacitor Cstarts discharging through resistor RB and transistor Q1. During discharging mode of capacitor C, as soon as the voltage

across the capacitor C becomes equal to [(1/3)Vcc], comparator-2 output will SET the flip flop, Q’ = 0, and output =
high. Then the cycle repeats.
Charging time duration of the capacitor C, is equal to the time the output is high is given by the expression:
tC = TON = 0.69(RA + RB )C
Discharging time duration of the capacitor C, is equal to the time the output is low is given by the expression:
1.
tHence,
d = TOFF
the= frequency
0.69(RB )Cof oscillation is, fO = 1/T = 45
(RA+2RB)
From thetotal
Hence the equation of frequency
time period of oscillation
of output waveform: T = tC + td = TON + TOFFis= independent
fo,
C frequency
0.69(RA + 2RB )Cof the supply voltage Vcc.
Duty Cycle: Duty cycle is the ratio of the time during which the output is high (TON) to the total time period T.
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RA+RB
% duty cycle = [TON / T] x 100 =
× 100 RA+2R
Applications: Astable multivibrator
B can be used to produce a square wave output. It can be used as a free
running ramp generator.

OP-AMP AS SCHMITT TRIGGER:

Figure 7.05(a) shows the circuit diagram and 7.05(b) input and output waveforms of op-amp as Schmitt trigger.
This circuit converts an irregular-shaped waveform to a square wave output.

+VUT
─ +VCC INPUT (VIN)
741 0
t
+ VO −VLT
ROM=R1||R2 ─VEE
VIN <VUT
+ +VSA
R OUTPUT (Vo)
T
VIN R
─ 2 t
1 0

Figure 7.05(a): Op-Amp as Schmitt ─ V >V

IN LT
Trigger Figure 7.05(b): V
SA
Waveforms T

Circuit diagram shows an inverting comparator with positive feedback as a Schmitt trigger. Upper threshold
voltage (VUT) and lower threshold voltage (VLT) are obtained by using voltage divider network R1 and R2.The voltage drop across R1 is fed

back to the non-inverting input. This voltage drop across R1 is the VUT and VLT threshold voltages that depend on the value and

polarity of output voltage Vo. The output voltage Vo, switches between positive saturation voltage (+VSAT) and negative
saturation voltage (−VSAT), each time the input voltage exceeds the threshold voltage levels, VUT and VLT, as shown in figure 7.05(b). ROM

is the offset minimizing resistance, used to minimize offset problems.

RSAT
As long as VIN < VUT, the output voltage Vo =+V 1 . When VIN > VLT, the output voltage Vo = −VSAT. Using the voltage divider rule, the
VUT = [+VSAT ]dV = R1+ SA ]
values of VUT and VLT can be obtained as: + R
R 1
2R 1 LT T
R2 [−V
To remove the false output transitions, the threshold voltages (VUT and VLT) are made slightly larger than the input noise voltages.

Also, the positive feedback, because of its regenerative action, switching of output voltage Vo, between positive
saturation voltage (+VSAT) and negative saturation voltage (−VSAT) will be fast.
This inverting comparator with positive feedback exhibits hysterisis, a dead band condition ie. the output
switches
from +VSAT to −VSAT , when the VIN > VUT and output comes back to its original state ie. +VSAT when the VIN < VLT.

COMPARATOR CHARACTERISTICS:
(1)Speed of operation: As the comparator switches rapidly between +VSAT to −VSAT, implies that the bandwidth is
wider and
hence the higher is the speed of operation.
(2)Accuracy: Comparator accuracy depends on its voltage gain, CMRR, input offsets, and thermal drifts.
(3)Compatibility of output: Comparator is aform of ADC converter, whose output swings between two logic
levels suitable for logic family (TTL logic family)
LIMITATIONS OF OP-AMP AS COMPARATORS:
Generally, output of a comparator is not well matched with a particular logic family (TTL logic family). This is the
limitation of comparator. Hence to matched the output, op-amps are used with external components such as
zeners or diodes. Hence, the resulting circuits, in which the outputs are limited to predetermined values, are
called limiters.

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OP-AMP AS VOLTAGE LIMITERS:

Figure 7.06 (a) to (f) shows the circuit diagram and input/output waveforms of voltage
limiters.
D1 D
+ VP
−2
+ INPUT (VIN)
R 2 +VCC 0
−
V2  7 6 t
741
VIN + + 4 −VP
V1 3 VO
OUTPUT(V
VEE
(VZ + VD2) o)
ROM =R
0
t
−(VZ + VD1)
Figure 7.06(a): Op-amp as Comparator Figure 7.06(b): Input and output
with positive and negative voltage Waveforms
limiting
Figure 7.06 (a) shows the circuit diagram of comparator with positive and negative voltage limiting circuit and (b)
shows the input and output waveforms. From figure, Point V1 and V2 are at virtual ground, so input voltage VIN, appears across input

resistor R, and output voltage Vo, across zener diodes D1 and D2, which are connected in the feedback path. Resistance ROM, is used to

minimize the offset problems.

This arrangement limits the output voltage. When the input voltage VIN, crosses zero and increases in positive direction, as shown in figure

7.06(b), diode D1 is forward biased and diode D2 goes into avalanche conduction, the output voltage (Vo) increases in negative

direction. Therefore, the maximum negative value of output voltage Vo, is equal to –(VZ + VD1) where VZ is the zener
voltage and VD1 is the voltage drop across the forward biased zener diode D1 ( = 0.7V). On the other hand, when input crosses zero and

increases in the negative direction, output voltage Vo, starts increasing positively until diode D2 is forward biased and

D1 goes into avalanche conduction. Thus the maximum positive voltage is equal to +(VZ + VD2), where VD2 is the voltage drop
across the forward biased zener D
diode
1 D2 ( = 0.7V).
D Thus the output voltage Vo swing is limited to +(VZ + VD2) and –(VZ + VD1).
V
−2 + P
If there is a need of output+ voltage to limit the swing in positive direction only, thenINPUT
the(Vcircuit
IN)
diagram in
figure R +VCC 0
−2
7.06(c) is used. Figure 7.06(d)
V2 
shows
7 the input and output waveforms of figure 7.06(c). t
6
741
VIN + + 4 −VP
V1 3 VO
VEE OUTPUT(V
(VZ +
o)
ROM =R VD2)
0 t

VSAT)
Figure 7.06(c): Op-amp as Comparator Figure−(7.06(d): Input and output
with positive voltage limiting Waveforms

If only one zener diode is used in feedback path, as shown in figure 7.06(e), the output voltage is limited to +VZ and −VD, as shown in

figure 7.06(f). If the direction of diode D in the feedback path is changed in figure 7.06(e), then exact opposite result can be obtained ie.

output voltage Vo, is limited to −VZ and +VD, where VZ is the zener voltage and VD is the voltage drop across the forward biased zener

diode.

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D
+ − VP
INPUT (VIN)
R 0
2 t
 6
741
VIN + + 4 −VP
V1 3 VO
+VCC
VEE OUTPUT(V
7 VZ
V2 o)
ROM =R
0
− t
(
V
Figure 7.06(e): Op-amp as Comparator Figure 7.06(f): Input and output
D
with positive and negative voltage Waveforms )

limiting
Voltage limiters are commonly used in communication devices such as Television and frequency modulation
receivers.

OP-AMP AS CLIPPERS AND CLAMPERS:

CLIPPERS:
The circuits which are used to clip off the unwanted portions of the input voltage above or below certain levels
to produce output are called as clipping circuits.
POSITIVE CLIPPER CIRCUIT:
Figure 7.07(a) shows the circuit diagram of positive clipper using op-amp with a rectifier diode and figure 7.07(b)
shows the input and output waveforms.

VP
VEE
2– 4 INPUT (VIN)
V2 6
D +V
741 REF
t
+ 7 VO' VO 0
V1 3
R −VP
+
VIN RP OUTPUT(V
+VCC
+V REF o)
+VREF 0 t
−( VP)

Figure 7.07(a): Positive Clipper

Circuit Figure 7.07(b): Input and output
Waveforms
Here the op-amp is basically used as a voltage follower with a diode D in the feedback path. Clipping level is
determined by reference voltage +VREF. The +VREF should always be less than the input voltage range of op-amp. Resistance RP is used as a

potentiometer (variable resistor) to vary the reference voltage. Diode D is assumed as an ideal diode.

Operation: During positive half cycle of input voltage, when VIN S VREF, the VREF voltage at inverting input terminal is higher than the

input voltage VIN applied at the non-inverting terminal of op-amp. Hence, op-amp output VO’(pin 6), is sufficiently negative to turn ON

diode D, so, the output Vo, follows the input VIN, because the op-amp is used as a voltage follower. when VIN > VREF, the VREF voltage at

inverting input terminal is lower than the input voltage VIN applied at the non-inverting terminal of op-amp. Hence, op-amp output

VO’(pin 6), is sufficiently positive to turn OFF diode D, the op-amp operates open-loop; therefore it further drives its output voltage

VO’(pin 6) towards positive saturation (+VCC). Thus, when VIN > VREF, VO’ =+Vcc and Vo = +VREF.

During negative half cycle, VIN S VREF, the output of op-amp VO’(pin 6), is sufficiently negative to turn ON diode D, so, the output Vo,

follows the input VIN. Thus from the output waveform, it is seen that the output portion of the positive half cycle above
reference voltage is clipped off, hence it is called as positive clipper circuit.
The op-amp
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NEGATIVE CLIPPER CIRCUIT:

If POTRP of figure 7.07(a) is connected to negative power supply –VEE, then the reference voltage VREF becomes negative. This will cause

the entire output waveform, above −VREF, to be clipped off. The output follows the input only when Vin < −VREF. By changing the

position of diode D and the polarity of reference voltage VREF, the positive clipper can be converted into negative clipper.

SMALL SIGNAL HALF-WAVE RECTIFIERS (POSITIVE):

Figure 7.08(a) shows the circuit diagram of a positive small signal half wave rectifier with zero reference voltage
and figure 7.08(a) shows the input and output waveforms.

+VREF = 0V VP
2 4 VEE
 INPUT (VIN)
V2  6
D 0
310 t
3
+ 7 VO
V1 VO' −VP
+ R
VIN L OUTPUT(V
+VCC VP
0 o)
t
Figure 7.08(a): Positive Small Signal
Half Wave Rectifier
Figure 7.08(b): Input and output
Waveforms
This circuit can rectify the signal of peak values of few millivolts. This is possible because the high open loop gain
of op-amp automatically adjusts the voltage drive to the diode D so that rectified output peak is the same as the
input. Diode D acts as an ideal diode.
Operation: When input voltage VIN increases in positive direction, output of op-amp VO’, also increases in positive direction and diode
D is forward biased and act as closed switch, and closes a feedback loop. Hence the op-amp act as a voltage
follower, and output voltage Vo, is same as input voltage, as shown in figure 7.08(b).
When input voltage VIN increases in negative direction, output of op-amp VO’, also increases in negative direction and diode D is
reverse biased and act as an open switch, and opens a feedback loop. Hence output voltage Vo, is zero volt, and
output does not follow the input as shown in figure 7.08(b).
Here the op-amp should be high speed op-amp, since it alternates between closed and open loop operations.
Examples of high speed op-amps are HA2500, LM310 and µA318.

SMALL SIGNAL HALF-WAVE RECTIFIERS (NEGATIVE):

This small signal positive half wave rectifier can be converted into negative small-signal half wave rectifier by
reversing diode D.

NEGATIVE HALF-WAVE RECTIFIER:

Figure 7.09(a) shows the circuit diagram of a negative half wave rectifier with zero reference voltage and figure
7.09(a) shows the input and output waveforms.

VEE
+
R1 2 RF = R1D1
VO VP INPUT (VIN)
VIN +  4 6  0
310 VO’ t
+ 7 +
3 −VP
D2
+VCC 
ROM OUTPUT(V
D1 D2
+VREF = 0V o)
0 ON ON
t
Figure 7.09(a): Negative Half Wave −VP
Rectifier Figure 7.09(b): Input and output
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In this circuit, op-amp is used in inverting configuration. The two diodes D1 and D2 are used in such a way that
the output Vo’ does not saturate which in turn minimizes the response time increases the operating frequency
of op- amp. The output voltage Vo is measured at the anode of D1.
Operation: During positive half cycle of input voltage VIN, output Vo’ is negative, hence diode D1 is forward biased and closes the feedback

loop through RF. Since R1 = RF, Vo = VIN. During negative half cycle of input voltage VIN, output Vo’ is positive, hence diode D2 is
forward biased and prevents the op-amp from going into positive saturation. Since diode D1 is OFF, Vo = 0V.
In order to obtained positive half-wave rectified outputs, diodes D1 and D2 must be reverse biased.

POSITIVE AND NEGATIVE CLAMPERS:

The circuit in which the output signal is clamped to a predetermined DC level (Positive or Negative), without
changing the shape and amplitude of the input signal is called clamper. Clamper is also called as DC inserter or
restorer. Condition to keep the output waveform undistorted is that the (RC) time constant should be very large
compared to the time period of the input waveform.
Figure 7.10(a) shows the circuit diagram of peak clamper and figure 7.10(b) shows the input and output
waveforms with +VREF.

Ci I VP
− + C
R − VO INPUT (VIN)
− VP −VEE D
2 0
VI 
4 + t
+ 6
N
741
VO’ −VP
3 + 7

+VCC
R 2VP
P
OUTPUT (Vo)
VRE
F +VRE
F 0 t
Figure 7.10(b): Input and output
Figure 7.10(a): Op-amp as peak
clamper Waveforms with +VREF

Figure 7.10(c) shows the input and output waveforms with −VREF.
Figure 7.10(a) consists of a variable positive DC level.
Output Vo, is the net result of AC and DC, applied to VP
inverting terminal and non-inverting terminal of op- INPUT (VIN)
amp. 0
t
Circuit Operation: Diode D is assumed as an ideal
diode. To understand the operation, we will consider −VP
each
0 t
input separately. Considering VREF input first, connected to non- −VRE
F OUTPUT
inverting terminal of op-amp. Since reference voltage (Vo)
−2VP
VREF is positive, output at pin 6 (Vo’) is also positive, which
forward bias the diode D. Thus diode act as a closed
switch, and closes the feedback loop and op- amp Figure 7.10(C): Input and output
operates as a voltage follower. This is possible because Waveforms
capacitor Ci is an open circuit for DC voltage. Therefore, Vo = with −VREF
During negative half cycle of input voltage VIN, diode D conducts and capacitor starts charging to the negative peak value of VP. During
+VREF.
Now considering
positive AC input
half cycle, diode voltage
D is reverse VIN,
biased, which
hence is capacitor will remain same. Since the positive half cycle VP, is in series with
VP across
connected to inverting terminal of op-amp.
the capacitor voltage VP, hence the output voltage VO = 2VP. Thus the net output is VREF plus 2VP, so the negative peak of 2VP is at VREF

as shown
Page no:in figure
48 7.10(b). For precision clamping, Ci.Rd << T/2 where
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input waveform. Resistor R is used to protect the op-amp from excessive discharge current from capacitor Ci, when DC supply
voltages are switched OFF. A positive peak clamped to negative reference level clamper circuit is made by
reversing the diode D and using negative reference voltage. Its input and output waveform is shown in figure
7.10(c).
Clipping and clamping are used in wave shaping circuits. These circuits are used in digital computers and
communications such as TV and FM receivers.

ABSOLUTE VALUE OUTPUT CIRCUIT:

Figure 7.11 (a) shows the circuit diagram of absolute value output circuit, figure 7.11 (b) shows the circuit
diagram of absolute value output circuit during positive half cycle, figure 7.11 (c) shows the circuit diagram of
absolute value output circuit during negative half cycle, and figure 7.11 (d) shows the input and output
waveforms. I2D3
D3 − R+ − +
R − R
R +
+VCC 2 +VCC
R 2 7 I2
D1 6 V2 7 6
V2 741 741
+ R 
R V1 + 4 − V1 + 4 VO(+)
+ D 3 VO 3
+ + D2− I1 +
2 VEE VEE
R
− VI −+VP −R
N

Figure 7.11(a): Absolute value output Figure 7.11(b): Absolute value output
circuit circuit during positive half cycle

I1
D3 − R+ D3
+ R− − R+ − + − ++VCC
IB2
2
− R+ +VCC RTH=R/2 V 7
− 7 2 6
D1 2
– 741
− V1
2 6 + 4 VO (−)
741 VO (−) 3
− + V + 4 VEE
E I2 + IB1
−VP V1 VE − R
3
R +
+
VTH=−(VP−VD1)/2

Figure 7.11(c): Absolute value output circuit Figure 7.11(c): Thevenin’s Equivalent
during negative half cycle Circuit Operation: During positive half cycle of input
+VP voltage (VP), diode D2 is forward biased and D1 is reverse biased.
INPUT (VIN)
0 Hence the Diode D2 is connected in the circuit as shown
t
in figure 7.11 (b). Thus the voltage at node V1 (+ input of op-
−VP
amp) is: V1
2
+VP = VP − VD2
OUTPUT (VO) Where, VD2 is the voltage drop across diode D2 = 0.7V Similarly,

t the voltage at node V2 (− input of op-amp) is:

0 V2 V0(+) − VD3
2
=
Figure 7.11(d): Input and output Where, VO(+) is the output voltage during positive half cycle and VD3
Waveforms is the voltage drop across diode D3 = 0.7V Since, difference input
Therefore voltage, Vid ≈ 0V, so V1 = V2.
, VP −
= V0(+) −
VD22 2
VD3
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Hence, we get the output voltage, VO(+) = VP (ie. the output voltage is equal to the peak of positive half cycle of the input as shown
in figure 7.11(d)).
During negative half cycle of input voltage (−VP), diode D1 is forward biased and D2 is reverse biased. Hence the Diode D1 is
connected in the circuit as shown in figure 7.11 (c). This circuit is further simplified by applying thevenin’s
theorem to the left of the (−) input of op-amp. Hence, its Thevenin’s equivalent voltage and resistance are:
VP − R
VTH = − ) and RTH≅
VD12 2
(
Where, VD1 is the voltage drop across diode D1 , VTH and RTH are Thevenin’s equivalent voltage and resistance. Now, applying

Kirchoff’s current law at node V2, we get:

I1 = I2 + IB2; Since, IB2 ≈ 0A; Hence, I1 = I2

Where, I1 and I2 are the currents flowing through resistor Rand RTH and IB2 is the bias current that flows into the inverting
terminal of op-amp as shown in the figure 7.11(c).
Since, I1 [V0(−) − VD3] − Va 2nd I2 V 2 −
= (V ) R = T
H
R2
⁄
Hence, on equating currents, I1 and I2, we get,
[V0(−) − VD3] −=
V2 V2 −
(VTH) R R⁄2
Since, Voltage at Node V1 = 0V, so, V2 is also zero, due to virtual ground concept. Therefore, substituting the node voltage V2 = 0V and

also VTH in the above equation, we get:

VO (−) – VD3 = VP – VD1

Hence, the output voltage, VO (−) = VP, where, VD1 = VD3 = 0.7V (ie. the output voltage is equal to the peak of negative
half cycle of the input as shown in figure 7.11(d)).
Hence, from the output equations of VO (−) and VO (+), it is concluded that the regardless of the polarity of the input signal, the
output is always positive going; hence the name given absolute value output circuit.
Note that the gain of the circuit is 1, therefore the positive peak amplitudes are the same as the input peak
amplitudes. Diode D3 compensates for the voltage drop across diodes D1 or D2.
This circuit is used in wave shaping circuits.

PEAK DETECTOR:
Peak detector is a circuit which is used to measure the peak value of any non sinusoidal waveforms. Figure
7.12(a) shows the circuit diagram of peak detector (positive) and 7.12(b) shows the input and output
waveforms. VEE +VP Input Voltage VIN
R2
 4 6 D1
IB
0
t
741
ROM=R +− −V
3
+ 7 + VO P T
+ C
+ D − R Output
VIN − 2 IC L +VP
+VCC Voltag
e

0 t
Figure 7.12(a): Peak Detector
Circuit Figure 7.12(b): Input and Output
Waveforms
Operation: During the application positive half cycle of input voltage VIN, diode D1 is forward biased and D2 is reverse biased. Due to

diode D1 forward biased, the op-amp operates as a voltage follower. As diode D1 is forward biased, capacitor Cstarts
charging towards positive peak +VP of input voltage as the polarity shown in figure 7.12(a).
During the application of negative half cycle, diode D1 is reverse biased, and voltage across capacitor C remains
unchanged. The only discharge path for Cis through load resistor RL. For proper operation of the circuit the charging time constant (C.Rd)
Page no: 50time constant (C.RL) must satisfy the following
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(i)(C. Rd) S(T/10); where Rd is the resistance of forward biased diode (100Ω typically) and T is the time period of
input waveform.
(ii) (C.RL) S(10T); where RL is the load resistor.
A high speed, precision type op-amp such as µA741 is used. The resistor R is used to protect the op-amp against
the excessive discharge currents, especially when the power supply is switched off. The resistor ROM = Rminimizes the offsets problems.

Diode D2 conducts during negative half cycle of VIN voltage to prevent the op-amp from going into negative saturation, which
in turn reduces the reverse recovery time of op-amp.
Negative peak detector can be detected by reversing diodes D1 and D2 of figure 7.12(a)

SAMPLE AND HOLD CIRCUIT:

Figure 7.13(a) shows the circuit diagram of sample and hold circuit and figure 7.13 (b) shows the input and
output waveforms.
VP
N-Channel 2 VEE
4
E-MOSFET  6
D S VC R INPUT (VIN)
741 VO
+ RL
3 +
VIN 0 t
7
C VS
+VCC
+VP Control Voltage (VS) TS=
G
Sample Time TH= Hold
Time
VS 0 t

TS TH
VIN : Input signal to VO = VP
be sampled Output
Voltage (VO)
VS : Sample and Hold Control Voltage VC :

Voltage across capacitor

G : Gate; D : Drain and S : Source 0 t
Sample and hold circuit is the circuit which samples the applied input signal and holds on to its last sampled
value until the input is sampled again. From the circuit, enhancement MOSFET
Figure 7.13(b): Input (E-MOSFET) works as a switch ie.
and output Waveforms
when gate (G) terminal is positive E-MOSFET conducts (ON) and when zero, E-MOSFET is OFF. This ON and OFF
of E- MOSFigure 7.13(a): by
FET is controlled Sample
sampleand
and Hold
hold control voltage (VS). The analog input signal (VIN) to be sampled is connected to
Circuit
drain (D) terminal and source (S) terminal is connected to capacitor C, where capacitor C, acts as a storage
element. Here op-amp acts as a voltage follower.
Operation: When control voltage VS, is positive, E-MOSFET is ON, and capacitor starts charging towards input voltage VIN. This input

voltage VIN, appears across capacitor C and in turn at the output of op-amp VO, as shown in figure 7.13(b). This is the sample
period time.
When control voltage VS, is zero, E-MOSFET is OFF, and act as a open switch. The only discharge path for capacitor C is through op-

amp. However the input resistance of op-amp as voltage follower is very high; hence the voltage across capacitor
VC, is retained. This is the hold period time. The output of op-amp is observed during hold periods.

Note that, for obtaining the close approximation of the input waveform, the frequency of control voltage VS must be higher than that

of the input signal VIN. Also precise and high speed op-amp is used. Choose a low-leakage capacitor such as Teflon or
polyethylene.
Sample Periods: The time periods TS of the control voltage VS, during which the voltage across the capacitor is equal to the input voltage
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The sample and hold circuit is commonly used in digital interfacing and communications such as
analog-to-digital and pulse modulation systems.

VOLTAGE TO CURRENTCONVERTER WITH GROUNDED LOAD:

Figure 7.14 shows the circuit diagram of an op-amp voltage to current converter operating with a grounded
load. The input voltage source is connected to the non-inverting
terminal of the op-amp; hence it does not get loaded due
R R to the very high input resistance of the circuit. The circuit
+VCC
is capable of converting an input voltage into its
2
 7 6 equivalent load current that flows through a load in which
V2 741
+ one end is grounded as shown in figure. It can be shown
R− V1 I1 + 4
3 VO =2.V1
+ mathematically that the load current IL is directly proportional to the
VIN − VEE
R
+ − input voltage VIN. The circuit analysis is carried out by determining the
LOAD I2 +
voltage V1 that appears at the non-inverting input (pin-3). We
− IL
then establish a relationship V1 and load current IL.

Figure 7.14: Voltage to current converter Applying Kirchhoff’s current equation at node V1,
Since, 1 = VINR −V1 and 2
= R
with grounded load I I1 + I2 = ILI
………………………………………..(6.1)
V0−V1

Substituting, I1 and I2 in equation no. 6.1, we get,

VIN−V1
R + 0R
V −V1
= L; On solving, we get, V = VIN+V0−R.IL ……………………………………(6. 2)
2 1
Since
I the gain of the circuit connected in non-inverting amplifier is given as (1+R/R) = 2. Hence the output
voltage
VO = 2.V1 ............................................................................(6.3)
On substituting equation 6.2 in equation 6.3, we get,
VO = VIN + VO – R.IL ; OR VIN = R.IL ; OR IL = VIN / R .....................................(6.4)

ie. IL α VIN ; this relationship shows that the load current IL is directly proportional to the input voltage VIN.
The load current IL depends on the input voltage VIN and the resistance R. In this circuit it is very important that all resistors must
have equal values for satisfactory operation.
Voltage to current converter circuits is used to test Zener diodes and LEDs. They are also used for low
voltage Voltmeters. The load size S R value will give satisfactorily performance of the circuit.

VOLTAGE TO CURRENTCONVERTER WITH FLOATING LOAD:

Figure 7.15 shows the circuit diagram of an op-amp voltage to voltage
The input current converter operating with
source is connected a floating
to the load
non-inverting
ie. the load terminals are
IO not
R L connected to ground. terminal of the op-amp; hence it does not get loaded due

+VCC to the very high input resistance of the circuit. The voltage
− RIN + 2 7
6 drop
VA 741
IO
+ 4 across resistance RIN is equal to (IO.RIN) where IO is the output current.
3
+ VEE
(VA) is the input at the inverting input terminal. The circuit is capable
VIN of converting an input voltage into its equivalent load
−
current that flows through the floating load as shown in
figure 7.15. This circuit is also called as current series
Figure 7.15: Voltage to current converter
with floating load negative feedback amplifier because the feedback voltage
across resistor RIN depends upon output current IO and is in series with
Applying Kirchhoff’s voltage law to the input circuit, we get, VIN = VA
input difference voltage Vid.
But VA = (IO . RIN) ; but VA = VIN ; therefore VIN = (IO . RIN); or IO = [VIN / RIN] ie. IO α VIN. The relationship of the output current

IO and the input voltage VIN clearly shows that the output current IO is directly proportional to the input voltage VIN. For satisfactory

Page no:of52
operation the circuit, the resistor RIN must be a precision
Followresistor.
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current converters with floating loads is used for testing Zener diodes, LEDs, for matching diodes and also in
low range (AC and DC) voltmeters.

CURRENT TO VOLTAGE CONVERTER:

Figure 7.16 shows the circuit diagram of current to voltage converter in which the input current is
directly proportional to output voltage. Basically the circuit is an op-amp inverting amplifier.
Input voltage source VIN in series with input resistor RIN is connected to inverting
IO RF
RIN terminal of op-amp. This series combination will form a constant
+VCC
 7 6 current source of magnitude IIN. − F
2 V2
IIN
741 (VO/ voltage
The VIN ) = −(RF / ofR
gain ) ; ie. V
INinverting = .IN
0 amplifier
R Vgiven
is 0 V0= −VIN . R
by:
VIN + + 4 RIN
V1 3 VO F
−  E Since, IIN = (VIN / RIN). RIN
V E

Hence, VO = −[(IIN).RF] ie. VO α (IIN).

From the above relationship it is clear that the output voltage VO is directly
Figure 7.16: Current to
proportional to the input current IIN which means that the circuit is capable of
voltage converter
converting an input current into a proportional output voltage. The
lower limit on current measurement is set by the
bias current IB of an op-amp, this means that op-amps with smaller IB values such as

μA714 which has an IB = 3 nAcan be used to detect lower currents.

Current to voltage converters are used to sense currents from photo
PRECISION FULL WAVE RECTIFIER : [ABSOLUTE detectors
VALUEand are alsoCIRCUIT]
OUTPUT used in digital to analog converters.
Refer to figure 7.11 for circuit diagram and operation.

PRECISION HALF WAVE RECTIFIER : [SMALL SIGNAL HALF-WAVE

RECTIFIERS]
Refer to figure 7.08 for circuit diagram and operation.

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VOLTAGE REGULATORS: A voltage regulator is a circuit that provides a constant voltage regardless of any
changes in the load currents. Performance parameters of voltage regulators are:
Line regulation or input regulation: The change in output voltage for a change in input voltage. Expressed in
millivolts.
Load regulation: The change in output voltage for a change in load current. Expressed in millivolts.
Temperature stability or average temperature coefficient of output voltage: The change in output voltage per
unit change in temperature. Expressed in either millivolts/°C or parts per million (ppm)/°C.
Ripple rejection: It is the measure of the regulator’s ability to reject ripple voltages. Expressed in decibels.
The smaller the values of line regulation, load regulation, and temperature stability, the better the regulator.
IC voltage regulators are multipurpose and have features as programmable output, current/voltage boosting,
internal short-circuit current limiting, thermal shutdown and floating operations for high-voltage applications.
Types of IC voltage regulators are:
(1) Fixed output voltage regulators: Positive and negative output voltage
(2) Adjustable output voltage regulators: Positive or negative output voltage
(3) Switching regulators
(4) Special regulators

SERIES VOLTAGE REGULATOR USING OP-AMP:

Figure 8.01 shows the circuit diagram of series voltage regulator using op-amp.
The op-amp is used as a comparator. It
+ T + compares the part of the output voltage Vo
VI R obtained from potential divider circuit as a
−N 3 2 + V CC
R − feedback with the reference voltage
V(+ + 7 1 VO
) 6 generated by the zener diode Vz.
V(−) 741 The output of the op-amp drives the series
3  4
R pass transistor T.
VE
E L If there is any change in output voltage the
+ control signal from op-amp control the
R conduction of the transistor T. Thus the
VZ 2
− output voltage is maintained at a constant
level.
Figure 8.01: Series voltage regulator using op-
amp
From virtual ground
concept V (−) = V(+)
V (−) = V(+)= [Vo/(R1+R2 )]
R2
The voltage at non-inverting terminal V+ is nothing but the zener voltage Vz as shown in figure
8.01. V(+) = Vz
The output voltage can be expressed as: Vo = [(R1+R2)/R2 ] V(+); Vo=[(R1+R2)/R2 ]
Vz Hence, Vo=[1+R1/R2 ] Vz

FIXED VOLTAGE REGULATORS:

Positive fixed voltage regulator: 78XX series is a positive voltage regulator ICs. It is 3-terminal IC. First terminal
is input , second terminal is ground and third terminal
TheseisICs
output, as shown
are fixed voltagein regulators
figure 8.02.and can deliver output
current of 1Amp. These ICs has internal thermal over load
Vin 1 78XX 3 VOUT
protection and short-circuit protection. Capacitor Ci, is
C 2 C required if the regulator is located at considerable distance
i o from a power supply filter. Capacitor Co, is used to improve
the transient response of the regulator. Ground pin no.2,
should be common for both input and output pins, for proper
Figure 8.02: Positive voltage regulator operation.
IC The dropout voltage, (Vin − VOUT), must be typically 2.0V even during the
low point on the input ripple voltage.
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Table 1.1 shows the 7800 series voltage regulators with seven voltage
options: Device type Output Voltage (Vo) Maximum Input Voltage (Vin)
7805 5.0 35
7806 6.0 35
7808 8.0 35
7812 12.0 35
7815 15.0 35
7818 18.0 35
7824 24.0 40
TABLE 1.1

Negative fixed voltage regulator: 79XX series is a negative voltage regulator ICs. It is 3-terminal IC as ground,
input and output.
Table 1.2 shows the 7800 series voltage regulators with seven voltage options:
Device type Output Voltage (Vo) Maximum Input Voltage (Vin)
7902 −2.0 −35
7905 −5.0 −35
7905.2 −5.2 −35
7906 −6.0 −35
7908 −8.0 −35
7912 −12.0 −35
7915 −15.0 −35
7918 −18.0 −35
7924 −24.0 −40
TABLE 1.2
ADJUSTABLE VOLTAGE REGULATORS:
A single IC which satisfies the voltage requirement from 1.2V to 57 V, is adjustable voltage regulator. LM317
series is the most commonly used adjustable voltage regulators.
Advantages of adjustable over fixed voltage regulators:
1) Improved system performance by having line and load regulation of a factor of 10 or better.
2) Improved overload protection allows greater output current over operating temperature range.
3) Improved system reliability with each device being subjected to 100% thermal limit burn-in.

Adjustable positive voltage regulators:

Figure 8.03 shows the typical connection diagram of LM317 series adjustable 3-terminal positive voltage
regulator.
The 3-terminals are: Vin, VOUT and ADJUSTMENT (ADJ). From
LM31 figure 8.03, LM317 requires only two resistors (R1=
7 VOU VOU
Vin 240Ω and R2= 3kΩ) to set the output voltage. When
T T
AD
I1 R configured, LM317 produces a 1.25 V, referred as
J
IAD 1 reference voltage (VREF), between the output and adjustment
Vin
J LOAD
terminal. Since this reference voltage is constant,
R
current I1 is also constant for a given value of R1. Resistor R1
2
is called as current set or program resistor. Current (I1 +
IADJ), flows through the output set resistor R2.
Referring to the connection diagram, we will
Figure 8.03: Connection diagram of determine the output voltage expression as:
Positive adjustable voltage regulator
The output voltage, VOUT = R1.I1 + R2(I1 + IADJ )-----(6.5)
Where, I1 = (Drop across R1)/ R1 = (VREF)/R1
R1 = Current (I1) set resistor
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Substituting the value ofRI1 in equation 6.5, we get:

V0 = V (1 + 2
) A+
DJI R -------------------------------------
R1
(6.6)
REF 2
Where, VREF = 1.25V and however IADJ is very small (100µA) and constant. Therefore, drop across resistor R2 is very small and can be
neglected.
Hence, V0 = V (1 + R2) ---------------------------------------
R1
(6.7) REF
Equation 6.7 indicated that the output voltage Vo is a function of resistor R2 for a given value of resistor R1
and can be varied by adjusting the value of resistor R2. To achieve good regulation, resistor R1 shoud be tied
directly to the output of the regulator, as shown in figure 8.03.
Table 1.3 shows the different grade LM317 regulators.
Device Vo (V) Io (A) Vin (max) in volts Ripple rejection (dB)
LM317 1.2 to 37 1.5 40 80
LM317H 1.2 to 37 0.5 40 80
LM317HV 1.2 to 57 1.5 60 80
LM317HVH 1.2 to 37 0.50 40 80
LM317L 1.2 to 37 0.10 40 65
LM317M 1.2 to 37 0.50 40 80
Table 1.3
The different grades of regulators in the series are available with output voltage of 1.2 to 57V and output
current from 0.10 to 1.5A. These ICs are available in standard transistor packages that are easily mounted and
handled.

Adjustable negative voltage regulator:

LM337 series is adjustable negative voltage regulators devices. These are available in same voltage and
current options as LM317Devicedevices. Vo (V)1.4 shows
Table Vin (max) in
Io (A)the different volts of Ripple
grades rejection
regulators in the(dB)
series.
LM337 −1.2 to −37 1.5 40 77
LM337H −1.2 to −37 0.5 40 77
LM337HV −1.2 to −47 1.5 50 77
LM337HVH −1.2 to −47 0.50 50 77
LM337LZ −1.2 to −37 0.10 40 65
LM337M −1.2 to −37 0.50 40 77
TABLE 1.4
Disadvantage: Fixed and adjustable voltage regulators such as 78XX, 79XX and LM317 and LM337 are called as
series dissipative regulators because these regulators creates a variable resistance between the input voltage and
the load, and hence function in a linear mode. Thus linear regulator maintains a constant output voltage by
dissipating the excess power as heat. Conversion efficiency of series dissipative regulator decreases as the
input/output voltage increases or vice versa. Hence, for this reason the linear series regulator is matched with
medium current applications, where power dissipation can be handled with heat sinks.

SWITCHING REGULATORS:
To improve the conversion efficiency of regulator, the series-pass transistor is used as a switch, rather than as a
variable resistor as in linear series regulator. A regulator constructed in this manner is called as switching
regulator. In switching regulators, a series pass transistor is used to switch between cut off and saturation at a
high frequency, which produces a pulse width modulated square wave output. This PWM output is then filtered
through a Low Pass LC filter to produce an average DC output voltage. The conversion efficiency of this regulator
is independent of input/output differential and can approach up to 95%.
Switching regulators comes in various configurations such as: Fly back, feed forward, push pull, and non-isolated
single ended or single polarity types.

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The way, in which the components (switch and filter) are connected, the switching regulators can operates in
any of the three modes: Step down, step up, or polarity inverting.
Basic Switching regulator:
Basic switching regulator has 4-major components: (i) Voltage source VIN (ii) Switch S1 (iii) Pulse generator VPulse and (iv) Filter F1.

Figure 8.04 shows the interconnection between the components of basic switching regulator. (i)Voltage Source, VIN :
Supply Voltage source VIN may be any DCsupply ie. a battery or an unregulated or a regulated voltage. Following requirements
must satisfy by the voltage source are:
1) The losses associated with voltage source and the required output power must be supplied by voltage
source.
2) It must be large enough to supply satisfactory dynamic range for line and load variations.
3) It must be sufficiently high to meet the minimum requirement of(ii)Switch S1: system
the regulator Transistor or designed.
to be thyristor is
used as power switch. Switch is
4) During power failure, voltage source should store energy for specified amount of time, for a back up.
Switch S1 Filter F1 operated in saturated mode. Generally
output of pulse generator used to turn
Supply Voltage the switch ON and OFF.
VIN
LOA
(iii)Pulse Generator VPulse: It produces an
+ Pulse asymmetrical square wave varying in
Generator D
either frequency or pulse width called
−
frequency modulation or pulse width
modulation. Effective frequency range of
pulse generator is around 20kHz and is
Figure 8.04: Connection diagram of basic switching well within the switching speeds of
regulator transistors and diodes.
The duty cycle of pulse waveform is given as
:duty cycle = 0N =
0N
= (0 ∙ f);Where, Ot = on-time of the pulse
waveform 0N+0FF T
N N

tOFF = off-time of the pulse waveform; T = time period.

Typical operating frequencies of switching regulators range from 10 to 50 kHz.
(iv) Filter F1: Filter is one of the major components in filter designing. The basic filter types are RC,RL and RLC,
which are used in switching regulators. The RLC filter is most commonly used filter. Filter F1 converts the pulse
into a DC voltage.
Output Voltage VO , is a function of duty cycle and input voltage V , and is expressed as0: V =0N T
(
)×V IN IN
Expression of output Voltage VO, indicates that when time period T is held constant, VO is directly proportional to the on-time, tON for a

given value of VIN. This method of changing the output voltage by varying tON is referred to as pulse width modulation (PWM). Similarly,

if tON is held constant, output voltage is inversely proportional to time period, T or directly proportional to frequency f of
pulse waveform. This method of changing the output voltage by varying frequency f, is referred to as frequency
modulation (FM).
Switching regulators are used in commercial switching supplies with multiple outputs. µA78S40 is an example of
switching regulator.

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DUAL POWER SUPPLY:

Figure 8.05 shows the circuit diagram of dual DC power
supply. Bridge rectifier circuit, which will convert the
ac supply into dc supply. The output of the
IN 1 IC78X OU rectifier circuit ie. DC, contains the ripples in
X 3
T the output voltage. To filter out these ripples,
2
+ capacitors C1 and C2 are used. The output of
C GN +VOUT the capacitor that is pure DC is given to
Bridge Rectifier
−
1 D voltage regulator IC78XX and IC79XX which
output. Ie. DC
which contains + will regulate the output voltage at +XX
C
ripples − 2 Volt and
GN
–XX Volt DC, despite the change in input
D 1 −VOU
IN T voltage.
OUT2 IC79X 3
X
Figure 8.05: Dual DC power
supply

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