Chapter – 2

Basic Computer Organization

And Design

 Lecture 2.2
• Common Bus
Basic Computer Organization & Design 2 Registers

BASIC COMPUTER REGISTERS

Registers in the Basic Computer

11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
Computer Organization Computer Architectures Lab
How registers, memory and I/O device communicates
• Path must be provided to transfer information between these eight registers and memory.
• The number of wires will be excessive if connections are made between the outputs of each register and the
inputs of other register.
• A more efficient way is to use a common bus system using a multiplexer or three state buffer gates.
• The outputs of the seven register and memory is connected to the bus.
• The specific output that is selected for the bus lines at any given time is determined from the binary value of
the selection variables S2, S1, and S0.
Basic Computer Organization & Design 4 Registers

COMMON BUS SYSTEM

S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1

LD INR CLR
PC 2
LD INR CLR

DR 3

LD INR CLR
E
ALU AC 4

LD INR CLR

INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 5 Registers

COMMON BUS SYSTEM

• Control variables: the bus is controlled by
1- Selection switches for selecting the source of information.
.
S2 S1 S0 Register
0 0 0 x
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory

2- Enable switches at the destination device to accept the information.

• Load input (LD): Enables the input of a register to download bits form
the common bus. When LD = 1 for a register, the data on the common
bus is load into the register.
–The 12-bit registers, AR and PC, have 0’s loaded onto the bus in the high order 4
bit positions
–When the 8-bit register OUTR is loaded from the bus, the data comes from the low
order 8 bits on the bus

Computer Organization Computer Architectures Lab

Operations involve AC and DR Registers
+Accumulator(AC) : takes input from ALU.
+ The ALU takes input from DR, AC and INPR :
o ADD DR to AC, AND DR to AC
Note : -
+Input register is not connected to the bus.
+The input register is connected only to the ALU
Exercise
• The following register transfers are to
be executed in the system as below.
• For each transfer, specify:
1. The binary value that must be applied to bus selected inputs s2, s1,
s0.
2. The register whose LD control input must be active.
3. A memory read or writes operation (if needed).
S2 S1 S0 Register
0 0 x
0 1 AR
1 0 PC
1 1 DR
0 0 AC
0 1 IR
1 0 TR
1 1 Memory

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Lecture Outline
—Computer Instructions
—Addressing Modes
—Computer Instructions
—Timing and Control
—Instruction Cycle
 Mano’s Basic Computer
Instruction Format

• Mano’s Computer (4K word memory, Each word is 16 bits long).

—the memory contains 4096 (= 212) words,
—we needs 12 bit to specify which memory address this
instruction will use.
• In the Basic Computer, bit 15 of the instruction specifies the
addressing mode (0: direct addressing, 1: indirect addressing)
• Since the memory words, and hence the instructions, are 16 bits
long, that leaves 3 bits for the instruction’s opcode.
Instruction Format

1514 1211 0
I Opcode Address
Addressing
mode
 Mano's Computer: Instructions Formats
Each instruction occupies one Memory Words (16 bits).
Bit 15 of the instruction specifies the addressing mode (0: direct
addressing, 1: indirect addressing)

15 12 11 0

• 3-bit opcode Bits 14-12

• How many possible instructions?
— 23=8
• This leaves 12 bits for the address
— How many words of memory?
— 212 = 22•210 = 4K = 4096 16-bit words
 ADDRESSING Instruction codes

MODES
• The address field of an instruction can represent either
— Direct address: the address filed indicates the address of an operand, or
— Indirect address: the address filed indicates the address of address of an operand or
operand accessed indirectly.
Direct addressing Indirect addressing
22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand
1350 Operand

+ +
AC AC

• Effective Address (EA)

— The address, that can be directly used without modification to access an operand for a
computation-type instruction, or as the target address for a branch-type instruction
Exercise
• The content of PC in the basic computer is 3AF (all are
in hexadecimal). The content of AC is 7EC3. The
content of memory at address 3AF is 932E. The content
of memory at address 32E is 09AC. The content of
memory at address 9AC is 8B9F.

 What is the instruction that will be fetched and executed next?

 Show the binary operation that will be performed in the AC
when the instruction is executed.
 Give the contents of registers PC,AR, DR, AC, and IR in
hexadecimal
BASIC COMPUTER INSTRUCTIONS CATEGORIES

• Instructions may be placed in several different kinds of categories based on

location of instructions.
— Register reference : - Referencing CPU registers for data processing.
— Memory reference : Referencing memory for data processing.
— I/O reference : program that interact with peripheral devices for data
processing.

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 BASIC COMPUTER
INSTRUCTIONS
Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
• Only 3 bits are used for
ADD 1xxx 9xxx Add memory word to AC opcode. It may seem that
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory the computer is restricted
BUN 4xxx Cxxx Branch unconditionally to 8 operations.
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

• However, since R-R and
CLE 7400 Clear E I/O instructions use the
CMA 7200 Complement AC
CME 7100 Complement E remaining 12 bits as part
CIR 7080 Circulate right AC and E of the operation code.
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive • The total number of
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero instruction chosen for the
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer basic computer is 25.
INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag 16
ION F080 Interrupt on
IOF F040 Interrupt off
CONTROL UNIT
 The function of control unit : -
—Generate relevant timing and control signals to all
operations in the computer.
—It controls the flow of data between the processor and
memory and peripherals.
 Control units are implemented in one of two ways
 Hardwired Control
 CU is made up of sequential and combinational circuits to generate the
control signals
 Microprogrammed Control
 A control memory on the processor contains microprograms that activate
the necessary control signals
CONTROL UNIT HARDWARE (Hardwired)
• Inputs to the control unit come from IR where an instruction is stored.
• A hardwired control is implemented using:
> A 3x8 decoder to decode opcode bits 12-14 into signals D0, ..., D7;

A flip-flop (I) to store the addressing mode bit in IR

TIMING AND CONTROL

Control unit of Basic Computer

Instruction register (IR)

15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I Combinational
D7 Control Control
logic signals

T15
T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter 19
(SC) Clock
 TIMING AND CONTROL
 Step1: Where do we fetch the next instruction from
at T0 (start time)?

 The Program Counter register (PC) is assumed to hold the

address of the next instruction to be executed.

 The PC is transferred to the Address Register (AR) which is

connected to the Address Bus Multiplexer.

T0 : AR = PC
 Timing and Control
• Step 2: How do we obtain the instruction from
memory at T1?
– The instruction code is transferred immediately to the
Instruction Register (IR)

T1 : IR = M[AR] , PC = PC + 1

Memory
Data bus
INC
M[AR] IR LD PC

CPU bus
AR LD
Address bus
 Timing and Control
• Step 3: How do we decode the instruction intention (ie.
meaning, operational
NOTE:
definition) at T2?
–AllThe OpCode, Mode and Address field bits all serve as inputs
instructions share the steps T0,
to the Control Logic Gates that select the specific instruction
T1 and T2.
semantics
However, depending on what each
• Direct
specific addressing
instruction the next steps
will addressing
• Indirect various.
• CPU register addressing
• Input
• Output

T2 : {D0,...,D7} = DEC( IR(12-14) ),

AR = IR(0-11),
I = IR(15)
 Timing and Control
• The instruction cycle consists of a controlled sequence of
microoperations using control logic gates and a sequence counter.
I OpCode Address
IR 15 14 13 12 11 0

2 1 0
Signal the SC to
3x8 DEC advance (INC) to
7 6 5 4 3 2 1 0 next timing
value, or reset.
Control
Control
Logic
Outputs
Timing inputs Gates
F E D C B A 9 ... 1 0
4x16 DEC
3 2 1 0
4-bit INC
Sequence
Counter (SC) CLR
INSTRUCTION CYCLE

 In Basic Computer, a machine instruction is executed in

the following cycle:
1. Fetch an instruction from memory
2. Decode the instruction and calculate effective address (EA)
3. Read the EA from memory if the instruction has an indirect address
(Fetch operand)
4. Execute the instruction

 After an instruction is executed, the cycle starts again at

step 1, for the next instruction

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 Instruction Cycle

FETCH AND DECODE

• Fetch and Decode T0: AR PC (S0S1S2=010, T0=1)

T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1
S2
T0 S1 Bus

S0
Memory
7
unit
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock 25
Common bus
 Instrction Cycle

DETERMINE THE TYPE OF INSTRUCTION

Start
SC 

T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference) =>opcode ≠ 111

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7IT3: AR M[AR]
D'7I'T3: Nothing
26
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
 Instruction Cycle

REGISTER REFERENCE INSTRUCTIONS

Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3

r = D7 IT3 => Register Reference Instruction

Bi = IR(i) , i=0,1,2,...,11
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1) 27
SZE rB1: if (E = 0) then (PC  PC+1)
HLT rB0: S  0 (S is a start-stop flip-flop)
 MR Instructions

MEMORY REFERENCE INSTRUCTIONS

Operation
Symbol Symbolic Description
Decoder
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1
- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T 3 when I = 1

- The execution of MR instruction starts with T4

AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4: DR  M[AR] Read operand 28
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E
 MEMORY REFERENCE INSTRUCTIONS
LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC  0 **
BUN: Branch Unconditionally
D4T4: PC  AR, SC  0
BSA: Branch and Save Return Address
D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SCPC,
Memory, AR
0 at time T4 Memory, PC after execution
20 0 BSA 135 20 0 BSA 135
PC = 21 Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

29
1 BUN 135 1 BUN 135
Memory Memory
 Memory Reference Instructions
• Branch UNconditional instruction
– I = 0 :: Replace PC by address in IR(0-11)
– I = 1 :: Replace PC by the address found at the address in IR(0-11)
• That is :: PC = M[ M[ IR(0-11) ] ]

Operation Codes
Direct Indirect
I=0 I=1 Mnemonic RTL
4 C BUN AR = IR(0-11)
PC = AR
 Memory Reference Instructions
• Branch and SAve instruction
– Used for programming subroutine calls
Operation Codes
Direct Indirect
I=0 I=1 Mnemonic RTL
5 D BSA AR = IR(0-11)
M[AR] = PC , PC = AR + 1

(a) BEFORE SUBROUTINE CALL (b) AFTER SUBROUTINE CALL

M M

PC Subr. call instr. PC Subr. call instr.

Return addr.
Subr. entry instr. Subr. entry instr.
 Memory Reference Instructions
• Increment and Skip if Zero instruction
– Used to implement a counter based <do-while> construct
ISZ: Increment and Skip-if-Zero
D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T4: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0

(a) BEFORE (b) AFTER

M M

PC Current instr. PC < 0 Current instr.

Branch instr. Branch instr.

Continue instr. Continue instr.

=0
AR AR
Data value Data value + 1
 MR Instructions
FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS

Memory-reference instruction

AND ADD LDA STA

D0 T 4 D1 T 4 D2 T 4 D 3T 4
DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0

D0 T 5 D1 T 5 D2 T 5
AC  AC  DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D4 T 4 D5 T 4 D6 T 4
PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D5 T 5 D6 T 5
PC  AR DR  DR + 1
SC  0
D6 T 6
M[AR]  DR
If (DR = 0) 33
then (PC  PC + 1)
SC  0
 EXERCISE
 An instruction at address 021 in the basic computer has I
= 0, an operation code of the AND instruction, and an
address part equal to 083(all are in hexadecimal). The
memory word at address 083 contain an operand B8F2
and the content of AC is A937. Go over the instruction
cycle and determine the contents of the following
registers at the end of the execution phase: PC, AR, DR,
AC, and IR. Do the problem for all memory reference
instructions.
35