Chap.

7 Microprogrammed Control(Control Unit) 7-1

 7-1 Control Memory

 Control Unit
 Initiate sequences of microoperations
» Control signal (that specify microoperations) in a bus-organized system
 groups of bits that select the paths in multiplexers, decoders, and arithmetic logic units
 Two major types of Control Unit
» Hardwired Control : in Chap. 5
 The control logic is implemented with gates, F/Fs, decoders, and other digital circuits
 + Fast operation, - Wiring change(if the design has to be modified)
» Microprogrammed Control : in this Chapter
 The control information is stored in a control memory, and the control memory is programmed
to initiate the required sequence of microoperations
 + Any required change can be done by updating the microprogram in control memory,
- Slow operation
 Control Word
 The control variables at any given time can be represented by a string of 1’s and
0’s.
 Microprogrammed Control Unit
 A control unit whose binary control variables are stored in memory (control
memory).

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 Microinstruction : Control Word in Control Memory

 The microinstruction specifies one or more microoperations

 Microprogram
 A sequence of microinstruction
» Dynamic microprogramming : Control Memory = RAM
 RAM can be used for writing (to change a writable control memory)
 Microprogram is loaded initially from an auxiliary memory such as a magnetic disk
» Static microprogramming : Control Memory = ROM
 Control words in ROM are made permanent during the hardware production.
 Microprogrammed control Organization : Fig. 7-1
 1) Control Memory
User Program
» A memory is part of a control unit : Microprogram 이 저장되어 있음
» Computer Memory (employs a microprogrammed control unit) Machine Instruction
 Main Memory : for storing user program (Machine instruction/data)
 Control Memory : for storing microprogram (Microinstruction) Microprogram
 2) Control Address Register
Microinstruction
» Specify the address of the microinstruction
 3) Sequencer (= Next Address Generator) Microoperation
» Determine the address sequence that is read from control memory
» Next address of the next microinstruction can be specified several way depending on
the sequencer input : p. 217, [1, 2, 3, and 4]

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 4) Control Data Register (= Pipeline Register )

» Hold the microinstruction read from control memory
» Allows the execution of the microoperations specified by the control word simultaneously
with the generation of the next microinstruction
 RISC Architecture Concept
 RISC(Reduced Instruction Set Computer) system use hardwired control rather than
microprogrammed control : Sec. 8-8
 7-2 Address Sequencing
 Address Sequencing = Sequencer : Next Address Generator
 Selection of address for control memory

 Routine Subroutine : program used by other ROUTINES

 Microinstruction are stored in control memory in groups
 Mapping
 Instruction Code Address in control memory(where routine is located)
 Address Sequencing Capabilities : control memory address
 1) Incrementing of the control address register
 2) Unconditional branch or conditional branch, depending on status bit conditions
 3) Mapping process ( bits of the instruction address for control memory )
 4) A facility for subroutine return

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 Selection of address for control memory : Fig. 7-2

 Multiplexer

 CAR Increment In s tr u c tio n c o d e

 JMP/CALL M a p p in g
lo g ic
 Mapping
   
 Subroutine Return S ta tu s B ra n c h
lo g ic
M UX
s e le c t
M u lt ip le x e r s
b it s
 CAR : Control Address Register S u b r o u tin e
r e g is e r
» CAR receive the address from (S B R )
C o n tro l a d d r e s s re g is te r
C lo c k
4 different paths (C A R )

1) Incrementer
In c re m e n te r
2) Branch address from
control memory
3) Mapping Logic C o n tro l m e m o ry

4) SBR : Subroutine Register

 SBR : Subroutine Register S e le c t a s t a t u s M ic r o o p e r a t io n s
b it
» Return Address can not be stored
B ra n c h a d d re s s
in ROM
» Return Address for a subroutine is
stored in SBR

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 Conditional Branching
 Status Bits
» Control the conditional branch decisions generated in the Branch Logic
 Branch Logic
» Test the specified condition and Branch to the indicated address if the condition is met ;
otherwise, the control address register is just incremented.
 Status Bit Test 와 Branch Logic 의 실제 회로 : Fig. 7-8
» 4 X 1 Mux 와 Input Logic(Tab. 7-4) 으로 구성
 Mapping of Instruction : Fig. 7-3
Opcode

Computer Instruction 1 0 1 1 Address

Mapping bits 0 x x x x 0 0

Microinstruction Address 0 1 0 1 1 0 0
 4 bit Opcode = specify up to 16 distinct instruction
 Mapping Process : Converts the 4-bit Opcode to a 7-bit control memory address
» 1) Place a “0” in the most significant bit of the address
» 2) Transfer 4-bit Operation code bits
» 3) Clear the two least significant bits of the CAR ( 즉 , 4 개의 Microinstruction 수용 가능 )
 Mapping Function : Implemented by Mapping ROM or PLD
 Control Memory Size : 128 words (= 27)

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 Subroutine
 Subroutines are programs that are used by other routines
» Subroutine can be called from any point within the main body of the microprogram
 Microinstructions can be saved by subroutines that use common section of
microcode
» 예제 ) Memory Reference 명령에서 Operand 의 Effective Address 를 구하는 Subroutine
 p. 228, Tab. 7-2 에서 INDRCT ( 여기에서 FETCH 와 INDRCT 는 Subroutine)
 Subroutine 은 ORG 64, 즉 1000000 - 1111111 에 위치 (Routine 은 0000000 - 0111111)
 Subroutine must have a provision for
» storing the return address during a subroutine call
» restoring the address during a subroutine return
 Last-In First Out(LIFO) Register Stack : Sec. 8-7
 7-3 Microprogram Example
 Computer Configuration : Fig. 7-4
 2 Memory : Main memory(instruction/data), Control memory(microprogram)
» Data written to memory come from DR, and Data read from memory can go only to DR
 4 CPU Register and ALU : DR, AR, PC, AC, ALU
» DR can receive information from AC, PC, or Memory (selected by MUX)
» AR can receive information from PC or DR (selected by MUX)
» PC can receive information only from AR
» ALU performs microoperation with data from AC and DR ( 결과는 AC 에 저장 )
 2 Control Unit Register : SBR, CAR

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 Instruction Format
 Instruction Format : Fig. 7-5(a)
» I : 1 bit for indirect addressing
M UX
» Opcode : 4 bit operation code
10 0
» Address : 11 bit address for system memory AR

 Computer Instruction : Fig. 7-5(b) A d d re s s M e m o ry

2048× 16

» 16 명령어가 가능하며 4 개만 표시 10
PC
0

 Microinstruction Format : Fig. 7-6

 3 bit Microoperation Fields : F1, F2, F3 M UX

» 총 21 개 Microoperation : Tab. 7-1 6 0 6 0

15 0
» 동시에 3 개의 microoperation 실행 가능 SBR CAR
DR

 3 개 이하일 경우 , 000(no operation) 으로 채움

» two or more conflicting microoperations can
not be specified simultaneously C o n tro l m e m o ry
128× 20
A rith m e tic
lo g ic a n d
s h if t u n it
 예제 ) 010 001 000
Clear AC to 0 and subtract DR from AC at the C o n tro l u n it

same time 15 0
AC

» Symbol DRTAC(F1 = 100)

 stand for a transfer from DR to AC (T = to)

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 2 bit Condition Fields : CD

» 00 : Unconditional branch, U = 항상 1
» 01 : Indirect address bit, I = DR(15)
» 10 : Sign bit of AC, S = AC(15)
» 11 : Zero value in AC, Z = AC = 0
 2 bit Branch Fields : BR
» 00 : JMP
 Condition = 0 : 1 CAR  CAR  1
 Condition = 1 : 2 CAR  AD
» 01 : CALL Save Return Address
 Condition = 0 : 1 CAR  CAR  1
 Condition = 1 : 2 CAR  AD, SBR  CAR  1
» 10 : RET CAR  SBR
Restore Return Address
3
» 11 : MAP CAR(2  5)  DR(11  14), CAR(0, 1, 6)  0
4
 7 bit Address Fields : AD
» 128 word : 128 X 20 bit
 Symbolic Microinstruction
 Label Field : Terminated with a colon ( : )
 Microoperation Field : one, two, or three     
n
symbols, separated by commas Label Microoperat CD BR AD
ORG 64
 CD Field : U, I, S, or Z FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
 BR Field : JMP, CALL, RET, or MAP DRTAR U MAP 0

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 AD Field
a. Symbolic Address : Label ( = Address )
b. Symbol “NEXT” : next address
c. Symbol “RET” or “MAP” : AD field = 0000000
 ORG : Pseudoinstruction(define the origin, or first address of routine)
 Fetch (Sub)Routine
 Memory Map(128 words) : Tab. 7-2, Tab. 7-3
» Address 0 to 63 : Routines for the 16 instruction( 현재는 4 instruction)
» Address 64 to 127 : Any other purpose( 현재는 Subroutines : FETCH, INDRCT)
 Microinstruction for FETCH Subroutine
» AR  PC Opcode Fetch
» DR  M [ AR ], PC  PC  1
» AR  DR(0  10), CAR(2  5)  DR(11  14), CAR(0, 1, 6)  0 Opcode Decode

Operand Address Mapping Instruction

15 14 Format
11 10 …. … 0

I Opcode Address
 Fetch Subroutine : address 64
» Label Microoperat CD BR AD
ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP 0

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 Symbolic Microprogram : Tab. 7-2

 The execution of MAP microinstruction in FETCH subroutine
» Branch to address 0xxxx00 (xxxx = 4 bit Opcode)
 ADD : 0 0000 00 = 0
 BRANCH : 0 0001 00 = 4
 STORE : 0 0010 00 = 8
 EXCHANGE : 0 0011 00 = 12, ( 16, 20, … , 60 )
 Indirect Address : I = 1
» Indirect Addressing : AR  M [ AR ]
 AR 이 지시하는 메모리 내용을 DR 에 읽은 후 , 다시 AR 에 써 넣는다
» INDRCT subroutine
Label Microoperat CD BR AD
INDRCT: READ U JMP NEXT DR  M [ AR ]
DRTAR U RET 0 AR  DR
 Execution of Instruction
» ADD instruction 실행 절차
 1) ADD 명령이 실행되면 FETCH subroutine 에서 Opcode 를 fetch 한 후 , MAP 이 실행되면
MAP Process 에 의해 CAR = 0 0000 00 으로 branch 한다 ( 여기서 Opcode = 0000, Fig. 7-5(b)
)
 2) ADD 명령의 Address 0 에서는 CD 비트를 검사하여 Indirect = 1 이면 INDRCT subroutine
에서 Effective Address 를 AR 에 써넣고 Return 한다 .
 3) ADD 명령의 Address 1 에서는 AR 이 지시하는 Memory 의 내용을 읽어서 DR 에 써넣는다 .
 4) ADD 명령의 Address 2 에서는 AC + DR 을 AC 에 저장한 후 , FETCH subroutine 으로
Branch 하면 1) 에서와 같은 방법으로 PC 가 지시하는 명령어를 Fetch 하여 MAP 수행 결과에
따라 해당 Routine Address 로 Branch 한다 .

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» BRANCH instruction 실행 절차
 1) BRANCH 명령의 Address 4 에서는 CD Bit 를 검사하여 Sign(S) = 1 이면 Address 6
번으로 가서 Indirect 를 검사하고 ARTPC 에 의해 해당 Address 로 Branch 한 후 , FETCH 에
의해 PC 가 지시하는 다음 명령을 수행한다 .
 2) BRANCH 명령의 Address 4 에서 Sign = 0 이면 Branch 하지 않고 FETCH 에 의해 PC
가 지시하는 다음 명령을 수행한다 .
» STORE instruction 실행 절차
» EXCHANGE instruction 실행 절차
 Binary Microprogram : Tab. 7-3
 Symbolic microprogram(Tab. 7-2) must be translated to binary either by means
of an assembler program or by the user
 Control Memory
» Most microprogrammed systems use a ROM for the control memory
 Cheaper and faster than a RAM
 Prevent the occasional user from changing the architecture of the system
 7-4 Design of Control Unit
 Decoding of Microinstruction Fields : Fig. 7-7
 F1, F2, and F3 of Microinstruction are decoded with a 3 x 8 decoder
 Output of decoder must be connected to the proper circuit to initiate the
corresponding microoperation (as specified in Tab. 7-1)

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F1 F2 F3
» 예제 ) F1 = 101 (5) : DRTAR
F1 = 110 (6) : PCTAR 3× 8 decoder 3× 8 decoder 3× 8 decoder
 Output 5 and 6 of decoder F1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
are connected to the load input
of AR (two input of OR gate)
From DR
 Multiplexer select the data from AND
DR when output 5 is active ADD
 Multiplexer select the data from DRTAC
A rith m e tic
AC when output 5 is inactive lo g ic s h if t
u n it
PCTAR DRTAR
 Arithmetic Logic Shift Unit
» Control signal of ALU in hardwired Load
F ro m F ro m
control : p. 164, Fig. 5-19, 20 PC D R (0- 10 ) AC
» Control signal will be now come
from the output of the decoders 0 1
S e le c t
associated with the AND, ADD, M u lt ip le x e r s
and DRTAC.

Load
AR C lo c k

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 Microprogram Sequencer : Fig. 7-8

 Microprogram Sequencer select the next
E x te rn a l
address for control memory (M A P )

 MUX 1  
L 3 2

1

0
Io
» Select an address source and route to CAR I1
In p u t
S 1 MUX 1 Load
lo g ic SBR
 CAR + 1 T S 0

 JMP/CALL
 Mapping
 Subroutine Return 1
Test
In c re m e n te r
I
» JMP 와 CALL 의 차이점 S
MUX 2

 JMP : AD 가 MUX 1 의 2 번을 통해 CAR 로 Z S e le c t

전송 C lo c k CAR
 CALL : AD 가 MUX 1 의 2 번을 통해 CAR 로
전송되고 , 동시에 CAR + 1(Return Address) 이
LOAD 신호에 의해 SBR 에 저장된다 .
 MUX 2
C o n tro l m e m o ry
» Test a status bit and the result of the test is
M ic ro o p s
applied to an input logic circuit CD BR AD

» One of 4 Status bit is selected by Condition bit (CD)

 Design of Input Logic Circuit
» Select one of the source address(S0, S1) for
CAR
» Enable the load input(L) in SBR

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 Input Logic Truth Table : Tab. 7-4

» Input :
 I0, I1 from Branch bit (BR)
BR Field Input MUX 1 Load SBR
 T from MUX 2 (T) I1 I0 T S1 S0 L
» Output : 0 0 0 0 0 0 0 0  CAR + 1
 MUX 1 Select signal (S0, S1) 0 0 0 0 1 0 1 0  JMP
S1 = I1I0’ + I1I0 = I1(I0’ + I0) = I1 0 1 0 1 0 0 0 0  CAR + 1
0 1 0 1 1 0 1 1  CALL
S0 = I1’I0’T + I1’I0T + I1I0
1 0 1 0 x 1 0 0  MAP
= I1’T(I0’ + I0) + I1I0 1 1 1 1 x 1 1 0  RET
= I1’T + I1I0
 SBR Load signal (L)
L = I1’I0T
CALL

Computer System Architecture Chap. 7 Microprogrammed Control Dept. of Info. Of Computer