CSPC 36

Microprocessors and
Microcontrollers

1st Unit
THE 8086 Microprocessor:
• Introduction to 8086
• Microprocessor architecture and Pin diagram
• Assembly language programming – Memory Segmentation & Addressing modes
• Assembly language programming -Instruction set and assembler directives
• Modular Programming
• Linking and Relocation
• Stacks
• Procedures
• Macros
• Interrupts and interrupt service routines
• Byte and String Manipulation.
 Internal
Architecture of
8086
 Memory Segmentation in 8086 Microprocessor
• Segmentation is the process in which the main memory of the computer is logically divided into
different segments.
• Minimum size of a segment can be 16 bytes and the maximum can be 64 kB.

• The BIU contains four 16 bit special purpose registers called as Segment Registers.

• Used for memory access:

• Code segment register (CS):  points to the code segment of the memory, where the executable program is
stored.

• Data segment register (DS): points to the data segment of the memory where the data is stored.

• Extra Segment Register (ES):  points to the another data segment in the memory.
• Stack Segment Register (SS): is used for addressing stack segment of the memory where stack data is
stored.
Rule of memory Segmentation : The four can overlap for

small programs and the segment can begin/start at

any memory address which is divisible by 16 (decimal value).

Segments are accessed by different pointers

• These segments can be overlapped if they don’t need the complete 64 KB space

• Can have the instruction, data or stack portion of a program to be more than 64KB by

using more than one code, data or stack segment

• Addresses within a segment can range from address = 00000h to address 0FFFFh. This

corresponds to the 64K-byte length of the segment.

 Addressing Modes
• Refers to the way in which the operand of an instruction is specified
• INSTRUCTION : Group of fields
• One field == Operation code / op code = indicating what the computer is to do
• Other fields == operands = indicates the information needed by the instruction in
carrying out its task.
• An operand may contain :
• a datum,
• at least part of the address of a datum,
• an indirect pointer to a datum,
• or other information pertaining to the data to be acted on by the instruction

Op code Operand ....... Operand

General Instruction Format

Basics
• Opcode destination, source ::::::::: MOV AX, BX

• Base segment address (16 bit) : Content of the 16bit segment registers CS, DS, ES, SS.

• Logical or offset or effective address (16 bit) : Content of the 16-bit IP, BP, SP, BX, SI or DI registers.

• It gives the displacement from the base address of the segment to the desired location within it.

• Logical address XXXX in the stack segment, is specified as SS:XXXX, which is equal to physical
address = [SS] * 16 + XXXX.

• Physical address or real address (20 bit) : Formed by combining the offset and base segment
addresses.

• It corresponds to the actual binary code output by the BIU on the address bus lines.

• Shifting segment address four bits to the left is equivalent to multiplying it by 16D or 10H
Data-Related Addressing Modes

1) Immediate

2) Direct

3) Register

4) Register Indirect

5) Register Relative

6) Based Indexed

7) Relative Based Indexed

• Immediate : The datum is 8/16 bits and is part of the instruction

• MOV DL, 08H, (DL)  08H

• MOV AX, 0A9FH, (AX)  0A9FH AH : 0AH & AL : 9FH

• The data must first be moved to a general-purpose registers and then to the segment register

• Not permitted: immediate data to segment register, memory location to memory location, segment register

to segment register and MOV to the CS segment register.

• MOV AX, 2550H ;

• MOV DS, AX Correct : Data is moved to AX and then to DS

• MOV DS, 0123H wrong instruction

• Direct : 16 bit effective address of the datum is part of the instruction

• MOV BX, [1354H] ; MOV BL, [0400H]

• The square brackets denotes the contents of the memory location.

• The physical address is calculated by combining the contents of offset location with DS = DS * 10H +
[offset]
• Example: DS = 1512H;

• MOV BX, [2400]; Physical Address = 15120 + 2400 = Content of [17520]  BX

• MOV BL, 3BH;

• MOV [3518], BL;

• First 3BH is copied into BL

• Shifting DS left and adding it to the offset gives the PA = 15120H + 3518H = 18638H.

• After the execution of the second instruction, the memory location with address 18638H will contain the
value 3BH.
Register : MOV AX, CX

Datum is in the register that is specified by the instruction

• For 16 bit operand, register maybe AX, BX, CX, DX, SI, DI, SP or BP
• Only one of the operand can be of segment register
• They should only contain segment addresses not values
• Memory is not accessed when this addressing mode is executed
• CS cannot be used as destination operand

• MOV DS, CX (DS)  (CX)

• MOV SI, DX (SI)  (DX)
Register Indirect : Name of the register which holds the effective address (EA) will be specified in the
instruction. MOV CX, [BX]

• Registers used to hold EA are : BP, BX, DI and SI

• Physical address calculation : = DS * 10H + [BX or DI or SI] = SS * 10H + [BP]
• Content of the DS register is used for when SI, DI and BX are used in the instruction.

• SS register is used for base address calculation when BP is used in the instruction.

• Physical address Example : DS = 1120, SI = 2498, BX = 1234 and AX = 17FE

• MOV CX, [BX], MOV [SI], AX;

• contents of the memory location pointed to by DS:BX and DS:BX + 1, 1000:1234 moves into CX,.
Physical address = 11200+1234 = 12434H

• contents of AX are moved into memory locations with logical address DS:SI and DS:SI + 1; Physical
address = 11200 + 2498 = 13698.

• Low address = 13698H = FE, the low byte, High address = 13699H = 17, the high byte
Register Relative: MOV AX, 50H[BX]

• Effective address (EA) is sum of an 8 or 16 bit displacement and the contents of a base register or an index register

• EA = {(BX) or (BP) or (SI) or (DI)} + {8/16 bit Displacement}

• PA = Physical Address = segment reg. x 10 + offset reg. + 8/16 bit displacement

• Example :
• MOV AX, [BX+4]; move contents of DS:BX+4 into AX; Physical Address = DSx10 + BX+4
• MOV CH, [SI+5] ; move contents of the DS:SI+5 into CH; Physical Address = DSx10 +SI+5
• MOV AH, [DI+1] ; move contents of the DS:DI+1 into AH; Physical Address = DSx10 + DI+1
• MOV [BP+2], AL; move contents of AL into SS:BP+2; Physical Address = SSx10 + BP+2

• Assume that DS = 4500, SS = 2000, BX = 2100, SI = 1486, DI = 8500, BP= 7814, and AX = 2512.
• MOV [BX+20], AX; [= DSx10 + BX+20] location 47120 = (12) and 47121 = (25)
• MOV [SI+10], AX; [= DSx10 + SI +10] location 46496 = (12) and 46497 = (25 )
• MOV [DI+4], AX; [= DSx10 + DI +4] location 4D504 = (12) and 4D505 = (25)
• MOV [BP+12], AX; [= SSx10 + BP +12] location 27826 = (12) and 27827 = (25)
Based Indexed : MOV AX, [BX][SI]

• Effective address is sum of a base register and an index register, both of which are
specified by the instruction

= {(BX) or (BP)} + {(SI) or (DI)}

• PA = DS * 10 + (BX) + {(SI) or (DI)} = SS * 10 + (BP) + {(SI) or (DI)}

• Examples :
• MOV [BX+DI], CL ; move contents of CL into DS:BX+DI; PA = DSx10H + BX+DI

• MOV CH, [BX+SI] ; move contents of the DS:BX+SI into CH; PA= DSx10H + BX+SI
• MOV AH, [BP+DI] ; move contents of the SS:BP+SI into AH; PA = SSx10H + BP+DI
• MOV [BP+SI], AL ; move contents of AL into SS:BP+SI; PA= SSx10H + BP+SI
Relative Based Indexed : MOV AX, 50H[BX][SI]

• Effective address is sum of an 8 or 16 bit displacement and a based indexed address

= {(BX) or (BP)} + {(SI) or (DI) + {8/16 bit Displacement}

• PA = DS * 10H + (BX) + {(SI) or (DI)} + Displ. = SS * 10H + (BP) + {(SI) or (DI)} +

Displ.

• Examples:
• MOV [BX+DI+1], AX ; move contents of AX into DS:BX+DI+1; PA= DSx10H + BX+DI+1H

• MOV AX, [BX+SI+10] ; move contents of the DS:BX+SI+10 into AX; PA = DSx10H + BX+SI+10H

• MOV AH, [BP+DI+3] ; move contents of the SS:BP+SI+3 into AH; PA = SSx10H + BP+DI+3H

• MOV [BP+SI+6], AL ; move contents of AL into SS:BP+SI+6; PA= SSx10H + BP+SI+6

 Effective Address & Physical Address
Addressing Mode Effective Address Physical Address
Immediate Value will be in the instruction
Register Value will be in the register
Direct Value will be in the address location specified in the instruction
Register Indirect [(BX) or (BP) or (SI) or (DI)] (SS or DS) * 10H + [(BX) or (BP) or Segment register + Base
(SI) or (DI)] register or Index register
Register Relative {(BX) or (BP) or (SI) or (DI)} (SS or DS) * 10H + {(BX) or (BP) Segment register + Base
+ {8/16 bit Displacement} or (SI) or (DI)} + {8/16 bit or Index register +
Displacement} Displacement
Based Indexed {(BX) or (BP)} + {(SI) or (SS or DS) * 10H + {(BX) or (BP)} Segment register + Base
(DI)} + {(SI) or (DI)} register + Index register
Relative Based {(BX) or (BP)} + {(SI) or (DI) (SS or DS) * 10H + {(BX) or (BP)} Segment register + Base
Indexed + {8/16 bit Displacement} + {(SI) or (DI) + {8/16 bit register + Index register +
Displacement} Displacement
Effective Address & Physical Address

Register Indirect: Based Indexed:

Example ::::
BX = 0158 EA = 0158 EA = 0158 + 10A5 =11FD
DI = 10A5 PA = 21000 + 0158 = 21158 PA = 11FD + 21000 = 221FD
Displ = 1B57 Register Relative: Relative Based Indexed:
DS = 2100 EA = 0158 + 1B57 = 1CAF EA = 0158 + 10A5 + 1B57 =2D54
PA = 1CAF + 21000 = 22CAF PA = 2D54 + 21000 = 23D54
 Branch-Related Addressing Modes
• For the control transfer instructions, the
addressing modes depend upon whether the
destination location is within the same
segment or in a different one.

• Intersegment: If the location to which the

control is to be transferred lies in a different
segment other than the current one.
• It also depends upon the method of passing the destination
• Intrasegment :If the destination location lies address to the processor.
• Intrasegment Direct
in the same segment, the mode is called
• Intrasegment Indirect
intrasegment mode. • Intersegment Direct
• Intersegment Indirect
1.Intrasegment Direct:
• control is to be transferred to the same segment and the address appears directly in the instruction as an
immediate displacement value.

• The displacement is computed relative to the content of the instruction pointer

• Effective branch address: 8 or 16 bit displacement + current contents of IP

• In case of jump instruction

• Short Jump : the signed displacement (d) is of 8-bits (i.e. -128<d<+127 = destination range)

• Long jump : the signed displacement (d) is of 16 bits (i.e. -32768<d<+32767)

• It may be used with either conditional or unconditional branching

• Example : JMP SHORT LABEL

2. Intrasegment Indirect:
• The displacement to which the control is to be transferred is in the same segment in
which the control transfer instruction lies, but it is passed to the instruction indirectly.

• Effective branch address : the contents of a register or memory location

• Used only in unconditional branch instructions.

• Example: JMP [BX]; Jump to effective address stored in BX.

3. Intersegment Direct:the address to which the control is to be transferred is in a different segment
• The purpose is to provide a means of branching from one code segment to another.

• Here, the CS and IP of the destination address are specified directly in the instruction.

• Example: JMP [CS] : [IP] ==> JMP 5000H:2000H  Jump to effective address 2000H in segment 5000H.

4. Intersegment Indirect :
• Replaces the contents of IP and CS with the contents of two consecutive words in memory that are
referenced using data-related addressing modes except the immediate and register modes.

• Control is to be transferred lies in a different segment and it is passed to the instruction indirectly.

• Example: JMP [2000H]. Jump to an address in the other segment specified at effective address 2000H in
DS.
Example
• (BX) = 1256    (SI) = 528F    Displacement = 20A1 Then:

• With direct addressing, the effective branch address is the contents of:

20A1 + (DS)*1610

• With register relative addressing assuming register BX, the effective branch address is the
contents of:

1256 + 20A1 + (DS)*1610

• With based indexed addressing assuming registers BX and SI, the effective branch address is
the contents of:

1256 + 528F + (DS)*1610

 Thank You

Seminar