VLSI Design Cycle

Concept of EDA
Where simulation stands
Design cycle
EDA : The current Wikipedia definition of EDA is “the category of tools for designing and
producing electronic systems ranging from printed circuit boards (PCBs) to integrated
circuits. This is sometimes referred to as ECAD (electronic computer-aided design) or just
CAD.” The workshop attendees felt that this definition was somewhat narrow, as it focuses
mainly on the use of EDA technologies.

1. EDA consists of a collection of methodologies, algorithms and tools, which assist and
automate the design, verification, and testing of electronic systems.
2. It embodies a general methodology that seeks to successively refine a high-level
description to low-level detailed physical implementation for designs ranging from
integrated circuits (including system-on-chips), to printed circuit boards (PCBs) and
electronic systems.
3. It involves modeling, synthesis, and verification at every level of abstraction.

EDA: Software engineers use to design integrated circuits

Most tools focus on large digital ICs:
• Microprocessors (Intel, Sun, Motorola)
• Graphics chips (nVidia, S3)
• Digital signal processors (TI, Motorola)
If a city is as crowded as a chip and if you have to find out new routes with narrow lanes
 VLSI Design Methodologies

Design methodology
Process for creating a design
Methodology goals
• Design cycle
• Complexity
• Performance
• Reuse
• Reliability
FPGA
Full Custom
PLA
 Gate Array

In a gate array (sometimes abbreviated GA) or gate-array

based ASIC the transistors are predefined on the silicon wafer
Can the design process depends
on frequency of operation?
Complex CMOS transceiver design
 The same design we can specify with respect to its behavior, with respect to its structure
where at this level design would consist of a block diagram some cells and their
interconnections and finally the implementation level or the physical level.

In terms of the y diagram you can assume that there are several concentric circles as we
have shown out here and as we move away from the centre of this y towards outside
the design becomes more and more abstract. So when you are at the outer layer of the
circles we are at a very abstract level may be behavior structure or physical. But as we
go towards the inner side of this y the design becomes more and more detailed.
Structural description all Front end Behavioral level if you
basic building blocks will recall this specifies
the behavior of the
be some components and
the components may be
synthesis circuit or the system
without explaining
cells from the libraries.
how this behavior has
to be implemented or
Ph realized.
ys
ica
Ba
ld
ck es
en ign
d
 Synthesis is essentially a detailing out of the design
Suppose we have given behavioral description out here, now when we carry out
synthesis we translate this behavioral description into the corresponding structural
description this is the process of synthesis.

Translation from behavior to structure is also sometimes called front end design. So when
we talk about front end design or front end CAD tools we are essentially talking about the
translation from behavior to structure.

In implementation level the primary requirement is the interconnections of blocks. So the

process from structural to physical design transmission is called physical design and
sometimes this process of translation is also known as back end design or back end CAD
tools
 Algorithm / flowchart
Processor S B
Memory Outer most level
Bus

PCB
SoC

P
Behavior at the most abstract level a design can be specified by simply specifying the
algorithm or if it is a system label design you can also specify the flow chart. So algorithm or
flowchart is a very high level kind of a design specification. So when we synthesize a
algorithm or flow chart at the corresponding structural level we will have a some kind of a
block diagram - some basic building blocks and their interconnections. Now these basic
building blocks at the level of algorithm or flow chart will be something like processors,
memories, buses, other IO interface units. So at this abstract level we are more concerned
with a block diagram kind of a design, how these high level blocks are interconnected rather
than going into the details of it.
In Physical domain now we are either talking about a printed circuit board where each of
these modules or cells will correspond to 1 VLSI chip or we can talk of a multi chip module
were inside the same integrated circuit we have several silicon wafers which are
embedded on them and they are interconnected. So this PCB and MCM are very similar
kind of PCB the chips are put on a board MCM.

S B
Next lower level
Registers R1<-R2+R3
Multiplexers RTL
ALU

ASIC
FPGA

P
Now register transfer level design will look something like this. Suppose R1 assigned R2 plus
R3, there can be a number of conditions. If then else kind of thing there can be a number of
such register transfer operations you defined based on the inputs you give. So here we
specify the behavior. But we do not say that how these register banks are implemented,
how these adders, subtractors, are implemented. How many adders are there? So all those
details we do not specify.
But one can understand with respect to the algorithm description, as we had said earlier
this is a much more detailed description. This may correspond to the so called
microinstruction level. So at a very high level you can specify a processor with the external
IO pins and the instruction set. But as we go into the design of the control unit of the
processor, we will have to specify the different microinstructions.

Now this register transfer level behavior when

we translate into structure we get a design for
the blocks are registers multiplexers ALU’s and
similar register transfer level components.
Similarly when you map them into the physical
implementation. So you can either have an
application specified circuit or you can have a
prototype on a field programmable gate array.
 S B
Next lower level
Gates
FF Boolean eq
FSM

Cells

P
But as you recal the design further from the register transfer level the next natural jump will
take in to something like a logical level behavior specification where if it is a combination
logic we will specify the behavior by a set of Boolean expressions. If it is a sequential logic we
will specify by finite state machines. These represent the behavior of the circuit of the system
we try to design. Now as you know starting from the Boolean expression or FSM there are
many methods which are available for synthesis where we get a circuit where the basic
building blocks now become gates and flip flops, so we have now an interconnection of gates
and flip flops starting from the behavior at this level.
In the physical implementation you are working through the back end CAD tool. There is
something called a library it is sometimes also called technology library. Now in the library
you have the standard components already available - standard components like gates flip
flops , arithmetic logic units. So at this level once you have the gate level implementation
you simply replace each gate or each flip flop by the corresponding cell available from the
library. So now at this level you have actually a tentative layout on silicon where you have
the cells, these cells are fairly low level cells gates and flip flops and the way they are
interconnected.

S B
Next lower level
Transistors
Transistor/CMOS functions

And as you go even

further down you get a
design at the lowest
level. Well with respect
to the behavior; see
ultimately we want to
implement a circuit
Transistor layout typically in CMOS; using
CMOS technologies.

P
You can also specify the behavior of a CMOS net list with respect to the transistor
functions typically for digital circuits a transistor or a MOS transistor is modeled in a very
ideal way. We treat this as a simple switch. So each transistor is modeled as a switch this is
what we mean by the transistor functions.

Well with respect to some more simplified model, when you go to the structural level. We
get the actual net list of the transistors which is used to implement the behavior which we
specify out here and finally at the physical level we get the actual layout of the transistors.
 Logic design
RTL/
Boolean level Logic verification

Component Logic synthesis

stimulus
library
netlist

Logic simulation Technology map Cell library

performance netlist

Back
annotation Physical design

In synthesis we are talking about translating the behavior into the structural
specification.
we start with the level of logic design where the specification is given either in terms of
set of Boolean expressions. It can be FSM’s also or it can be slightly higher, it can be
register transfer level specifications also.
 We are specifying the behavior of the circuit and from there we are trying to go through
the different steps of synthesis. Now this diagram will show you what are the different
steps that we typically go through

logic synthesis is the block which accepts the

specification as the input and generates some But when you are trying to implement
kind of a synthesized net list as the output net it this net list may not be sufficient.
list means some basic components and their Why? See suppose you are trying to
interconnection. design using FPGA. So using FPGA you
have some constraints you know that
Now if the specification is in the terms of these are the functions I can
Boolean expressions, then this net list will implement using FPGA and these are
consist of gates possibly flip flops and then the things I cannot.
interconnections.

Simple example
Suppose we are trying to design using CMOS. Now in CMOS again we will be having some kind of a library available with
you where you will be getting a list of available gates or cells which you can use in your design. So the net list that we
have obtained through the logic synthesis process, the basic cells out there, they will have to be mapped some how into
the cells that belongs to that library. So that process is achieved or accomplished through a step called technology
mapping
So technology mapping takes the net list And it tries to map the cells out here to the cells available in
the library. And as the output, it generates another net list
which is generated by the logic where the basic cells are those which are available in the
synthesizer it also accepts the library library. So this net list is something which can be
this is a given cell library implemented

So this is the essential process and after completing the

physical design if you find that something is wrong the
circuit is not working according to the specification,
then you may have to redesign and have to go back
and change the original specification.

You lost : cost/ time / manpower/ load

So usually what people do before going for the

actual physical design, so you take the net list
which was obtained by the synthesizer and try
to check whether this net list is working as per
the specifications or not this you do through a
process called logic simulation.
So logic simulation will again take this net list as the input. it will also take a stimulus
which is just a set of inputs. If I have circuit and want to test the circuit for these inputs. So
we apply these inputs and the simulator will tell you what will be the outputs.

I can verify if the outputs are correct or not. So when you are doing logic simulation the
behavior of all the cells of this net list must be known that is available in another library.
This is called the component library. Here all the basic components that can be there in
this net list are present as well as their behavior is also present which helps in carrying out
the logic simulation.

So after simulation we get the performance

and if we see the performance is not according
to our requirement we again to do redesign go
back and change the specs.

Now sometimes even during the physical

design we can do something called back
annotation. Back annotation means form of
very low level design specification we can re
extract possibly the gate level design again. So
we can go back to the logic simulation phase
and again simulate with the same stimulus and
check the performance.
logic simulation process takes as input a logic level net list. Logic level net list means net
list comparison of gates/ comparison of flip flops and it simulates the functional behavior.
we would like to see whether the input output specifications are correct that if you give a
particular input to the circuit what is the expected response or what is the response that
we get

Simulation tool is a software program where the circuit you want to stimulate in terms of
suitable data structure and through a systematic scan of the circuit of the data structure.

Design a Expected outcome

Input ckt by sim

The simulated circuit is a close model of the netlist

Obtained from synthesis
This is an unknown system I can say which on table
Top I have to test
Component library : when you are doing simulation you need the behavior of the
components behavior of the components what does that mean? Suppose if the
components are simple gates like AND, OR, NOT, then what you need is the input output
behavior of the gates. You need either the Boolean function or the truth table in some
form. So you need the behavior of the gate in order to evaluate the output of a gate when
some particular input values are applied to it okay. So behavior of the components is
assumed to be present in the so called component library. Now component library can be
quite exhaustive you can have gates out there. You can have sequential elements like flip
flops and registers you can have slightly more combinational more complex blocks like
multiplexers, adders and other functions and models like decoders

one of the requirements of logic simulation is that it should be possible to handle large
circuits. So when we talk of large circuits in the present day scenario, we are actually
talking about millions of gates okay. So the logic simulation process should be very
efficient it should be able to handle large circuits of the order of millions.

Objectives of simulation:
1. Functional correctness -> test bench
2. Timing analysis
3. Test generations
Test Generation : you have a design and you have done some kind of synthesis on it. So
what we obtained is a net list . But this is not something which you have already
fabricated. This net list is still on your computer . So through simulation you try to verify
whether the net list is working as per the specification . This is done on the design.
But suppose the design process is what you have completed the physical design process
also and now the chips are getting fabricated. Suppose you have fabricated 1000 chips for
your design. Now during fabrication there can be a large number of faults which can
creep in obviously. So once you have manufactured the circuits in terms of the chips you
will have to test each and every chip by applying some input stimulus input test vector
and checking the output. This is the so called manufacture test

Design for manufacturability

Finding out yield
Response model
 Logic synthesis

Outputs:
Inputs:
Logic synthesis Netlist of gates and FF
B expression
Combinational
FSM
Sequential
Design Goal :
Constraint
1. Number of level ( delay)
Target library
2. Number of gates ( area)
3. Low power

Suppose you are trying to design a circuit for a very critical application where delay is
most important to you. You want to design a circuit that will work as fast as possible. So
here if it is combination circuit your designed goal will be to minimize the number of gate
levels. So as you reduce the number of levels

to minimize signal active means as the switching activity in the circuits get reduced the
total power consumption also get reduced. So we want to ensure that the number of
signal transitions that are going on signal transition means 1 to 0, 0 to 1 they are going
on per unit time in the circuit is as less as possible.
 Circuit breakup

if you have a gate with large number of inputs.

You have a AND gate with a large number of inputs. So instead of having 1 AND gate with
a large number of inputs you may be possibly break it up into several smaller AND gates.
But you may argue that if I do this I am increasing the number of levels. So apparently I
am also increasing the delay because the number of gate delays is more. But well this is
not true. ------ Assignment

Technology Mapping

Technology mapping is a process where we have the net list with us. We have a technology
library with us we will have to map our net list from some modules which are available in
the technology library. So the basic concept is that during synthesis we will have to map
portions of the net list to so called cells which are available in the cell library. cells can be
these standard gates NAND, NOR, NOT, AND, OR, invert or depending on the target where
you want to map the design on if it is FPGA.
 This is the standard
Component library

So the idea is simple you have a big net list of gates you try to find out the small sub
circuits from there which matches with some net list available in your technology library.
And if you find a match replace it by the corresponding component of the technology
library. So if you do this what you have is that your entire net list which was there at the
beginning will now get transformed into a net list of cells which have been picked up from
the technology library. Now as I had said there can be overlap among the cells, the
objective is to have minimum number of cells if area is important or to reduce the
number of levels of the cell net list if delay is more important.
A pictorial overview of design flow
What is Simulation
 System State Variable
• System state variables are the collection of all information
needed to define what is happening within the system to a
sufficient level.
• Having defined system state variables, a contrast can be made
between discrete-event models and continuous models based
on the variables needed to track the system state.
• The system state variables in a discrete-event model remain
constant over intervals of time and change value only at
certain well defined points called event times.
• Continuous models have system state variables defined by
differential or difference equations giving rise to variables
that may change continuously over time.
 Entities and Attributes
• An entity represents an object that requires
explicit definition.
• An entity can be dynamic in that it "moves"
through the system, or it can be static in that it
serves other entities.
• Attributes should be considered as local
values.
 Activities and Delays
• An activity is duration of time whose duration is known
prior to commencement of the activity.
• The duration can be a constant, a random value from a
statistical distribution, the result of an equation, input
from a file, or computed based on the event state.
• A delay is an indefinite duration that is caused by some
combination of system conditions.
• When an entity joins a queue for a resource, the time that
it will remain in the queue may be unknown initially since
that time may depend on other events that may occur.
 Phases in Simulation

• A simulation run typically starts in the empty and idle state. The run is therefore
characterized by a "run-in" phase followed by a "steady state" phase, see Figure 1.
The run-in phase is generally ignored and is only used for investigating the effects
of transient conditions such as starting up a new factory or performing radical
changes within an existing facility.
• Typically the steady state phase is of greater interest. At this stage checks must be
made to ensure no long term trends exist, such as continual build up of stock in the
factory, that suggest the model (hence the real system) will be unstable and
unworkable.
 Verification and Validation
• The validation efforts can be grouped into two parts
1. validation of the abstract model itself
2. validation of its implementation
• The first part consists of examining all assumptions,
which transform the real world system into the
conceptual model.
• Testing the validity of an implementation is a more
objective and easier task. It consists of checking the
logic, the flowchart, and the computer program to
ensure that the model has been correctly implemented.
Timing Analysis
Micro-instructions
Scheduling
Classification of EDA