Vlsi5 Bicmos

Brief Outline
Introduction
Advantages of BiCMOS Technology
Evolution of BiCMOS from CMOS
BiCMOS Process Flow
Applications of BiCMOS Technology
Conclusion
References
Introduction
What is BiCMOS?
BiCMOS technology combines Bipolar and CMOS

transistors
onto a single integrated circuit where the advantages of both
canbe utilized.
Advantages of BiCMOS Technology
Improved speed over CMOS
Lower power dissipation than Bipolar
Flexible input/outputs
High performance analog
Latch up immunity
Evolution of BiCMOS from CMOS
BiCMOS technology has evolved from CMOS
processes in order to obtain the highest CMOS
performance possible.
The bipolar processing steps have been added to
the core CMOS flow to realize the desired device
characteristics such as adding masks for bipolar
transistor (BJT) fabrication.
BiCMOS Process Flow
We start up with a lightly-doped P-type wafer and form the buried N+ layer by ion
implantation of antimony. The pattern is etched in a thick oxide covering the
substrate. The structure before the antimony implantation is shown in Figure 1.
Figure 1: Device cross-section of BiCMOS process showing N+ buried

layer implant.
Contd.
A high temperature anneal is performed to remove damage defects and to
diffuse the antimony into the substrate. During this anneal an oxide is grown
in the buried N+ windows. To achieve breakdown between the buried N+
regions a self-aligned punch through implant is performed. Therefore, the
nitride mask is selectively removed and the remaining oxide serves as
blocking mask for the buried P-layer implant (see Fig. 2).
Figure 2: Device cross-section of BiCMOS process showing P buried layer self

aligned implant
Contd.
After removing all oxide a thick epitaxial layer with intrinsic doping is grown
on top (see Fig. 3).
Figure 3: Device cross-section of BiCMOS process after growth of the EPI-

layer.
Contd.
After that a twin well process is used to fabricate the N-well of the PMOS and
the collector of the NPN device. Again, the wafer is capped with a nitride layer
which is opened at the N+ regions.
Figure 5.2-4: Device cross-section of BiCMOS process showing EPI-layer

and masking for N-well implant.
Contd.
After implanting the N-type dopant a thick oxide is grown and the nitride is
stripped from the P+ regions. The subsequent P-well implant is self-aligned to the
well edge (see Fig. 5).
Figure 5: Device cross-section of BiCMOS process showing self-aligned P-

well implant.
Contd.
After the wells are fabricated the whole wafer is planarized and a pad oxide is
grown. The oxide is capped with a thick nitride. After patterning the active regions
of the device, an etch step is used to open up the field isolation regions. Prior to
field oxidation, a blanket channel stop is implanted (see Fig. 6).
Figure 6: Device cross-section of BiCMOS process showing channel stop

implant.
Contd.
Oxidation is used to fabricate a thick field oxide. After removal of the nitride
masks from the active regions, phosphorus is implanted into the N-well of the
collector region to implant the deep N+ subcollector (see Fig. 7). The PMOS and
NMOS devices are protected by the photoresist.
Figure 7: Device cross-section of BiCMOS process showing deep N+

subcollector implant.
Contd.
For the fabrication of the intrinsic base for the bipolar device, the base region is
opened and the base implant is performed. To ensure low base-emitter
capacitance a thicker gate oxide is deposited after the base implant. The deposited
oxide has to be removed from the non base regions by an etch step. The structure
after the intrinsic base implant and prior to the base oxide deposition is shown in
Figure 8
Figure 8: Device cross-section of BiCMOS process showing the intrinsic

base implant.
Contd.
We proceed with the resist strip and perform a pre-gate oxide etch to clean the
oxide surface. The active emitter window is patterned and opened up with an
etching process until the whole gate oxide is removed in the emitter region. Then a
polysilicon layer is deposited, which forms the emitter contact as well as the gate
polysilicon layers. This polysilicon layer is implanted with arsenic which will diffuse
out from the polysilicon layer at the final source-drain anneal to form the emitter
junction (see Fig. 9). Arsenic
Figure 9: Device cross-section of BiCMOS process showing the fabrication of the

polysilicon emitter.
Contd.
The polysilicon layer is patterned to define the CMOS gates and the bipolar
emitter. After emitter formation, all subsequent process steps are well known from
CMOS technology. Phosphorus is implanted to form a shallow lightly doped
drain(LDD) region for the NMOS device (see Fig 10). The subcollector is opened to
collect additional N-type doping.
Figure 10: Device cross-section of BiCMOS process before the NMOS LDD
doping is implanted.
Contd.
Then the sidewall spacer formation is initiated. Therefore, an oxide layer is
deposited and anisotropically etched back. Next, the NMOS source-drain regions
are heavily doped by phosphorus, which is depicted in Figure 11
Phosphorus
Figure 11: Device cross-section of BiCMOS process showing the source-drain

implantation of the NMOS device.
Contd.
Next, the PMOS source-drain regions are heavily doped by Boron, which is
depicted in Figure 12. The P+ source-drain implant is also used for the extrinsic
base fabrication (see Figure 12).
Figure 12: Device cross-section of BiCMOS process showing the PMOS source-
drain implantation.
Contd.
Finally, the fabrication of the active regions is finished by the source-drain
anneal, which is optimized for outdiffusion conditions of the bipolar device. The
final device structure including the active area doping is shown in Figure 13.
Afterwards the structure is scheduled for a double-level interconnect process.
Figure 13: Device cross-section of BiCMOS process after fabrication of the active
areas.
Applications of BiCMOS Technology
BiCMOS has been widely used in many applications like

 Static Random Access Memory(SRAM) circuits
 Wireless Communication equipments like Transceivers,
Amplifiers, Oscillators etc
 System-on-Chip Technology
 Personal Internet Access Devices
 Set-top boxes
 And many mixed signal applications
Conclusion
Silicon technology evolution continues at rapid pace
CMOS development is rapidly reaching its limits
BiCMOS likely to emerge as preferred technology
platform for mixed signal applications

Vlsi5 Bicmos

Uploaded by

Copyright:

Available Formats

Vlsi5 Bicmos

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Vlsi5 Bicmos

Uploaded by

Copyright:

Available Formats

Brief Outline

BiCMOS technology combines Bipolar and CMOS

Figure 1: Device cross-section of BiCMOS process showing N+ buried

Figure 2: Device cross-section of BiCMOS process showing P buried layer self

Figure 3: Device cross-section of BiCMOS process after growth of the EPI-

Figure 5.2-4: Device cross-section of BiCMOS process showing EPI-layer

Figure 5: Device cross-section of BiCMOS process showing self-aligned P-

Figure 6: Device cross-section of BiCMOS process showing channel stop

Figure 7: Device cross-section of BiCMOS process showing deep N+

Figure 8: Device cross-section of BiCMOS process showing the intrinsic

Figure 9: Device cross-section of BiCMOS process showing the fabrication of the

Figure 11: Device cross-section of BiCMOS process showing the source-drain

BiCMOS has been widely used in many applications like

You might also like