ECE 545

Lecture 2 – Part 2

Data Flow
Modeling of
Combinational Logic

ECE 545 – Introduction to VHDL George Mason University

 Resources

• Volnei A. Pedroni, Circuit Design with VHDL

Chapter 5, Concurrent Code
Chapter 4.1, Operators

• Sundar Rajan, Essential VHDL: RTL Synthesis

Done Right
Chapter 3, Gates, Decoders and Encoders
(see errata at http://www.vahana.com/bugs.htm)

ECE 545 – Introduction to VHDL 2

Register Transfer Level (RTL) Design Description

Today’s Topic

Combinational
Logic
Combinational …
Logic

Registers

ECE 545 – Introduction to VHDL 3

 Describing
Combinational Logic
Using
Dataflow Design Style

ECE 545 – Introduction to VHDL 4

VHDL Design Styles

VHDL Design
Styles

dataflow structural behavioral

Concurrent Components and Sequential statements

statements interconnects • Registers
• State machines
• Test benches

ECE 545 – Introduction to VHDL 5

 Data-flow VHDL

Major instructions

Concurrent statements
• concurrent signal assignment ()
• conditional concurrent signal assignment
(when-else)
• selected concurrent signal assignment
(with-select-when)
• generate scheme for equations
(for-generate)

ECE 545 – Introduction to VHDL 6

 Data-flow VHDL

Major instructions

Concurrent statements
• concurrent signal assignment ()
• conditional concurrent signal assignment
(when-else)
• selected concurrent signal assignment
(with-select-when)
• generate scheme for equations
(for-generate)

ECE 545 – Introduction to VHDL 7

 Data-flow VHDL: Example
xiyi
ci 00 01 11 10

0 1 1
ci xi yi ci + 1 si
1 1 1
0 0 0 0 0
0 0 1 0 1
s i = x i  y i  c i
0 1 0 0 1
0 1 1 1 0 xiyi
1 0 0 0 1
ci 00 01 11 10
1 0 1 1 0
1 1 0 1 0 0 1
1 1 1 1 1
1 1 1 1

(a) Truth table

ci + 1 = xi yi + xici + yi ci

(b) Karnaugh maps

xi

yi si

ci

ci + 1

(c) Circuit
ECE 545 – Introduction to VHDL 8
 Data-flow VHDL: Example (1)

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY fulladd IS
PORT ( x : IN STD_LOGIC ;
y : IN STD_LOGIC ;
cin : IN STD_LOGIC ;
s : OUT STD_LOGIC ;
cout : OUT STD_LOGIC ) ;
END fulladd ;

ECE 545 – Introduction to VHDL 9

 Data-flow VHDL: Example (2)

ARCHITECTURE fulladd_dataflow OF fulladd IS

BEGIN
s <= x XOR y XOR cin ;
cout <= (x AND y) OR (cin AND x) OR (cin AND y) ;
END fulladd_dataflow ;

ECE 545 – Introduction to VHDL 10

Logic Operators

• Logic operators
and or nand nor xor not xnor

• Logic operators precedence

only in VHDL-93
Highest
not
and or nand nor xor xnor
Lowest

ECE 545 – Introduction to VHDL 11

No Implied Precedence
Wanted: y = ab + cd
Incorrect
y <= a and b or c and d ;
equivalent to
y <= ((a and b) or c) and d ;
equivalent to
y = (ab + c)d

Correct
y <= (a and b) or (c and d) ;

ECE 545 – Introduction to VHDL 12

Concatenation
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c, d, e, f: STD_LOGIC_VECTOR(7 DOWNTO 0);

a <= ”0000”;
b <= ”1111”;
c <= a & b; -- c = ”00001111”

d <= ‘0’ & ”0001111”; -- d <= ”00001111”

e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ &
‘1’ & ‘1’; -- e <= ”00001111”
f <= (‘0’,‘0’,‘0’,‘0’,‘1’,‘1’,‘1’,‘1’) ;
-- f <= ”00001111”

ECE 545 – Introduction to VHDL 13

Rotations in VHDL

a<<<1

a(3) a(2) a(1) a(0)

a(2) a(1) a(0) a(3)

a_rotL <= a(2 downto 0) & a(3)

ECE 545 – Introduction to VHDL 14

Arithmetic Operators in VHDL (1)
To use basic arithmetic operations involving
std_logic_vectors you need to include the
following library packages:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
or
USE ieee.std_logic_signed.all;

ECE 545 – Introduction to VHDL 15

Arithmetic Operators in VHDL (2)
You can use standard +, - operators
to perform addition and subtraction:

signal A : STD_LOGIC_VECTOR(3 downto 0);

signal B : STD_LOGIC_VECTOR(3 downto 0);
signal C : STD_LOGIC_VECTOR(3 downto 0);
……
C <= A + B;

ECE 545 – Introduction to VHDL 16

 Data-flow VHDL

Major instructions

Concurrent statements
• concurrent signal assignment ()
• conditional concurrent signal assignment
(when-else)
• selected concurrent signal assignment
(with-select-when)
• generate scheme for equations
(for-generate)

ECE 545 – Introduction to VHDL 17

 Conditional concurrent signal assignment

When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;

0
Value N
1
.… … 0
alue N-1 0
1 Target Signal
1
Value 2
Value 1
Condition N-1

Condition 2
Condition 1

ECE 545 – Introduction to VHDL 18

Operators

• Relational operators
= /= < <= > >=

• Logic and relational operators precedence

Highest not
= /= < <= > >=
Lowest and or nand nor xor xnor

ECE 545 – Introduction to VHDL 19

Priority of logic and relational operators

compare a = bc
Incorrect
… when a = b and c else …
equivalent to
… when (a = b) and c else …

Correct
… when a = (b and c) else …

ECE 545 – Introduction to VHDL 20

 Tri-state Buffer – example (1)

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY tri_state IS
PORT ( ena: IN STD_LOGIC;
input: IN STD_LOGIC_VECTOR(7 downto 0);
output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END tri_state;

ECE 545 – Introduction to VHDL 21

 Tri-state Buffer – example (2)

ARCHITECTURE tri_state_dataflow OF tri_state IS

BEGIN
output <= input WHEN (ena = ‘0’) ELSE
(OTHERS => ‘Z’);
END tri_state_dataflow;

ECE 545 – Introduction to VHDL 22

 Data-flow VHDL

Major instructions

Concurrent statements
• concurrent signal assignment ()
• conditional concurrent signal assignment
(when-else)
• selected concurrent signal assignment
(with-select-when)
• generate scheme for equations
(for-generate)

ECE 545 – Introduction to VHDL 23

Selected concurrent signal assignment

With –Select-When
with choice_expression select
target_signal <= expression1 when choices_1,
expression2 when choices_2,
. . .
expressionN when choices_N;

expression1 choices_1
expression2 choices_2
target_signal

expressionN choices_N

choice expression

ECE 545 – Introduction to VHDL 24

Allowed formats of choices_k

WHEN value

WHEN value_1 to value_2

WHEN value_1 | value_2 | .... | value N

ECE 545 – Introduction to VHDL 25

Allowed formats of choice_k - example

WITH sel SELECT

y <= a WHEN "000",
b WHEN "011" to "110",
c WHEN "001" | "111",
d WHEN OTHERS;

ECE 545 – Introduction to VHDL 26