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REAL TIME EMBEDDED SYSTEM - Lec5

The document provides an overview of 8086-based real-time embedded systems. It discusses the 8086 architecture including its pipeline, bus architecture, memory organization and addressing schemes. It also covers interrupts in 8086 systems including hardware interrupts, the interrupt controller 8259, and the interrupt handling sequence. Examples of interrupt request handling with nested and simultaneous interrupts are also presented.

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71 views17 pages

REAL TIME EMBEDDED SYSTEM - Lec5

The document provides an overview of 8086-based real-time embedded systems. It discusses the 8086 architecture including its pipeline, bus architecture, memory organization and addressing schemes. It also covers interrupts in 8086 systems including hardware interrupts, the interrupt controller 8259, and the interrupt handling sequence. Examples of interrupt request handling with nested and simultaneous interrupts are also presented.

Uploaded by

parthasarothi_sikder79
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Real-time Embedded Systems- Lecture 05

Real-time Embedded Systems


Lecture 5
Understanding targets-
8086 based systems
Prof. Dr. Amitava Gupta

Department of Power Engineering

Jadavpur University, India


Real-time Embedded Systems- Lecture 05

What have we learnt?

Application
+
Operating System

Interface with application

Hardware
Embedded System?
Real-time Embedded Systems- Lecture 05

We start with a survey of 8086 based systems

Instruction Address
AH AL queue Data
BH BL 20
CH CL
DH DL

Control
Logic SP Control
BP 16
CS
SI
SS
ALU DI DS
IP ES

PSW
Real-time Embedded Systems- Lecture 05

Pipelined Architecture

The fetching and execution activities overlap. Instructions are


pre-fetched and kept in instructions queue.

While one instruction is being executed, the next one is fetched.


This is because of the fact that fetch and execution units are separate.

When processors have more than one execution unit, they are said to
have a superscalar architecture. The Pentium is an example of such
processors.
Real-time Embedded Systems- Lecture 05

Bus Organized Computers

A set of conductors used for communicating information between the components


of a computer is called a bus.

External bus- connects two major components e.g. CPU and memory.This
is the system bus.

Internal bus- connects two minor components within a major component


e.g. set of working registers and the control unit.

Components which control the Bus are called bus masters, e.g. CPU,DMA
controller etc.
Real-time Embedded Systems- Lecture 05

System Bus Timing contd..

T1 T2 T3 Tw T4 T4 Ti Ti

Bus Cycle: Activity involved in transferring a byte or word over system bus
is called bus cycle. The execution of an instruction may require more
than one bus cycle.

The timing of signals within the CPU and bus control logic is controlled by
a clock. The bus cycles and CPU activity are controlled by groups of clock pulses.

The exact number of clock pulses or cycles within a bus cycle varies
Real-time Embedded Systems- Lecture 05

Read timing for 8086 without wait states

T1 T2 T3 T4 Tw

Address out Data in

ALE

RD

Device sends a Ready signal here


else wait states are introduced between
T3 and T4
Real-time Embedded Systems- Lecture 05

Physical memory organization

512 KB each
Selectable by
bit A0
o + e
OA = EA + 1
So, for an even address
the next odd address can
be obtained by using
A0 = 1 keeping all other
bits same
Address D15-D8 D7-D0
+1
Address
Real-time Embedded Systems- Lecture 05

Basic addressing scheme uses two 16 bit registers to


compute a 20 bit address

The memory is ‘logically’ organized into segments

64K

1M 16 bit segment register 4 Bits


base
16 bit pointer register
offset
Real-time Embedded Systems- Lecture 06

Excercise

If the physical address is 5A230 when [CS] = 5200,


what will it be [CS] becomes 7800?

Solution:
Real-time Embedded Systems- Lecture 05

Interrupts (Hardware Interrupts)

Each interrupt is associated with an Interrupt Service Routine (ISR) that is executed when an
interrupt occurs

Interrupt table
00000
IP type 0
CS type 0 00002
00004
Real-time Embedded Systems- Lecture 05

Interfacing External Interrupts

INTR

CPU PIC
8259

INTA

T1 T2 T3 T4 T4

ALE

INTA

AD7-AD0
Real-time Embedded Systems- Lecture 05

Interrupt Sequence

•Establishing the type N

•Pushing the contents of PSW, CS


and IP into the stack

•Clearing the IF and TF flags

•Loading content of 4*N into IP


and 4*N + 2 into CS
Real-time Embedded Systems- Lecture 05

INT I 0
0
In Service Register Priority Resolver IRR & ML 11
Pending

ICW 1(Chip Control)


OCW 1(IMR) 0 0
ICW 2(Type)
OCW 2 7
ICW 3(Slave Control)
OCW 3
ICW 4(Mode Control)

INTA
Real-time Embedded Systems- Lecture 05

ICW1- Chip Control

1 LTIM ADI SNGL IC 4

ICW4- Mode Control

0 0 0 SFNM BUF M/S AEOI µPM


Real-time Embedded Systems- Lecture 05

OCW2

R SL EOI 0 0 L2 L1 L0

OCW3

0 ESMM SMM 0 1 P RR RIS


Real-time Embedded Systems- Lecture 05

Requests arrive simultaneously on IRQ2 and IRQ4,


& while IR2 routine is being executed, IRQ1 arrives!
D1 in ISR set IR1
----------- D1 in ISR reset
Reset IF
IRQ2 D2 in ISR set (STI)
Main IR2 .
Program ----------- .
Reset IF .
IRQ4
(STI) IRET
IRQ1 .
. D2 in ISR reset
.
IRET
IR4
-----------
Reset IF
(STI)
.
D4 in ISR set .
.
IRET

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