Computer System: Operating Systems: Internals and Design Principles
Computer System: Operating Systems: Internals and Design Principles
Systems:
Internals Chapter 1
and Design
Principles Computer System
Overview
Seventh Edition
By William Stallings
Operating Systems:
Internals and Design Principles
Herbert Simon
Operating System
Exploits
the hardware resources of one or more
processors
Provides a set of services to system users
Manages secondary memory and I/O devices
Basic Elements
Referred to as the
Central Processing
Unit (CPU)
Main Memory
Volatile
Providesfor communication
among processors, main
memory, and I/O modules
Top-Level
View
Microprocessor
Inventionthat brought about desktop and
handheld computing
Processor on a single chip
Fastest general purpose processor
Multiprocessors
G P U
Digital Signal Processors
(DSPs)
Deal with streaming signals such as audio
or video
Used to be embedded in devices like
modems
Encoding/decoding speech and video
(codecs)
Support for encryption and security
D S P
System on a Chip
(SoC)
To satisfy the requirements of handheld
devices, the microprocessor is giving way
to the SoC
Componentssuch as DSPs, GPUs, codecs
and main memory, in addition to the
CPUs and caches, are on the same
chip
Instruction Execution
A program consists of a set of instructions
stored in memory
Two steps:
●
processor reads (fetches) instructions from memory
●
processor executes each instruction
Basic Instruction Cycle
Instruction Fetch
and Execute
The
processor fetches the instruction from
memory
Program counter (PC) holds address of the
instruction to be fetched next
PC is incremented after each fetch
Instruction Register (IR)
Fetched instruction is
Processor interprets the
loaded into Instruction instruction and performs
Register (IR) required action:
Processor-memory
Processor-I/O
Data processing
Control
Characteristics of a
Hypothetical Machine
Example of
Program
Execution
Interrupts
Interrupt the normal sequencing of the processor
Provided to improve processor utilization
most I/O devices are slower than the processor
processor must pause to wait for device
wasteful use of the processor
Common Classes
of Interrupts
Flow of Control
Without Interrupts
Interrupts:
Short I/O Wait
Transfer of Control via Interrupts
Instruction Cycle With Interrupts
Program Timing:
Short I/O Wait
Program Timing:
Long I/O wait
Simple
Interrupt
Processing
Changes
for an
Interrupt
Multiple Interrupts
An interrupt occurs
while another interrupt
Two
is being processed approaches:
e.g. receiving data from
● ●
disable interrupts while
a communications line an interrupt is being
and printing results at processed
the same time ●
use a priority scheme
Transfer of Control With
Multiple Interrupts:
Sequential
Transfer of Control With
Multiple Interrupts:
Nested
Example Time Sequence
of Multiple Interrupts
Memory Hierarchy
Cache of cache
levels
Design
write cache
policy size
replacem
block
ent
algorithm size
mapping
function
Cache and Block Size
Cache Size
●
can occur every time the block is updated
●
can occur when the block is replaced
●
minimizes write operations
●
leaves main memory in an obsolete state
I/O Techniques
∗ When the processor encounters an instruction relating to
I/O, it executes that instruction by issuing a command to the
appropriate I/O module
Availability
the failure of a single
processor does not
halt the machine
SMP Organization
external
memory communications
o n to the ch ip
with th e memo ry co ntro ller o n th e
to other
ch ip th echips:
Fro n t Sid e Bu s is
elimin ated
Quick
Path
Interco
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(QPI)
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Intel
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