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4.add & Shift Sequential Multiplier Architecture With 8-Bit Operands or Beyonds

This document describes an architecture for a sequential multiplier using an add-and-shift algorithm. It includes: 1) A generic N-bit register entity that can load, shift, and clear its contents. 2) A generic N-bit adder that performs additions. 3) A controller entity that directs the multiplier algorithm by controlling loading, shifting, and adding operations over N clock cycles based on the bits of the multiplier. 4) A testbench that multiplies pairs of 4-bit numbers and checks the product.

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tinku kumar
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100 views12 pages

4.add & Shift Sequential Multiplier Architecture With 8-Bit Operands or Beyonds

This document describes an architecture for a sequential multiplier using an add-and-shift algorithm. It includes: 1) A generic N-bit register entity that can load, shift, and clear its contents. 2) A generic N-bit adder that performs additions. 3) A controller entity that directs the multiplier algorithm by controlling loading, shifting, and adding operations over N clock cycles based on the bits of the multiplier. 4) A testbench that multiplies pairs of 4-bit numbers and checks the product.

Uploaded by

tinku kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Add & Shift sequential multiplier architecture with 8-bit operands

or beyonds

By TINKU KUMAR, IIT PATNA


System Example: 8x8 multiplier:
Multiply Algorithm:
Generic N-bit shift/load register entity:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RegN is
generic (N: integer := 4);
port ( Din: in std_logic_vector(N-1 downto 0); --N-bit input
Dout: out std_logic_vector(N-1 downto 0); --N-bit output
Clk: in std_logic; --Clock (rising edge)
Load: in std_logic; --Load enable
Shift: in std_logic; --Shift enable
Clear: in std_logic; --Clear enable
SerIn: in std_logic --Serial input
);
end RegN
Generic N-bit register architecture:
architecture Behavioral of RegN is
signal Dinternal: std_logic_vector(N-1 downto 0); -- Internal state
begin
process (Clk)
begin
if (rising_edge(Clk)) then
if (Clear = '1') then
Dinternal <= (others => '0'); -- Clear
elsif (Load = '1') then
Dinternal <= Din; -- Load
elsif (Shift = '1') then
Dinternal <= SerIn & Dinternal(N-1 downto 1); -- Shift
end if;
end if;
end process;
Dout <= Dinternal; -- Drive outputs**
end Behavioral
N-bit adder (behavioral):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity AdderN is
generic (N: integer := 4);
port( A: in std_logic_vector(N-1 downto 0); -- N bit Addend
B: in std_logic_vector(N-1 downto 0); -- N bit Augend
S: out std_logic_vector(N downto 0) -- N+1 bit result, includes carry
);
end AdderN;
architecture Behavioral of AdderN is
begin
S <= std_logic_vector(('0' & UNSIGNED(A)) + UNSIGNED(B));
end Behavioral;
Multiplier Controller:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Controller is
generic (N: integer := 2); -- # of counter bits
port ( Clk: in std_logic; -- Clock (use rising edge)
Q0: in std_logic; -- LSB of multiplier
Start: in std_logic; -- Algorithm start pulse
Load: out std_logic; -- Load M,Q and Clear A
Shift: out std_logic; -- Shift A:Q
AddA: out std_logic; -- Load Adder output to A
Done: out std_logic -- Indicate end of algorithm
);
end Controller;
Multiplier Controller – Architecture:

Multiplier Controller - Architecture

architecture Behavioral of Controller is


type states is (HaltS,InitS,QtempS,AddS,ShiftS);
signal state: states := HaltS;
signal CNT: unsigned(N-1 downto 0);
begin
-- Moore model outputs to control the datapath
Done <= '1' when state = HaltS else '0'; -- End of algorithm
Load <= '1' when state = InitS else '0'; -- Load M/Q, Clear A
AddA <= '1' when state = AddS else '0'; -- Load adder to A
Shift <= '1' when state = ShiftS else '0'; -- Shift A:Q
process(clk)
begin
Controller – State transition process :
if rising_edge(Clk) then
case state is
when HaltS => if Start = '1' then -- Start pulse applied?
state <= InitS; -- Start the algorithm
end if;
when InitS => state <= QtempS; -- Test Q0 at next clock**
when QtempS => if (Q0 = '1') then
state <= AddS; -- Add if multiplier bit = 1
else
state <= ShiftS; -- Skip add if multiplier bit = 0
end if;
when AddS => state <= ShiftS; -- Shift after add
when ShiftS => if (CNT = 2**N - 1) then
state <= HaltS; -- Halt after 2^N iterations
else
state <= QtempS; -- Next iteration of algorithm: test Q0 **
end if;
end case;
end if;
end process;
Controller – Iteration counter:

process(Clk)
begin
if rising_edge(Clk) then
if state = InitS then
CNT <= to_unsigned(0,N); -- Reset CNT in InitS
state
elsif state = ShiftS then
CNT <= CNT + 1; -- Count in ShiftS state
end if;
end if;
end process;
Multiplier test bench (main process):
Clk <= not Clk after 10 ns; -- 20ns period clock
process
begin
for i in 15 downto 0 loop -- 16 multiplier values
Multiplier <= std_logic_vector(to_unsigned(i,4));
for j in 15 downto 0 loop -- 16 multiplicand values
Multiplicand <= std_logic_vector(to_unsigned(j,4));
Start <= '0', '1' after 5 ns, '0' after 40 ns; -- 40 ns Start pulse
wait for 50 ns;
wait until Done = '1'; --Wait for completion of algorithm
assert (to_integer(UNSIGNED(Product)) = (i * j)) – Check Product
report "Incorrect product“ severity NOTE;
wait for 50 ns;
end loop;
end loop;
end process;
Simulation results:

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