Chapter4: Combinational Logic

Lecture2- Design 4-bit Ripple Carry Binary Adder-Subtractor Circuit

Engr. Arshad Nazir, Asst Prof

Dept of Electrical Engineering
Fall 2021 SEECS 1
 Objectives
• Study Half and Full Adders
• Design 4-Bit Ripple Carry Binary Adder-subtractor design using
Full-Adders

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 Binary Adder-Subtractor
• Digital computers perform various arithmetic operations
• The most basic arithmetic operation is the addition of two binary
digits
• When both augend and addend bits to be added are equal to 1, the
binary sum consists of two digits (1+1=10). The higher significant bit of
this result is called a carry. This carry is added to the next higher order
pair of significant bits.
• A combinational circuit that performs the addition of two bits and
produces SUM and Carry is called a half adder (HA).

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 Half Adder
• Half adder adds two binary bits and produces SUM and Carry so it
requires two inputs and two outputs
• 0+0=0 ; 0+1=1 ; 1+0=1 ; 1+1=10
• The input variables designate the augend and addend bit, the output
variables produce the sum (S) and carry (C)
• The truth table for half adder is shown. The C output is 1 only when
both inputs are 1. The S output represents the least significant bit of
the sum

x y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

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 Half Adder Output Expressions
• The simplified sum of products expressions are:
S = x'y+xy'
C = xy
• It can be implemented in sum of products. It can also be implemented
with an exclusive-OR and an AND gate
S=xy= (x+y)(x'+y')
S' = xy+x'y'= C+ x'y'
S = (C+x'y')'
C = xy= (x'+y')'

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 Full Adder
• A Full-Adder (FA) is a combinational circuit that forms the arithmetic
sum of three bits (three input bits).
Two of the input variables x, y represents the two significant bits
to be added
The third input z represents the carry bit from the previous lower
significant position
Two output bits are necessary designated by the symbol S for sum
and C for carry
• When all input bits are 0, the output is 0 x y z c s
0 0 0 0 0
• The S output is equal to 1 when only one 0 0 1 0 1
input is equal to 1 or when all three inputs 0 1 0 0 1
are equal to 1 0 1 1 1 0
• The C output has a carry of 1 if two or 1 0 0 0 1
1 0 1 1 0
three inputs are equal to 1 1 1 0 1 0
1 1 1 1 1

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 C

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 Simplified Output Expressions for
Full Adder
• The simplified expressions for full adder are
• S = x' y' z + x' y z' + x y' z' + x y z
• C = xy + xz + yz

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 Full Adder with Two Half Adders
• Full adder can also be implemented with two half adders and an OR gate. The S
output from the second half adder is the exclusive-OR of z and the output of
the first half adder giving
• S = z Å (x Å y)
= z'(xy'+x'y)+z(xy'+x'y)'
=z'(xy'+x'y)+z(xy+x'y')
= xy'z'+x'yz'+xyz+x'y'z
• C = z(xy'+x'y)+xy
= xy'z+x'yz+ xy

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 4-Bit Binary Adder
• A binary adder is a digital circuit that produces the arithmetic sum of
two binary numbers.
• A binary adder can be implemented using multiple full adders (FA)
connected in cascade with the output carry from each full adder to
the input carry of the next full adder in the chain

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 4-Bit Binary Adder
• The augend bits of A and the addend bits of B are designated by
subscript numbers from right to left, with subscript 0 denoting the
least significant bit
• The carries are connected in a chain through the full adders
• The S outputs generate the required sum bits

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 4-Bit Binary Adder
• Consider the two binary numbers, A= 1011 and B= 0011
• Their sum S= 1110 is formed with four-bit adders
• The bits are added with full adders, starting from the least significant position (subscript 0),
to form the sum bit and carry bit
• The input carry C0 in the least significant position must be 0
• The value of Ci+1 in any position is the output carry of the that full adder stage and it is
transferred into the input carry of the full adder that adds the bits one higher
significant position higher.
Subscript i 3 2 1 0
• The sum bits are thus generated starting from the
Input carry 0 1 1 0 Ci
rightmost position and are available as soon as the Augend 1 0 1 1 Ai
corresponding previous carry bit is generated. Addend 0 0 1 1 Bi
Sum 1 1 1 0
• All the carries must be generated for the correct sum Si
Output carry 0 0 1 1 Ci+1
bits to appear at the outputs

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 Carry Propagation
• The addition of two binary numbers in parallel implies that all the bits
of the augend and addend are available for computation at the same
time
• In any combinational circuit, the signal must propagate through the
gates before the correct output is available in the output terminals.
• The Total propagation time = propagation delay of a typical gate X the
number of gate levels
• The longest propagation delay time in a binary adder is the time it
takes the carry to propagate through the full adders.
• This is because each bit of the sum output depends on the value of
the input carry. This makes the binary adder very slow.

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 Carry Propagation
• Since each bit of the sum output depends on the value of input carry,
the value of Si in any given stage in the adder will be in its steady state
final value only after the input carry to the stage has been propagated
• Consider output S3 in Figure 4-9. Inputs A3 and B3 are available as soon
as input signals are applied to the adder, however input carry C3
doesn’t settle to its final value until C2 is available from the previous
stage
• Similarly, C2 has to wait for C1 and so on down to C0
• In this way only after the carry propagates and ripples through all
stages will the last output S3 and carry C4 settle to their final correct
value

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 Carry Propagation
• The number of gate levels for the carry propagation can be found
from the circuit of the full adder
• The input and output variables use the subscript i to denote a typical
stage in the adder
• The signals at Pi and Gi settle to their steady state values after they
propagate through their respective gates

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 Carry Propagation
• These two signals are common to all full adders and depend only on
the augend and addend bits
• The signal from the input carry Ci to the output carry Ci+1 propagates
through an AND gate and an OR gate, which constitutes two gate
levels
• If there are four full adders in the adder, the output carry C4 would
have 2 x 4 = 8 gate levels from C0 to C4.
• For an n-bit adder, there are 2n gate levels for the carry to propagate
from input to output
• The outputs of a combinational circuit will not be correct unless the
signals are given enough time to propagate through the gates
connected from inputs to outputs
• All other arithmetic operations are implemented by successive
additions, the time consumed during the addition process is very
critical.

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 Carry Propagation
• One choice to reduce the carry propagation delay is to employ faster
gates but the most widely used technique for reducing the carry
propagation time in parallel adder is principle of carry lookahead
• Consider the circuit of full adder shown in fig 4-10
• If we define two binary variables
carry propagate: Pi = AiBi (Term associated with the propagation
of carry from Ci to Ci+1)
carry generate: Gi = AiBi (Produces 1 when both Ai and Bi are 1)
• Output sum and carry can be expressed as
sum: Si = PiCi
carry: Ci+1 = Gi+PiCi

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 Carry Propagation
• We now write the Boolean functions for the carry outputs of each
stage and substitute for each Ci, its value from the previous equation
Co= input carry
C1 = G0+P0C0
C2 = G1+P1C1
= G1+P1(G0+P0C0)
= G1+P1G0+P1P0C0
C3 = G2+P2C2
= G2+P2G1+P2P1G0+ P2P1P0C0
C4 = G3+P3C3
=G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0C0
• Since the Boolean function for each output carry is expressed in sum of
products, each function can be implemented with one level of AND
gates followed by an OR gate (or by two-level NAND)

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 Carry Look ahead Generator
• The four Boolean functions for C1, C2, C3 ,and C4 are implemented in
the carry look ahead generator shown in Figure 4-11
• Here C4 doesn’t have to wait for C3, C2 and C1 to propagate and C4 is
propagated at the same time as C1, C2, and C3.

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Carry Look ahead Generator

Fig 4-11 Logic Diagram of Carry Look ahead Generator

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4-Bit Adder with Carry Look ahead
• The construction of 4-bit adder with a carry lookahead generator is
shown in Figure 4-12
• Each sum output requires two exclusive-OR gates.
• The output of first exclusive-OR gate generates the Pi variable and the
AND gate generates the Gi variable
• The carries are propagated through the carry look ahead generator
and applied as inputs to the second exclusive-OR gate
• All outputs carries are generated after a delay through two levels of
gates
• Outputs S1 through S3 have equal propagation delay times

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4-Bit Adder with Carry Look
ahead

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 Binary Subtractor
• The subtraction of unsigned binary numbers can be easily done
by means of complements.(section 1-5)
• A-B = A+(2’s complement of B)
• The 2’s complement can be obtained by taking the 1’s
complement and adding 1 to least significant pair of bits
• To obtain 2’s complement, the 1’s complement can be
implemented with inverters and one can be added to the sum
through the input carry

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 Binary Subtractor
• The circuit for subtracting A – B consists of an adder with inverters
placed between each data input B and the corresponding input of
full adder
• The input carry C0 must be equal to 1 when performing subtraction
• The operation thus performed becomes A plus the 1’s complement
of B plus 1 (A+1’s complement of B+1). This is equal to A plus 2’s
complement of B (A+2’s complement of B)
• For unsigned numbers this gives A – B if A ≥ B or the 2’s complement
of (B – A) if A<B

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 Binary Subtractor
• The addition and subtraction operation can be combined into one circuit
with one common binary adder
• This is done by including an exclusive-OR gate with each full adder
• The mode input M controls the operation. When M=0, we have B0= B.
The full adder receives the value of B, the input carry is 0 and the circuit
performs A+B
• When M=1, we have B1= B’. The full adder receives the value of B’, the
input carry C0 is 1 and the circuit performs A plus the 2’s complement of
B. (A+1’s complement of B+1).
• The exclusive-OR with output V is for detecting an overflow (detail later,
in overflow)

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The End

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