KNR 1063 Digital Electronics: Counters
KNR 1063 Digital Electronics: Counters
KNR 1063 Digital Electronics: Counters
DIGITAL ELECTRONICS
Counters
Mod number = 2N
K ~Q K ~Q K ~Q K ~Q
K ~Q K ~Q K ~Q K ~Q
Number of FFs
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Cont…
A flip-flop must change states at each NGT. For this reason, its J & K inputs are permanently
HIGH (J=K=1)
B flip-flop must change states on each NGT that occurs while A=1. This operation is
accomplished by connecting output A to the J & K input of B, so that J=K=1 only when A=1
C flip-flop must change states on each NGT that occurs while A=B=1. This operation is
accomplished by connecting the logic signal AB to FF C’s J & K input, this FF will toggle only
when A=B=1
D flip-flop must change states on each NGT that occurs while A=B=C=1. This operation is
accomplished by connecting the logic signal ABC to FF D’s J & K input, this FF will toggle only
when A=B=C=1
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Circuit operation
• Count value increments on each
negative edge
• Note that low-order bit (A)
toggles on each clock cycle
• The basic principle for
constructing synchronous
counter:
– Each FF should have its J
and K inputs connected so
that they are HIGH only
when the outputs of all
lower-order FFs are in the
HIGH state
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Advantage of synchronous counter over
asynchronous
• Total delay is the same no matter how many FFs are
in the counter and it will generally be much lower
than with an asynchronous counter with the same
number of FFs
total delay = FF tpd + AND gate tpd
• Synchronous counter can operate at much higher
input frequency
• Circuitry of synchronous counter is more complex
• Basic idea:
– J-K excitation table
Example:
Design a three-bit synchronous counter
the count 000 to 100 and the sequence
does not include the 101, 110, and 111
states.
JA C
KA 1
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Cont…
(a) K maps for the JC and KC logic circuits; (b) K maps for the JB and KB logic circuits.