MICROCOMPUTER AND

MICROCONTROLLER

• Multichip and • Single chip system.

multiboard system. • Fixed programmed.
• User programmed.
• Programs are stored
• Programs are stored
in nonvolatile
in volatile as well as
non- volatile memory.
memories. • Weak in floating
• Powerful in floating point calculations
point calculations • Powerful in bit
• Weak in bit manipulation
manipulation.
 MICROCOMPUTER AND
MICROCONTROLLER
• Instructions are
lengthy and • Instructions are simple
complicated. and short.
• Instruction execution • Instruction execution
speed is slow. speed is fast.
• Instruction set is • Instruction set is not
flexible. flexible.
• General purpose • Application specific
system system.
• Result depends upon • Result depends upon
the quality of the the quality of design.
user program.
 MICROCOMPUTER AND
MICROCONTROLLER
• Mass storage devices • Mass storage devices
are required. are not required.
• The performance is
• The performance is
degraded due to
external access. not degraded
• Microprocessor(CISC • Microcontroller
) follows Von follows Harvard
Neumann architecture i.e.
architecture i.e.. different addressing
common addressing mechanism, functions
mechanism, functions and control signals for
and control signals data and program
for program and data
memories. memories.
 MICROCOMPUTER AND
MICROCONTROLLER

• Programs can be • Programs must be

stored in ROM and stored in ROM only
RAM.
 MICROCONTROLLER
ALU Timer/counters ADC and DAC

Accumulator
I/O Ports
Registers Internal
ROM Interrupt circuits
Internal RAM
Clock circuits

Stack pointer Program counter

8051 MICROCONTROLLER
• 8 bit microcontroller.
• Fabricated using HMOS technology.
• Single +5V power supply.
• On chip 4k bytes of program memory
(ROM/EPROM ).
• On chip 128 bytes of data memory (RAM).
• 32 bi-directional lines (four 8 bit IO ports).
• Multimode, highspeed programmable full duplex
serial port.
• Two multimode 16 bit timer/counter.
 8051 MICROCONTROLLER
• On chip oscillator and clock circuitry.
• Two math registers viz. A and B.
• Sixteen bit PC and DPTR.
• Five two level prioritized interrupts.
• Full depth stack for subroutines.
• Eleven addressing modes (4 for branch and seven
for data.
• Hardware based multiply and divide
instructions. Instruction time is 4s.
• 111 instructions (64 instructions are single
cycles).
8051 MICROCONTROLLER
• Performs both binary and decimal arithmetic.
• Boolean processor for control applications.
• Instruction time is 1s at 1MHzCPU or 12 MHz
crystal.
• Maximum length of the instruction is 3 bytes(4
machine cycles).
• 128 user defined software flags.
• Bit addressable RAM.
• 8 bit program status register and stack pointer.
• Provides four register banks of each 8 registers.
8051 MICROCONTROLLER
• Program memory can be expanded upto 64K
bytes.
• Data memory can be internal(128 bytes) +
external(64K bytes).
• External IO devices.
• Throughput is 10 times higher than that of 8048.
• Direct bit and byte addressability.
• Can detect signed overflow.
• Can do parity computations.
• Provides hardware based multiply and divide
instructions(4sec).
• Upward compatible with exiting 8048 software.
A register B register p.b.borole
8 | E0* 8 | F0* 8051 programming model
Bit TMOD TCON
IP register IE register register
addressed 8 | B8* register
8 | A8* 8 | 89
RAM 8 | 88*
RAM TH0 TL0 TH1 TL1
7F counter counter counter
General FFF counter
purpose 8 | 8C 8 | 8A 8 | 8D 8 | 8B
area SCON SBUF PCON PSW
------------- 30 register register register register
Bit address 2F 8 | 98* 8 | 99 8 | 87 8 | D0*
area* DPTR
-------------- 20 ROM PC SP
DPH |DPL
Register 1F 16 | No address 8 | 81
8 | 83 | 8 | 82
banks
Port 0 Port1 Port2 Port3
3, 2, 1, 0
00 latch latch latch latch
8 | 80* 8 | 90* 8 | A0* 8 | B0*
• Accumulator:-Holds source operand and result
of the arithmetic instructions. It can be source or
destination for logical operations and a number
of special data movement instructions including
table look ups and external RAM expansion.
Used in rotate, parity computation, testing for
zero, Boolean bit manipulation and so on. Even
though the architecture is acc. based, provision
has been made to bypass the acc. in common
instruction situations. Data may be moved from
any location on chip to any register, address or
indirect address, any register may be loaded with
constant. Logical operation may be performed
against register or variables to alter fields of bits.
 8051 programming model
• Variables may be incremented, decremented or
tested without using the acc.
• B-register:- It is an operand register. It is used in
conjunction with acc. as the second input
operand and to return eight bits of the result. It
is intended for multiplication and division.
 7 6 5 4 3 2 1 0

PSW CY AC F0 RS1 RS0 OV --- P

4- Math flags USER ODD

OVER
3- general purpose BANK SELECT
flags F0, GF0 and
GF1.
Math flags:
CY:- Carry flag. It is set by hardware or
software.Used in arithmetic, jump, rotate and
Boolean instructions(acc.)
AC:-Used for BCD arithmetic.
F0:-User defined flag. It is set/cleared/tested by
software.
• RS1 and RS0:- Register bank select bits PSW
RS1 RS0 Register
bank
0 0 Bank0
0 1 Bank1
1 0 Bank2
1 1 Bank3

• OV:- Used in signed arithmetic operations

only.
• P:- Shows a parity of register A; 1= Odd
number of 1’s 0 = Even number of 1’s
 8051 architecture
• Stack pointer:- It is an 8 bit register. It points top
of the stack. It is set to 07h after reset and can be
changed to any internal RAM address by the
programmer. To store a byte on the stack, the
microprocessor increments stack pointer by 1
first and then stores a byte on the stack. To read
a byte from a stack the microprocessor reads a
byte from the stack and then decrements stack
pointer by 1. Hence the stack pointer should be
initialized with the lowest address of the stack
memory.The stack is normally placed in general
purpose area of the internal RAM. It is never
placed in external RAM.
 8051 architecture
• DPTR:-Made up of two 8 bit registers viz.. DPH
& DPL. It is used to hold the address of the
internal and external RAMs.DPH and DPL
individually can be used as 8 bit registers. Each 8
bit register can be used as a data memory
location. It functions as a base register in base
relative addressing mode and indirect jump. It is
also used to hold 16 bit data.
• PC:- 16 bit register. Holds the address of the
program memory. Points next instruction to be
fetched.It cannot be used as a data memory
location
Arithmetic and PSW Special 8051 Block Diagram
logic unit function
Registers latch Port0
8bit RAM
A B data and address bus
latch Port1

ROM
PC DPTR IE latch Port2
IP
16 bit address bus PCON
SBUF
System Timing Byte/Bit address
SCON
Register Bank 3
TCON
System Interrupts Register Bank 2
TMOD latch
Timers Register Bank 1
TL0
Register Bank 0
TH0
Data buffers TL1 Port3
Memory control TH1
 8051 Block Diagram
• ALU:-Performs addition, subtraction,
multiplication, division, logical AND, OR,
EXOR, rotate, clear & compliment operations.
Manipulates 8bit and 16 bit data. Individual bits
may be set, tested, cleared, complimented, moved
and used in logical computation. Provides data
paths and temporary registers for internal
transfers. Makes conditional branching
decisions.Increments registers and automatically
computes program jump addresses. Decrements
registers and compare two bytes through
subtraction. Provides dedicated logic to build
complex instructions such as incrementing a 16
bit register pair.
 8051 Block Diagram
• To execute one form of the compare instructions
e.g. the 8051 increments the PC.three times,
reads three bytes of program memory, computes
a register address with logical operations, reads
internal data memory twice, makes an arithmetic
comparison of two variables, computes a sixteen
bit destination address and decides whether or
not to make a branch within two microseconds.
Additional Boolean processor that can be used
for control applications.
 8051 architecture
7 6 5 4 3 2 1 0
TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TF -> Timer overflow flag; set to 1 when the count is
changed from FFFF to 0000. Cleared automatically
when interrupt vectored to location 001B(TF1) or 000B
(TF0).
TR -> Timer run bit; 1= run the timer 0 = stop the timer
IE -> External interrupt flag:set to 1 when the external
interrupt is activated; cleared automatically when
vectored to location 0013(IE1)and 0003(IE0).
IT -> external Interrupt type; 1= Edge triggered mode
0= level triggered mode
 TMOD 7 6 5 4 3 2 1 0
GATE1 C/T1 M1 M0 GATE0 C/T0 M1 M0

Gate= Enable/disable timer. When it is equal to 1 the

timer is enabled/disabled by INT pin.
C/T =Event counter/ timer.
M1,M0 = Mode selection bits
Mode0 = 8048 timer
Mode1 = 16 bit timer/counter.
Mode2 = 8bit auto reload timer
TH -> TL on overflow.
Mode3 = Two independent 8bit timer TH0 and TL0
controlled by timer1 and timer 0 control bits
Timer1 is stopped.
 7 6 5 4 3 2 1 0
SCON SM0 SM1 SM2 REN TB8 RB8 TI RI

SM0 SM1 MODE Description

0 0 0 Shift register,baud=f/12
0 1 1 8bit UART;baud =variable
1 0 2 9bit UART; baud =f/32 or
f/64
1 1 3 9bit UART; baud
=variable
SM2= Multiprocessor communications bit in mode 2 and 3 When SM2
is 1 the interrupt is activated if bit 9 of the received data is 1. In mode
1, the port activates interrupt only when the valid stop bit is received. In
mode 0, It is always 0.
REN = Receiver enable, TB8=Transmitted bit8 in mode2&3, RB8=
Received bit8 in mode 2&3; stop bit in mode1;not used in mode0
TI=Transmit interrupt flag, RI= Receive interrupt flag
 PCON 7 6 5 4 3 2 1 0

SMOD -- -- -- GF 1 GF 0 PD IDL

SMOD=0, baud rate is1/64 the oscillator frequency in

mode 2. Baud rate is1/32 the timer overflow rate in
mode1&3.
SMOD =1, baud rate is 1/32 the oscillator frequency in
mode 2 Baud rate is1/16 the timer over flow rate in
mode1&3.
GF= General purpose user flag.
PD= Power down mode; on chip oscillator is stopped.
IDL= Ideal mode , The oscillator continues to run and the
interrupt.
serial port and timer blocks continue to be clocked.
 7 6 5 4 3 2 1 0
IE
EA -- - ES ET1 EX1 ET0 EX0
Interrupt
enable EA =Enable interrupt bit
ES =Enable serial port interrupt.
ET = Enable timer interrupt.
EX =Enable external interrupt.
Interrupt 7 6 5 4 3 2 1 0
priority IP
-- -- -- PS PT1 PX1 PT0 PX0
Priority within same level
interrupts
1 IE0 PS = Priority of serial port interrupt.
2 TF0 PT = Priority of timer interrupt.
3 IE1 PX = Priority of external interrupt.
4 TF1
5 Serial
 8051 architecture

• Oscillator and clock circuits:-On chip

logic, but external tuned circuit is
required. Maximum and minimum
frequencies are 16MHz and 1MHz.
Divides oscillator frequency by two.Each
state contains two phases p1 and p2.
 PROGRAM MEMORY
• On chip 4k bytes of memory(ROM).Can
be expanded upto 64k.The address of this
memory is 16 bits and stored in PC only.
It always used to store program only.
During external memory access port2
cannot be used as an I/O port.The
microprocessor cannot write data into
program memory.
PROGRAM MEMORY ORGANIZATION

FFFF
EXTERNAL

EXTERNAL INTERNAL
INTERNAL
EA = 0 EA
EA==11
0000

PSEN
CASE 1= EA = 1 PC accesses 4k internal and 60k external program
memories.
CASE 2 = EA = 0 PC accesses 64k external program memory.
DATA MEMORY ORGANIZATION
External accesses are EXTERNAL FFFF
distinguished by the mnemonic
x in the instruction e.g. movx INTERNAL
* Can access internal and FF
external RAMS
independently 7F
* Rp(R0 and R1) is used to 00
point internal and 0000
external(port0) and port2 for RD WR
page RAMS.
* DPTR is used to point
external(port 0 & port 2) flat
memory RAM
XTAL1
P0.7
XTAL2 P0.0

EA P1.7
P1.0
PSEN

ALE P2.7
P2.0
RXD/P 3.0
RST TXD/P3.1
INT0/P3.2
INT1/P3.3
VSS
T0/P3.4
T1/P3.5
VCC
WR/P3.6
 8051 pin functions
• XTAL1:- I/P line of the internal clock generator. It is
connected to the inverting amplifier.
• XTAL2:-O/P line of the internal inverting amplifier.
XTAL1and XTAL2 are used to connect the crystal.
XTAL2 is used to drive 8051 from a external clock
source, but XTAL1 should EA be grounded.
• EA:- When EA is low, the 8051 accesses only external
program memory otherwise it accesses internal and
external program memories.
• PSEN:- It is used to read contents of external program
memory. It is activated twice every external program
memory cycle. It is not activated for internal fetches.
 8051 pin functions
• ALE:- It is used to latch lower byte of external
memory address(program and data memories).
To provide properly timed signals to latch the
lower byte of address, the ALE is activated twice
every machine cycle. It is activated once in
external data memory access cycle.It is activated
in all internal operations. If the external data
memory is not accessed, then the ALE is
activated at a constant rate of 1/6 the oscillator
frequency. It can be used for external clocking or
timing purposes
 8051 pin functions
• RST:- It is a Schmitt triggered reset I/p line. It
should be maintained high for at least two
machine cycles while oscillator is running. It
initializes ALE and PSEN signals in input modes.
The internal reset is executed during second cycle
and is repeated every cycle until RST goes low.It
clears the following registers. PC, ACC, B,PSW,
DPTR,TMOD, TCON, TH0, TL0,TH1, TL1 and
SCON. SP-> 07, P0-P3 -> FF SBUF ->  , IP-> 
 00000, IE->0  00000, PCON ->0      
 . Internal RAM is not affected by reset.
 8051 pin functions
• PORT0 :- It is an 8 bit bi-directional I/O port.
Logic 1 should be written to float these lines. In
these case, it will function as a high
impedance(open drain) I/p port. During external
accesses, it functions as a multiplexed data and
low order address bus.But internal pull-up is
available during external access.
• PORT1:- It is an 8 bit bi-directional I/O port. To
operate in input mode, logic 1 should be written
into all port lines.
• PORT2:- It is an 8 bit bi-directional I/O port.
During external access, it functions as a high
order address bus.
 8051 pin functions
• PORT3:-It is an 8 bit bi-directional I/O port.
Each line can be used as a special function line
specified by contents of special function registers.
P3.0 -> RXD(SBUF), P3.1 -> TXD(SBUF), P3.2
-> INT0(TCON1), P3.3 -> INT1(TCON3), P3.4 ->
T0(TMOD2), P3.5 ->T1(TMOD6) P3.6 -> WR,
P3.7 -> RD. Each pin of port 3 may be
individually programmed to be used either as I/O
or one of the alternative functions. The alternate
function can only be activated if the
corresponding bit of latch in the port SFR
contains a 1. Otherwise the port pin is stuck at 0.
 Delay in real time control
• Delay has to be provided between two events.
• Two types of events - Software and hardware.
• Software event is initiated by instructions.
• Hardware event is initiated by external device
through interrupt or other signal.
• Event may be periodic or non periodic.
• Two delay methods have been adopted- software
and hardware.
• In software delay the delay program is used to
provide delay between two events.
 Software delay in software events
Execute instruction 1 Event 1

Delay program

Execute instruction 2 Event 2

Applications:- Waveform generation, stepper motor

speed control, digital clock etc.
 Delay in real time
t
system
Desired t1 2

Delay
time
Actual
t2
t1

Desired delay
time
Delay Delay
due due
to instruction1 to instruction 2
 Software delay with hardware event
Provides delay between two external events
INT1 is activated to begin event.
INT2 is activated to terminate event.

P IS INTERRUPTED Event 1

DELAY ISR

P IS INTERRUPTED Event 2

STOP EVENT
 Software delay with hardware event
Desired delay
t1 t2

Delay time
Actual delay
t1 t2

Desired delay time

Latency of interrupt Latency of interrupt
Applications:- Frequency measurement,pulse width
measurement,real time clock,process control,motor
speed measurement etc.
 Drawbacks of software delay
• Not accurate.
• Microprocessor can not perform other
operations.
• Performance of the system is degraded.
• Limitations on minimum delay.
• Cannot handle two or more delay events
simultaneously.
• Expensive.
 Hardware delay techniques
Hardware logic is either analog or digital:
C
1) Analog:- Trigger R

Port
C line 555
Mono
INT O/P
2) Digital:- Count in

C Programmable
clk Timer
INT
 Event detection
• Event is detected through either hardware or
software.
• Event detection through software:-
• Checks overflow of the timer.
• Drawbacks:- Microprocessor can not perform
other operations.
• Performance of the system is degraded.
• Advantage over software delay- 1) Accurate
• 2)Can handle two or more events simultaneously.
• 8051 Software delay:-
Event detection
• R7- 1millisecond delay, Register A + Register B--
1 to 65,535 milliseconds XTAL freq.= 12 MHz
and CPU freq.=1MHz
%Error = Actual delay - desired delay
desired delay 100
0.4 + 0.3B(0.59) +1.5/ desired delay
• For 1ms - Error = 2.04%
• For 256 ms - Error = 41%
• For 65,535 ms - Error = 40%
 Event detection
• Hardware delay with software event detection-
• Error = Actual delay - Desired delay
Desired delay
Error = Desired delay15 + 3B + 10 s
Desired delay( ms)
% Error = 1.5 + 0.3B +1/desired delay
• For 1ms delay error - 2.5%
• For 256ms delay error - 1.5%
• For 65,535 ms delay error - 1.5%
 Hardware delay with hardware event
detection
• In hardware event detection, the microprocessor
can perform all other operations.
• Error is very small and independent of count
value.
• The microprocessor can handle real time events
efficiently.
 TIMER/COUNTER
The 8051provides two 16 bit timers viz.. timer0 and
timer1.Each timer contains 16 bit up counter. Each timer
operates in two modes viz. timer and counter. In timer
mode, it counts internal clock pulses or m/ccycles to
provide delay between two events.Min delay =1s Max.
delay =65535m/c cycle time.The timer mode can be used
to measure time intervals, determine pulse width or
initiate events with one microsecond resolution, upto
maximum interval of 64k m/c cycles.Longer delays may be
accumulated through software. In the timer function, the
register is incremented every machine cycle. The machine
cycle consists of 12 crystal clock periods, hence the count
rate is 1/12 of the oscillator frequency.
 TIMER/COUNTER
In counter mode, the same hardware measures external events or
clock cycles at frequency DC to500khz. In counter mode,
the count register is incremented at the falling edge of external
clock applied at T0 or T1. In this mode, T0 or T1pin is sampled
during S5P2 of every machine cycle. When the samples show
high in one cycle and low in next cycle the count is incremented.
The new count will appear in the register during S3P1of next
machine cycle. Since it takes 2 machine cycles(24 clock periods)
to recognize falling edge of the clock signal,the maximum count
rate is 1/24 of the oscillator frequency. Each high and low state
of the clock cycle must be held constant for at least one machine
cycle to ensure reliable counting. The counter/timer operation is
selected by C/T bit of the TMOD register.There is no restriction
on duty cycle.
 TIMER MODES
Timer operates in 4 modes viz.. mode 0, mode1,
mode2 and mode3. These modes are selected by M1
and M0 of TCON register.
Mode 0: In mode 0, the timer functions like 8048
timer which is an 8 bit counter with a divide by 32
prescalar.In this mode, timer register is configured
as a 13 bit register.
The higher register TH1/0 functions as an 8 bit up
counter TL1/0 functions as a 5 bit counter. As the 8
bit count of TH1/0changes from FF to 00, it sets
TF1/0 flag and activates timer interrupt.
 MODE 0
OSC.  12

C/T=0 32 8 bit counter

T1/0 TL1/0 TH1/0 TF1/0

C/T=1
prescalar
TR1/0
Interrupt
control
Gate1/0

INT1/0
 TIMER MODE 0
To enable counter TR1/0 should be 1 and Gate1/0
should be 0 or INT1/0 should be 1. When Gate1/0 is 1
then the counter is enabled by INT1/0 pin.The pin
INT1/0 functions as an active high GATE1/0 input of
the timer0/timer1. The Pulse width of the signal can
be measured by applying pulse to the INT0/1 pin.

W
Timer mode 0
The 13 bit register consist of 8 bits of TH 0/1 and
lower 5 bits of TL0/1. Upper 3 bits of TL0/1 are
irrelevant.
It counts from N to 3FFF.
Setting TR0/1 flag doesn't clear the registers.
Timer mode:-
Delay = (256 - N )32 12 Crystal clock period.
Counter mode:-
Delay = (256- N) 32 External clock period.
The maximum clock frequency of external clock
signal is crystal frequency/24.
Mode 0 initialization
Initialize

ResetTR0/1

Set gate = 1 to use INT0/1pin as gate input else to

logic0

Set M1, M0 and C/T and initialize TCON

Initialize timer0/1

Set TR0/1 of TMOD to start the timer timer

 Mode116 bit timer
• It is similar to mode0 except that the counter is
16 bit without prescalar.
• 16 bit counter counts from N to FFFF, after
FFFF it sets TF0/1 flag.
• Timer mode:-
• Delay = (65,536- N)12 Crystal clock period.
• Counter mode:-
• Delay = (65,536 -N)  External clock period.
 MODE 1
OSC.  12

C/T=0 16bit counter

T1/0 TL1/0 TH1/0 TF1/0

C/T=1
TR1/0
Interrupt
control
Gate1/0

INT1/0
 Mode 2 8 bit auto reload
• In this mode TL0/1 is automatically loaded with
contents of TH0/1 after each overflow.
• It is used to generate periodic events like pulse
train.
• TH0/1 functions as preset register.
• TL0/1 functions as an 8 bit up counter.
• Initialization sequence is same as mode0 except
that the counter is used for multiple
transitions( N to 255).
 MODE 2
OSC.  12

C/T=0 8bit counter

TL0/1
T1/0 TF1/0
C/T=1
TR1/0
control Reload
Gate1/0
TH0/1 Interrupt
INT1/0
 Mode 3 Two 8 bit independent timers
• In this mode TL0 and TH0 can be used as two separate 8
bit counters.
• TL0 uses Timer0 control bits- INT0, C/T0, GATE0,
TR0,TF0.
• TH0 uses Timer1 control bits- TR1,TF1.
• TL0 operates in timer as well as counter modes.
• TH0operates in timer mode only.
• Timer 1 holds only count value. But it counts when
TR1=0.
• In this mode, it provides 3 timers logically.
• TR1=0 Timer 1 - counts without interrupt e.g. Baud rate
generation in mode1 and 3 of serial port.
• TR1=1 Timer 1- Stopped.
 MODE 3
OSC.  12

C/T0=0 8 bit counter

TL0
T0 TF0
C/T0=1
TR0 Interrupt
control
Gate0
TH0 TF1
INT0
 Serial IO port
• Full duplex high speed serial port.
• Baud rate- 122 bauds to 31k bauds.
• Asynchronous serial data format.
• Multiprocessor communication.
• Interrupt driven port.
• Operates in four modes.
• Receiving path is double buffered. Can be enabled
separately(REN). Transmitter is enabled automatically
by writing data into SBUF.
• SBUF for transmission(write) and reception(read).
• 9th bit is programmable.
• Can detect error in stop bit.
 Operating modes of serial port
• There are two applications of serial IO port viz.
Communication with serial device and
multiprocessor communication.
• All modes are intended for communication with
serial device.
• SM0 and SM1 bits are used in this
communication.
• SM2 bit is normally reset in serial device
communication.
• SM2 bit may be used to detect error in stop bit in
serial device communication.
• SM2 bit must be set in multiprocessor
communication.
 Mode 0 shift register
• Half duplex RXD - transmission and reception.
TXD- Baud rate.
• Baud rate = Oscillator frequency/12.
• Intended for data collection and control of
multipoint control system.
• Framing information like start and stop bits is
not transmitted, hence protocols are not
maintained between transmission and reception.
• Clock signal must be used for synchronization.
Mode 0 application
Monitored data

PISO REG. TXD

Port8051
line
RXD

SIPO REG.
Portline

Control points
 Operation of serial in mode0
It is not intended for serial communication. It can
be used to connect external PISO and SIPO
registers. The RXD line is common for transmission
and reception, hence external hardware is required
to isolate external transmitting device in transmit
mode. Operation of data transmission:-1) The
microcontroller enables SIPO register of external
device.
2) It writes appropriate control word
(SM2=0,SM1=0 SM0=0,REN=0)
3)It writes data into SBUF. The logic 1 is also
written into 9 bit of shift register at S6P2.
 Mode 0
• It activates internal SEND signal to enable shift register.
The time gap between write to SBUF and activation of
SEND is one m/c cycle.
• The SEND signal also activates shift clock on TXD line.
• The shift clock is low during S3,S4 and S5 of the every
m/c cycle and high during S6,S1 and S2.
• The contents of transmit shift register are shifted to the
right one position.
• During transmission MSB of the transmitter loads next
bit with 9th bit(logic 1). This 9th bit indicates the end of
transmission to the internal TX control block and
disables SEND signal and sets TI. Both of these actions
occur at S1P1of the 10th m/c cycle after write to SBUF.
Mode 0 p.b.borole
• Reception is enabled by setting REN bit and RI=0.
• At S6P2 of the next m/c cycle, the RX control unit writes
the bits 11111110 to the receive shift register and in the
next phase activates internal RECEIVE. Signal.
• RECEIVE enables shift clock on TXD line. Shift clock
makes transitions at S3P1 and S6P1 of every m/c cycle.
• At S6P2 of every m/c cycle in which RECEIVE is active,
the contents of the receive shift register are shifted to the
left one bit position. The value that comes in the right
position is the value sampled at the RXD at S5P2 of the
same m/c cycle.
• When the 0 that was initially loaded in rightmost
position arrives at the leftmost position in the shift
register, it indicates the end reception and loads SBUF.
Mode 0

• At S1P1 of the 10th m/c cycle after the

write to SCON that clears RI, RECEIVE
is disabled and RI is set.
 Serial mode1-8 bit UART
• Full duplex port, hence TXD is used for transmission
and RXD is used for reception.
• Total no of data bits to be transmitted is 10( 8 data bits+
1 start bit +1 stop bit).
• Transmission is initiated after loading SBUF.
• Reception begins if REN=1 and start bit is received.
• Received character is loaded into SBUF.
• Stop bit is loaded into RB8.
• In serial device communication, the SM2 bit is set or
reset. This bit is used to detect error in stop bit.
• Not intended for multiprocessor communication.
• Baud rate = 2SMOD/32Timer1 overflow rate. The Timer1
interrupt should be disabled.
 Operation of serial port in mode1
• The microprocessor write data into SBUF. This also
loads a 1 into the 9th bit position of the transmit shift
register and indicates the beginning of transmission.
• The transmission begins at S1P1 of the m/c cycle. I.e. the
the transmission is started after counting operation of
divide by 16 internal counter, hence bit time is
synchronized with internal divide by 16 counter not by
write to SBUF.
• The transmitter activates internal SEND signal to
transmit start bit.
• The transmitter activates internal DATA signal to
transmit data bit.
• Before transmitting MSB, the 1that was loaded in the
9th bit position is added left of the MSB. This is done to
indicate the end of transmission.
 Operation of serial port in mode1
• The transmitter disables internal SEND signal and sets
TI bit.This occurs after 10 operations of divide by 16
counter.
• The reception is initiated by the falling edge of the start
bit.
• The RXD line is sampled at the rate of 16 times
whatever the baud rate has been established.
• When the falling edge of start is detected, it clears divide
16 counter and loads input register with 1FF.
• Each bit time contains 16 states of internal divide by 16
counter.
• The RXD is sampled at 7,8 and 9th count value.
 Operation of serial port in mode1
• If the sampler accepts the value that was seen in at least
2 of the 3 samples. This is done for noise rejection.
• If the valid start bit is not received the receiver is reset
and it waits for new start bit.This is done to provide
rejection of false start bits. If the valid start bit is
received, it is shifted into the input shift register and the
reception of the rest of the data will proceed.
• When the start bit arrives at the left most position of the
input shift register, it indicates the end data reception
and loads SBUF with data and RB8.and sets RI bit.
 Operation of serial port in mode1
• To load received character into SBUF the
following conditions must be satisfied
• 1)RI =0 and
• 2)Either SM2 = 0 or the received stop bit =1.
• If either of two conditions is not met the
received character is ignored.
 Mode 2 and 3- 9 bit UART
• Full duplex port like mode1.
• Transmits 11 bits ( 8 data bits + 1 programmable bit+ 1
start bit + 1 stop bit).
• Baud rate = 2SMOD/64 x Oscillator freq. in mode 2.
• Baud rate = 2SMOD/32 x Timer1 overflow rate in mode 3.
• Intended for multiprocessor communication.
• The error can be detected in data by using 9th bit(e.g.
Parity bit).
• Transmission operation is similar to mode 1 except that
9 th bit is transmitted, hence 11 operations of internal
divide by 16 counter are required to transmit data.
• The reception is similar to mode 1 except that 9th bit is
received and stored in RB8.
 Multiprocessor features
• SM2 bit is used in multiprocessor communications.
• Conditions for serial interrupts:
• When TI is set, it activates serial interrupt in
transmission.
• When RI is set. It activates serial interrupt in reception.
• The RI interrupt depends upon SM2 bit and 9th received
bit.
• If SM2 is 1 and 9th received bit 1, then it interrupts the
CPU.
• If SM2 is 1 and 9th bit 0, then it doesn't interrupt the
CPU.
• If SM2 is 0, the CPU is always interrupted independent of
the 9th bit.
• Ring and bus configurations can be easily implemented.
 Multiprocessor configuration -bus
SM2=0
Talker
TXD
RXD

RXD TXD

LIST. LIST. LIST. LIST. LIST. LIST.

00 01 02 03 04 05

SM2 SM2 SM2 SM2 SM2 SM2

=1 =1 =1 =1 =1 =1
 Flow chart Reset p.b.borole

Set SM2 of all listeners on power reset

Talker sends address(9th bit=1) to all listeners

All listeners are interrupted

All listeners execute their ISRs to check address

The addressed listener resets it’s SM2 bit and

starts transmitting or receiving data with 9th bit = 0
 Interrupts of 8051
• Provides 5 sources of interrupts viz.. INTO, INT1,
timer0, timer1and serial.
• Provides only two priority levels viz. low and high.
• The maximum level of nesting of ISRs is two.
• Provides two hardware external interrupts.
• Provides three internal interrupts.
• It cannot acknowledge interrupt through hardware.
• All interrupts can be requested through software.
• All interrupts are maskable.
• Vector address of each interrupt is fixed and located in
program memory only.
Interrupts of 8051
• Priority level structure-
• Each interrupt has two priority levels viz.. Low
and high.
• When two different priority level interrupts are
activated simultaneously, it accepts only high
priority interrupt.
• When two same priority level interrupts are
activated simultaneously, it executes internal
polling sequence to resolve the priority of the
interrupt. The polling sequence is only used to
resolve simultaneous request of same level.The
polling sequence is
 Interrupts of 8051
SOURCES PRIORITY
IE0 1

TF0 2
IE1 3

TF1 4

RI+TI 5
Interrupt operations
• The interrupt flags are sampled at S5P2 of every m/c
cycle.
• But the samples are checked in next machine cycle.This
cycle is also called polling cycle.
• If the flags are set, it resolves priority of unmasked
interrupts and accepts high priority interrupt.
• It executes LCALL instruction after completion of
polling cycle provided that the interrupt is not blocked
by any of the following conditions:
• 1) An interrupt of high or same level interrupt is already
in progress. 2)The polling cycle is not the final cycle of
the instruction cycle. 3)The CPU is executing IRET or
instruction accessing IE and IP.
Interrupt operations
• If the interrupt is activated in last m/c of the current
instruction cycle, the microprocessor completes next
instruction execution.
• The microprocessor does not terminate current
instruction execution.
• The microprocessor always completes next instruction
after RETI and access to IP and IE register.
• All flags are polled in each machine cycle.If the
interrupt is not accepted by CPU due to any of blocking
conditions in the current polling cycle, the CPU will get
new values of flags in the next m/c cycle. Hence previous
sampled values are cancelled. The interrupt source may
lose interrupt activity due to blocking conditions.
 Interrupt operations
• The LCALL takes two m/c cycles. If high priority
interrupt is activated before S5P2 of first m/c
cycle of LCALL and after accepting lower
priority interrupt, the LCALL of the new higher
priority interrupt will be executed after
completion of current LCALL execution.
• During execution of LCALL, it clears IE0(edge
triggered) IE1 (edge triggered), TF0 and TF1. It
never clears TI and RI.
• The LCALL saves contents of PC on the stack. It
does not save contents of PSW.
• The microprocessor executes ISR.
Interrupt operations
• The addresses of ISRs are given below:
• IE0 -> 0003H, TF0-> 000BH, IE1-> 0013H
TF1 -> 001BH, TI+RI -> 0023H
• At the end of ISR it executes RETI instruction to
transfer microprocessor control to main
program.
• This instruction tells the completion of ISR.But
RET will not be able to tell the completion of the
ISR.
• The RETI pops two bytes from the stack.
 Interrupts of 8051
• Types of interrupts:-
• External interrupts - 8051 provides two external
interrupts. They can be programmed in either edge or
level triggered modes depending of IT bit of TCON
register.
• In edge triggered mode, the interrupt is requested at the
falling edge of the signal. This signal sets IE bit of the
TCON register. Then this bit activates the
corresponding external interrupt. In this mode the IE
bit is cleared automatically after invoking ISR.
• In level triggered mode, the interrupt is requested at the
low level of the signal.
Interrupts of 8051
• In level triggered mode, the corresponding IE bit
TCON register is set at low level of this signal
then this bit activates the corresponding external
interrupt. But this bit is not cleared
automatically after invoking ISR, hence the IE
bit must be cleared by the ISR.
• The external interrupts are sampled once each
m/c cycle, Hence two m/c cycles are needed to
recognize falling edge of the interrupt signal in
edge triggered mode, hence the signal should be
maintained high for at least one m/c cycle. Then
it should be maintained low for at least one m/c
cycle.
 Interrupts of 8051
• In level triggered mode, the interrupt signal should be
maintained low until it is acknowledged. This signal
should be removed before completion of the ISR.
• The levels of INT0 and INT1 are inverted and latched
into IE0 and IE1at S5P2 of every m/c cycle.
• But the values are not actually polled by the CPU until
the next m/c cycle. If the request is active and interrupt
is valid then it executes LCALL instruction internally to
transfer microprocessor’s control to the ISR after
completion of the current m/c cycle. Hence the minimum
time gap between activation of interrupt and beginning
of execution of ISR is three m/c cycles.
 Interrupts of 8051
• Timer interrupts :- Provides two timer interrupts.
• Timer1 interrupt is requested by TF1 and timer0
interrupt is requested by TF0.
• TF0 and TF1 are set by timers.
• These flags are automatically cleared after invoking
timer ISR.
• Serial interrupt:- This interrupt is common for serial
transmission and serial reception.
• It is activated by TI or RI.Where TI is set by transmitter
( SBUF is empty) and RI is set by receiver( SBUF is full).
• These bits are not cleared after invoking ISR.
• TI and RI bits are used by ISR to distinguish
between transmitter and receiver interrupts.
Single step operation
• In response to any interrupt the microprocessor
completes current instruction cycle. This feature
can be used to complete current instruction of
the main program.
• It doesn't accept same priority level interrupt
during execution of the ISR, hence we can use
same interrupt for other purpose during
execution of same interrupt ISR.
• If the interrupt is activated in IRET instruction,
the microprocessor completes IRET and next
instruction. This feature can be used to execute
only one instruction of the main program.
Single stepping +5v

Single step key

INT0

8051
 Single stepping
Single step ISR

L1:JNB P3.2 L1

L2:JB P3.2 L2

RETI
 EXPANSION OF
MICROCONTROLLERS
• Needs of expansion:- • Expandable
• Insufficient internal resources:-
resources. • Program memory.
• Software and • Data memory.
hardware • I/O ports.
development.
• System debugging
and testing.
 8051 MICROCONTROLLER
EXPANSION
• On chip resources
• ROM 4k 8 bits [0000 to 0FFF] POINTER
-> PC(16 bit).
• RAM 128  8bits {1- Four register banks
of each 8 bytes[00 to 1F] 2- Bit mapped
memory 16 bytes [20 to 2F]3- General
purpose data memory 8bytes [30 to 7F]4-
Special function registers [80 to FF]}.
• 8751 4k 8bits EPROM, 8031-> NIL.
 MEMORY EXPANSION
FEATURES
• The internal partitioning of program and data is
extended to external memory.
• Each uses same address but different control
signals i.e. program memory is accessed by PSEN
signal and data memory is accessed by RD AND
WR signals.
• Both can be expanded upto 64k bytes.
• External data memory can be divided into pages
of 256 each.
 MEMORY EXPANSION
FEATURES
• Provides strappable pin EA
• EA = 1 ->4K+60K ROM(Internal and external)
and 128+128+64K RAM(Internal and external).
• EA = 0 -> 64K (External) program memory and
128 +128 +64K RAM (Internal and external).
• External data and program memories can be
combined to follow Von Neumann architecture.
 MEMORY EXPANSION
FEATURES
WR MEMW
RD

PSEN MEMR

* Provides separate instructions for external data memory

* Port 0 functions as multiplexed address/ data bus
* Port 2 functions as high order address bus
 IO EXPANSION
• Provides 4 I/O ports
• Both I/O mapped I/O and memory
mapped I/O.
• I/O mapped I/O is slow, but any port can
be accessed.
• General purpose devices can be
interfaced 8255, 8155, 8355, 8755, 8251,
8279, 8275, 8295, ADC and DAC.