Digital Logic Design Cs302 Power Point Slides Lecture 01
Digital Logic Design Cs302 Power Point Slides Lecture 01
Lecture 01
Analogue Quantities
Continuous Quantity
Intensity of Light
Temperature
Velocity
Digital Values
45
40
35
30
temperature 0C
25
20
15
10
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
time
Continuous Signal
45
42 41
40
37
35 34 35
30
temperature 0C
29
25 25 25
23 22
20
18
15
10
7
5 4
1 2
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
time
Digital Representation
45
42 41
40
37
35 34 35
30
temperature 0C
29
25 25 25
23 22
20
18
15
10
7
5 4
1 2
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
samples
Under Sampling
45
40
35
30
temperature 0C
25
20
15
10
0
1 3 5 7 9 11 13 15
samples
Electronic Processing
Analogue Systems
Digital Systems
Representing quantities in Digital Systems
Representing Digital Values
39 0C ? Digital 39mV
System
8
b2
b3
b4
b1
1mV = 1
0
0
GND
Vcc1
a2
a3
a4
a1
1
6.25 x 1015 V !!
6.25 x 1018 ?
Digital Systems
Black/White
Hot/Cold
Stationary/Moving
Binary Number System
Binary Numbers
Representing Multiple Values
Combination of 0v & 5v
Merits of Digital Systems
Numbers
Text
Formula and Equations
Drawings and Pictures
Sound and Music
Logic Gates
Building Blocks
AND, OR and NOT Gates
NAND, NOR, XOR and XNOR Gates
Integrated Circuits (ICs)
Logic Gate Symbol and ICs
13
12
11
10
6
1
3
Combinational Circuits
Sum
Carry
Functional Devices
Functional Devices
Adders
Comparators
Encoders/Decoders
Multiplexers/Demultiplexers
Sequential Circuits
Memory Element
Current & Previous State
Flip-Flops
Counters & Registers
Block Diagram of a Sequential Circuit
Input 1
a1 b1
5
Output
Combinational
2 6
a2 b2
Logic Circuit
1 5
a1 b1
Memory Element
Programmable Logic Devices (PLDs)
Configurable Hardware
Combinational Circuits
Sequential Circuits
Low chip count
Lower Cost
Short development time
Memory
Storage
RAM (Random Access Memory)
Read-Write
Volatile
Non-Volatile
A/D & D/A Converters
x1
*/*
u1
Digital x1
*/*
u1
Controller
A/D D/A
Converter Converter
Thermocouple
Reaction
Vessel
Heater
Control
Summary
Continuous Signals
Digital Representation in Binary
Information Processing
Logic Gates
Summary
∑, ∆, >, Ω and ↑
Base – 5 Number System
∆Ω↑∑ = 220
Caveman Number System
Decimal Number Caveman Number Decimal Number Caveman Number
0 ∑ 10 >∑
1 ∆ 11 >∆
2 > 12 >>
3 Ω 13 >Ω
4 ↑ 14 >↑
5 ∆∑ 15 Ω∑
6 ∆∆ 16 Ω∆
7 ∆> 17 Ω>
8 ∆Ω 18 ΩΩ
9 ∆↑ 19 Ω↑
Caveman Number System
0 0 10 1010
1 1 11 1011
2 10 12 1100
3 11 13 1101
4 100 14 1110
5 101 15 1111
6 110 16 10000
7 111 17 10001
8 1000 18 10010
9 1001 19 10011
Combination of Binary Bits
Combination of Bits
100112 = 1910
= (1 x 24) + (0 x 23) + (0 x 22) + (1 x 21)
+ (1 x 20)
= (1 x 16) + (0 x 8) + (0 x 4) + (1 x 2)
+ (1 x 1)
= 16 + 0 + 0 + 2 + 1
= 19
Fractions in Binary
Fractions in Binary
1011.1012 = 11.625
= (1 x 23) + (0 x 22) + (1 x 21) + (1 x 20)
+ (1 x 2-1) + (0 x 2-2) + (1 x 2-3)
= (1 x 8) + (0 x 4) + (1 x 2) + (1 x 1)
+ (1 x 1/2) + (0 x 1/4) + (1 x 1/8)
= 8 + 0 + 2 + 1 + 0.5 + 0 + 0.125
= 11.625
Floating Point Notations
Decimal-Binary Conversion
Repeated Division by 2
Decimal to binary conversion using
Sum of weight
Number Weight Result after subtraction Binary
100112
(1 24 ) (0 23 ) (0 22 ) (1 21 )
(1 2 )
0
100112 16 2 1 19
1011.1012 8 2 1 1
2 8
11 5
8
11.625
Lecture No. 1
Number Systems
A Summary