14th Week Lecture Slides

Latches and Flip-Flops

• Latches are also called transparent or level triggered flip flops,

because the change on the outputs will follow the changes of the
inputs as long as the Enable input is set.
• Edge triggered flip flops are the flip flops that change there outputs
only at the transition of the Enable input. The enable is called the
Clock input.

2
 Edge Detection Circuits
Edge detection circuits are used to detect the transition of the Enable from logic 0 to
logic 1 (positive edge) or from logic 1 to logic 0 (negative edge). The operation of
the edge detection circuits shown below is based on the fact that there is a time delay
between the change of the input of a gate and the change at the output. This delay is
in the order of a few nanoseconds. The Enable in this case is called the Clock (CLK)

Positive Edge Detection Negative Edge Detection

EN
EN' EN
EN'
EN
EN
EN

EN EN

EN

EN
EN

EN' EN'

3
 The JK Edge Triggered Flip Flop

The JK edge triggered flip flop can be obtained by inserting an edge detection circuit
at the Enable (CLK) input of a JK latch. This ensures that the outputs of the flip flop
will change only when the CLK changes (0 to 1 for +ve edge or 1 to 0 for –ve edge)

Positive Edge JK Flip Flop Negative Edge JK Flip Flop

J J
S Q Q S Q Q

CLK CLK

R Q Q R Q Q
K K

CLK J K QN+1 Function CLK J K QN+1 Function

Logic Symbol Logic Symbol
X X Q X X
J Q J Q
0 0 Q 0 0
CLK CLK
K Q 0 1 0 K Q 0 1
1 0 1 1 0
1 1 Q’ 1 1

4
 The D Edge Triggered Flip Flop
The D edge triggered flip flop can be obtained by connecting the J with the K inputs
of a JK flip through an inverter as shown below. The D edge trigger can also be
obtained by connecting the S with the R inputs of a SR edge triggered flip flop
through an inverter.

Positive Edge D Flip Flop Negative Edge D Flip Flop

D J Q Q D J Q Q

CLK CLK

K Q Q K Q Q

Logic Symbol CLK D QN+1 Function Logic Symbol CLK D QN+1 Function
D Q X Q D Q X Q
CLK 0 CLK 0
0 0
Q Q 1
1 1 1

5
 The Toggle (T) Edge Triggered Flip Flop
The T edge triggered flip flop can be obtained by connecting the J with the K inputs
of a JK flip directly. When T is zero then both J and K are zero and the Q output does
not change. When T is one then both J and K are one and the Q output will change to
the opposite state, or toggle.
Positive Edge T Flip Flop Negative Edge T Flip Flop

T J Q Q T J Q Q

CLK CLK

K Q Q K Q Q

Logic Symbol CLK T QN+1 Function Logic Symbol CLK T QN+1 Function
T Q X Q T Q X Q
CLK 0 Q CLK 0 Q
Q 1 Q΄ Q 1 Q΄

6
 Summary
Flip-Flop Flip-Flop Characteristic Characteristic Excitation
Name Symbol Table Equations Table

S R Q+ Q Q+ S R
S Q
S-R 0 0 Q Q+ = S + R Q 0 0 0 X
R Q 0 1 0
Clk 0 1 1 0
1 0 1 1 0 0 1
1 1 NA 1 1 X 0

J K Q+ Q Q+ J K

Q Q+ S R
J Q
J-K 0 0 Q Q+ = J Q + K Q 0 0 0 X
K Q 0 1 0
Clk 0 1 1 X
1 0 1 1 0 X 1
1 1 Q 1 1 X 0

D Q+
Hold
0 Q
0
Q+ D
0 X
0 1 1 0
D Q
D 0 0 Q+ = D
Clk
Q 1 1
Reset 0
0
1
0
1
0
0
1
0

Set 1
1 1

0
1

0 1
T
T Q
T Q+
NA Q+ = T Q + T Q
Q Q+ T

1 1 X 0
0 Q 0 0 0
Q 1 Q
Clk 0 1 1
1 0 1
1 1 0

Flip-Fl op Flip-Flop Char acteri sti c Character istic Exci tation

Name Symbol Table Equati ons Tabl e

S-R
S
R
Clk
Q
Q
S

0
0
1
1
R

0
1
0
1
Q+

Q
0
1
NA
Q+ = S + R Q
Q Q

0
0
1
1
Q+
Q+

0
1
0
1
S

0
1
0
X
J
R

X
0
1
0
K
J-K
J
K
Cl k
Q
Q
J

0
0
1
K

0
1
0
Q+

Q
0
1
Hold Q+ = J Q + K Q 0Q

0
0
1
0
Q+

0
1
0
J

0
1
X
0
K

X
X
1
X
Reset 0 1 1 X
1 1 Q 1 1 X 0

D Q+ Q Q+ D

Set
D Q
D 0 0 Q+ = D 0 0 0

1 0 X 1
Q 1 1
Clk 0 1 1
1 0 0
1 1 1

T Q
T Q+ Toggle Q Q+ T

1 1 X 0
T 0 Q Q+ = T Q + T Q 0 0 0
Q 1 Q
Clk 0 1 1
1 0 1
1 1 0

Flip-Flop Flip-Flo p Characteristic Characteristic Excitation

Q Q+ D
Name Symb ol Tab le Equati ons Table

S R Q+ Q Q+ S R
S Q
S-R 0 0 Q Q +
= S + R Q 0 0 0 X
R Q 0 1 0
Clk 0 1 1 0

0 0 0
1 0 1 1 0 0 1
1 1 NA 1 1 X 0

Reset
J K Q+ Q Q+ J K
J Q
J-K 0 0 Q Q+ = J Q + K Q 0 0 0 X
K Q

0 1 1
Clk 0 1 0 0 1 1 X
1 0 1 1 0 X 1

Set
1 1 Q 1 1 X 0

D Q+ Q Q +
D
D Q

1 0 0
D 0 0 Q+ = D 0 0 0
Q 1 1
Clk 0 1 1
1 0 0
1 1 1

T Q+ Q Q+ T

1 1 1
T Q
T 0 Q Q+ = T Q + T Q 0 0 0
Q 1 Q
Clk 0 1 1
1 0 1
1 1 0

Flip-Fl op Flip-Flop Char acteri sti c Character istic Exci tation

Name Symbol Table Equati ons Tabl e

Q Q+ T
S R Q+ Q Q+ S R
S Q
S-R 0 0 Q Q+ = S + R Q 0 0 0 X
R Q 0 1 0
Clk 0 1 1 0
1 0 1 1 0 0 1
1 1 NA 1 1 X 0

J-K
J
K
Cl k
Q
Q
J

0
0
1
1
K

0
1
0
1
Q+

Q
0
1
Q
Hold Q+ = J Q + K Q 0Q

0
0
1
Q+

0
1
0
0 J

0
1
X
0
K

X
X
1

0 1 1
1 1 X 0

D
D Q
D Q+
Toggle Q+ = D
Q Q+ D
0 0 0 0 0
Q 1 1
Clk 0 1 1

1 0 1
1 0 0
1 1 1

T Q+ Q Q+ T
T Q
T 0 Q Q+ = T Q + T Q

1 1 0
0 0 0
Q 1 Q
Clk 0 1 1
1 0 1
1 1 0

7
 Flip Flops with asynchronous inputs (Preset and Clear)

Two extra inputs are often found on flip flops, that either Preset or Clear the output.
These inputs are effective at any time, thus are called asynchronous. If the Clear is at
logic 0 then the output is forced to 0, irrespective of the other normal inputs. If the
Preset is at logic 0 then the output is forced to 1, irrespective of the other normal
inputs. The Preset and the Clear inputs can not be 0 simultaneously. In the Preset and
Clear are both 1 then the flip flop behaves according to its normal truth table.

Positive Edge JK Flip Flop with Preset and Clear

CLK PR CLR J K QN+1 Function

PRESET
PR
0 0 X X
J Q
0 1 X X 1
1 0 X X 0
K Q 1 1 0 0 Q
CLR
1 1 0 1 0
CLEAR
1 1 1 0 1
1 1 1 1 Q’

8
 Data (D) Latch :- Example
Complete the timing diagrams for :
(a) D Latch
(b) JK Latch
Assume that for both cases the Q output is initially at logic zero.

(a) (b)

Enable Enable

Data (D) J

K
Q

9
 JK Edge Triggered Flip Flop :- Example
Complete the timing diagrams for :
(a) Positive Edge Triggered JK Flip Flop
(b) Negative Edge Triggered JK Flip Flop
Assume that for both cases the Q output is initially at logic zero.

(a) (b)

CLK CLK

J J

K K

Q Q

10
 D and T Edge Triggered Flip Flops :- Example
Complete the timing diagrams for :
(a) Positive Edge Triggered D Flip Flop
(b) Positive Edge Triggered T Flip Flop
(c) Negative Edge Triggered T Flip Flop
(d) Negative Edge Triggered D Flip Flop
(a) (b)

CLK CLK

D D

Q Q

(c) (d)

CLK CLK

T T

Q Q

11
 JK Flip Flop With Preset and Clear:- Example
Complete the timing diagrams for :
(a) Positive Edge Triggered JK Flip Flop
(b) Negative Edge Triggered JK Flip Flop.
Assume that for both cases the Q output is initially at logic zero.

(a) (b)

CLK CLK

J J

K K

CLR CLR

PR PR

Q Q

12
 Flip-Flop Applications
• Parallel data storage
• Frequency division
• Counting

13
Flip-Flop Applications: parallel data
storage
• Store several bits of data from parallel lines
simultaneously in a group of flip-flops.
• As shown in the next slide, the asynchronous
reset (R) inputs are connected to a common
CLR line, which initially resets all the flip-
flops.
• This is an example of a basic register used for
data storage.

14
15
Flip-Flop Applications: Frequency division
• Dividing (reducing) the frequency of a
periodic waveform.
• When a pulse waveform is applied to the clock
input of the J-K flip-flop with a toggle mode,
the Q output is a square wave with one-half
the frequency of the clock input.
• Thus, a single flip-flop can be applied as a
divide-by-2 device, i.e., resulting in an output
that changes at half the frequency of the clock
waveform.
16
The J-K flip-flop as a divide-by-2 device. Q is one-half the
.frequency of CLK

17
Example of two J-K flip-flops used to divide the clock frequency by
4. QA is one-half and QB is one-fourth the frequency of CLK.

18
Example: Develop the fout waveform for the given circuit when an 8
KHz square wave input is applied to the clock input of the flip-flop.

19
Flip-Flop Applications: Counting

20
Example: Determine the output waveform in relation to the
clock for QA, QB, and QC in the circuit shown. Show also the
binary sequence represented by these waveforms.

21