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VLSI Design Style

The document discusses different VLSI design styles including data path design of a 4-bit ripple carry adder using full adders, the VLSI design cycle, physical design process, FPGA architecture including lookup tables and routing, gate arrays, standard cell based design and full custom design.

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Selvaraj Sathiyaseelan
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59 views34 pages

VLSI Design Style

The document discusses different VLSI design styles including data path design of a 4-bit ripple carry adder using full adders, the VLSI design cycle, physical design process, FPGA architecture including lookup tables and routing, gate arrays, standard cell based design and full custom design.

Uploaded by

Selvaraj Sathiyaseelan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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VLSI DESIGN

STYLE
Data Path Design
• Example: A 4-bit Ripple Carry Adder

• Consists of four full adders.


• Each full adder consists of a sum circuit and a carry circuit.
Cont’
• We instantiate carry and sum circuits to create a full adder.
• We instantiate four full adder to create the 4-bit adder.

• Carry=A.B+B.C+C.A
• Sum=A ⊕B ⊕C
VLSI Design Cycle
• Large number of devices
• Optimization requirements for high performance
• Time-to-market competition
• Cost
VLSI Design Cycle
(contd.)
1. System specification
2. Functional design
3. Logic design
4. Circuit design
5. Physical design
6. Design verification
7. Fabrication
8. Packaging, Testing and Debugging
Physical Design
• Converts a circuit description into a geometric description.
 This description is used for fabrication of the chip
• Basic steps in the physical design cycle:
 Partitioning, floor planning and placement
 Routing
 Static timing analysis
 Signal integrity and crosstalk analysis
 Physical verification and signoff
Various Design Styles
• Programmable Logic Devices
 Field Programmable Gate Array (FPGA)
 Gate Array
• Standard Cell (Semi-Custom Design)
• Full-Custom Design
Which Design Style to
Use?
• Basically a trade-off among several design parameters.
 Hardware cost
 Circuit delay
 Time required
• Optimizing on these parameters Is often conflicting.
What does FPGA offer?
• User/Field Programmability
 Array of logic cells connected via routing channels
 Different types of cells:
 Special I/O cells
 Logic cells (Mainly lookup tables (LUT) with associated registers)
 Interconnection between cells:
 Using SRAM based switches
 Using anti-fuse elements
Ease of Use
• FPGA chips are manufactured by a number of vendors:
 Xilinx, Altera, Actel, etc
 Products vary widely in capability
• FPGA development boards and CAD software available from
many sellers.
 Allows rapid prototyping in laboratory
CLB Functionalities
• Two 4-input function generators
 Implemented using Lookup Tables using 16x1 RAM.
 Can also implement 16x1 memory.
• Two 1-bit registers
 Each can be configured as flip-flop or latch
 Independent clock polarity
 Synchronous and asynchronous Set/Reset
Look Up Tables (LUT)
• Combinational Logic is stored in 16x1 SRAM LUTs in a
CLB.
• Capacity is limited by number of inputs, not complexity.
• Choose to use each function generator as 4-input logic (LUT)
or as high-speed RAM
LUT Mapping: An
Example
• A function: f=A’.B+B’.C.D
• The mapping process:
 Create the truth table of the 4-variable function
 Load the output column into SRAM corresponding to the LUT
 Apply the function inputs to the LUT inputs
• Any 4-variable function can be realized
 Netlist to LUT mapping is an interesting design trade-off
Area-Delay Tradeoff
XC4000x I/O Block Diagram
Xilinx FPGA Routing
• Fast Direct Interconnect-CLB to CLB
• General Purpose Interconnect
 Uses switch matrix
FPGA Design flow
• Design Entry
 In schematic, VHDL or Verilog
• Implementation
 Placement & Routing
 Bit stream generation
 Analyze timing, view layout, simulation, etc
• Download
 Directly to Xilinx H/W devices with unlimited reconfiguration
• In view of the speed of prototyping capability, the gate array
(GA) comes after the FPGA.
• Design implementation of
 FPGA chip is done with user programming
 Gate array is done with metal mask design processing
Cont’
• Gate array implementation requires a 2-step manufacturing
process:
a) The first phase, which is based on generic (standard0 masks, results in an array of
uncommitted transistors on each GA chip
b) These uncommitted chips can be customized later, which is completed by defining
the metal interconnects between the transistors of the array
Two-step Manufacture
Cont’
• The GA chip utilization factor is higher than that of FPGA
 The used chip area divided by the total chip area
• Chip speed is also higher
 More customized design can be achieved with metal mask designs
• Typical gate array chips can implement millions of logic gates
Standard Cell Based
Design
• One of the most prevalent design styles
 Also called semi-custom design style
 Requires developing full custom mask set
• Basic idea:
 Commonly used logic cells are developed, and stored in a standard cell library
 Typical library may contain a few hundred cells(Inverters, NAND, NOR, AOI, OAI, 2-t0-
1 MUX, D-latches, flip-flops, etc)
Characteristic of the Cells
• Each cell is designed with a fixed height
 To enable automated placement of the cells and routing of the inter-cell connections
 A number of cells can be abutted side-by-side to form rows
• The power and ground rails typically run parallel to upper and
lower boundaries of cell
 Neighboring cells share a common power and ground bus.
• The i/p and o/p pins are located on the upper and lower
boundaries of the cell
Standard Cell Example
•  Made to stack side by side
 Fixed height
 Width can Vary
 Can abut at
Floorplan for Standard
Cell Design
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• Dfsd
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Full Custom Design
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• Sdfgsd
• Dffgdf
• Zgsdfg
• Fsdfd

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