CHAPTER 2

THE PROCESSOR UNIT (CPU)

By: Solomon S.

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Topic Contents
• Computer arithmetic
 The ALU
 Integer representation
 Floating point representation and arithmetic
• Instruction sets
 Types of operands
 Data types
• Instruction formats
 Three-address
 Two-address
 One-address
 Zero-address
• Processor organization
 Instruction pipelining 2
Computer arithmetic
o Computer arithmetic is a branch of
computer engineering that deals with
methods of representing integers and
real values (e.g., fixed- and floating-
point numbers) in digital systems and
o Efficient algorithms for manipulating
such numbers by means of hardware
circuits or software routines
Cont…
The two principal concerns for computer
arithmetic.
1) The way in which numbers are represented
(the binary format) and
2) The algorithms used for the basic arithmetic
operations (add, subtract, multiply, divide).
 These two considerations apply both to
integer and floating-point arithmetic.
Cont..
?
How can a computer perform arithmetic operations?

Well, it depends on the type of numbers:

integer and floating point;
• Representation is a crucial design issue...
?What is the computer component responsible for calculations?
ALU( Arithmetic And Logic Unit)

Arithmetic Logic Unit

Component that performs arithmetic and
logical operations;
All other system components are there mainly
to:
 Bring data into the ALU;
 Process data;
 Take results back out;
 General organization
of the ALU Textual description of the image:
Operands for arithmetic/logic
operations are provided in
registers;
Results of an operation are also
stored in registers;
ALU may also set flags as the
result of an operation, e.g.:
Operand Result  Auxiliary Carry flag is set to 1:
 If a Carry is generated from 3rd bit
to the 4th bit when we adding two
binary numbers.
 Zero flag is set to 1:
 If a result produces value zero
(JMP.Z, JMP.NZ, etc...)
Integer Representation
o Computers are designed to use binary digits to
represent numbers and other information.
o The computer memory is organized into
strings of bits called words of same length.
Decimal numbers are first converted into their
binary equivalents and then are represented in
either integer or floating point form.
Cont..
o Bit-- Binary Digit
 1 byte = 8 bits
 1 word = 2 bytes
o Integer takes up two bytes; can be signed or
unsigned.
 Can represent numbers from -32,767 to 32,767.
Cont..

Signed Integers
o Need to reserve one bit for the sign.
o Three ways:
 Sign-Magnitude
 1's Complement
 2's Complement
Cont..

I. Sign-Magnitude
o Uses most significant bit of the word to represent the sign.
 0 - Positive
 1 - Negative.
o Rest of the number is encoded in magnitude part
 37 = 00000000 00100101
 -37 = 10000000 00100101
 6712 = 00011010 00111000
 -6712 = 10011010 00111000
o Can represent numbers from -32,767 to 32,767.
o But, two representations for zero, which is poor side of sign-
magnitude:
• 0 = 00000000 00000000
• -0 = 10000000 00000000
The general case can be expressed as follows:

There are several drawbacks to sign-magnitude representation.

 One is that addition and subtraction require a consideration
of both the signs of the numbers and their relative
magnitudes to carry out the required operation.
 The other drawback is there are two representations of 0:
+ 010 = 00000000
 -010 = 10000000 (sign magnitude)

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Cont..

II. 1's Complement

o Negative number is stored as bit-wise complement of
corresponding positive number.
o Leftmost bit of positive number is 0. That of negative
number is 1.
196 = 00000000 11000100
-196 = 11111111 00111011
o Can represent numbers from -32,767 to 32,767.
o Arithmetic is easier than sign-magnitude.
o But, still have two representations for zero:
 0 = 00000000 00000000
-0 = 11111111 11111111
Cont..

III. 2's Complement

o Modern Method
o Positive number represented in same way as other two methods
o Negative number obtained by taking 1's Complement of positive
number and adding 1.
 6713 = 00011000 00011101
 1's Comp = 11100111 11100010
 2's Comp = 11100111 11100011
o Word integer can represent numbers from -32,768 to 32,767.
o Byte integer can represent numbers from -128 to 127.
o One version of zero: Eg.
 00000000 00000000
Block Diagram of Hardware for Addition and
Subtraction
Cont..
o The above figure suggests the data paths and hardware
elements needed to accomplish addition and subtraction
o The central element is a binary adder, which is presented
two numbers for addition and produces a sum and an overflow sign.
o The binary adder treats the two numbers as unsigned integers.
o For addition, the two numbers are presented to the adder from
two registers, designated in this case as A and B registers.
o The result may be stored in one of these registers
o The overflow indication is stored in a 1-bit overflow flag
 0 = no overflow;
 1 = overflow.
o For subtraction, the subtrahend (B register) is passed through
a twos complementer so that its twos complement is presented
to the adder.
 ? Individual Assignment on Floating point
representation and arithmetic

 Floating-Point Representation
 IEEE Standard for Binary Floating-Point
Representation
 Floating-Point Arithmetic
 IEEE Standard for Binary Floating-Point
Arithmetic
Submit on 30/03/2021
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Instruction sets KEY POINTS

 An operand reference in an instruction either contains the

actual value of the operand (immediate) or a reference to the

address of the operand.

 A wide variety of addressing modes is used in various

instruction sets.
 These include direct (operand address is in address field), indirect

(address field points to a location that contains the operand address),

register, register indirect, and various forms of displacement, in which

a register value is added to an address value to produce the operand

address.
 Cont…
 What is an Instruction Set?
o Instruction set: The complete collection of instructions
that are understood by a CPU
o Machine language: binary representation of operations
and (addresses of) arguments
o Assembly language: mnemonic representation for
humans, e.g., MOV A, C A <- C

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 Cont…
 Elements of an Instruction
o Instruction in memory has two parts:
 opcode and
 operands.
o The opcode identifies the operation that instruction does
o The operands are subjects of the operation, such as data
values, registers, or memory addresses.
o Due to variety of opcodes and operands, instructions
may occupy different sizes of bytes in memory.
 Eg. SHLD, STA

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Instruction Types
o registers,
o main memory,
Data transfer
o stack or
o I/O

o arithmetic,
Data processing
o logical

o systems control,
Program flow control
o transfer of control
o Branch control 21
Data Transfer
• Instructions like: Store, load, exchange,
move, clear, set, push, pop
• Specifies source and destination (memory,
register, stack), amount of data
• May be different instructions for different
(size, location) movements
Arithmetic
• Add, Subtract, Multiply, Divide for signed
integer (+ floating point and packed decimal)
• May include
– Absolute (|a|)
– Increment (a++)
– Decrement (a--)
– Negate (-a)
Logical
• Bitwise operations: AND, OR, NOT, XOR,
TEST, CMP, SET
• Shifting and rotating functions, e.g.
– logical right shift for unpacking: send 8-bit
character from 16-bit word
– arithmetic right shift: division and truncation for
odd numbers
– arithmetic left shift: multiplication without
overflow
Transfer of Control
• Skip, e.g., increment and skip if zero:
ISZ Reg1, jumping out from loop if it’s true
• Branch instructions: BRZ X (branch to X if
result is zero), BRP X (positive), BRN X
(negative), BRE X,R1,R2 (equal)
• Procedure: call and return,
– Unconditional call and return
– Eg. CALL 2035H, RET 2030H
Branch Instruction
Nested Procedure Calls
 Types of Operand
1. Addresses:
 immediate,
 direct,
 indirect,…
2. Numbers: integer or fixed point (binary, twos
complement), floating point (sign, significand,
exponent),
3. Characters: ASCII (128 printable and control
characters + bit for error detection)
4. Logical Data: bits or flags, e.g., Boolean 0 and 1
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 Data types
Most programming languages support common data
types of real, integer and boolean.
x86 Data Types
 8 bit Byte
 16 bit word
 32 bit double word
 64 bit quad word
 128 bit double quadword
 Addressing is by 8 bit unit
 Data accessed across 32 bit bus in units of double word
read at addresses divisible by 4
 Little endian
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 Instruction formats
o Instruction format describes the internal
structures (layout design) of the bits of an
instruction, in terms of its constituent parts.
o An Instruction format must include an
 opcode, and
 address
o Note: Address is dependent on an
availability of particular operands.

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 Cont…
 On the basis of number of address instruction are
classified as:
o Three-address
o Two-address
o One-address
o Zero-address
1. Zero Address Instructions
 Zero-address instructions are applicable to a special
memory organization, called a stack.
 A stack based computer do not use address field in
instruction.
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 Cont…
2. One Address Instructions
 This use a implied ACCUMULATOR register for
data manipulation.
 One operand is in accumulator and other is in
register or memory location.
 Implied means that the CPU already know that
one operand is in accumulator so there is no need
to specify it.

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 Cont…
3. Two Address Instructions
 This is common in commercial computers.
 Here two address can be specified in the
instruction.
 Unlike earlier in one address instruction the result
was stored in accumulator here result cab be
stored at different location rather than just
accumulator, but require more number of bit to
represent address.

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 Cont…
4. Three Address Instructions
 This has three address field to specify a register or
a memory location.
 Program created are much short in size but
number of bits per instruction increase.

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 PROCESSOR ORGANIZATION
• To understand the organization of the processor, let us consider the
requirements placed on the processor, the things that it must do:
o Fetch instruction: The processor reads an instruction from
memory (register, cache, main memory).
o Interpret instruction: The instruction is decoded to determine
what action is required.
o Fetch data: The execution of an instruction may require reading
data from memory or an I/O module.
o Process data: The execution of an instruction may require
performing some arithmetic or logical operation on data.
o Write data: The results of an execution may require writing
data to memory or an I/O module.
• To do these things, it should be clear that the processor needs to
store some data temporarily
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• Figure below shows a simplified view of a processor, indicating its
connection to the rest of the system via the system bus.
• The major components of the processor are an arithmetic and logic
unit (ALU) and a control unit (CU).
• The ALU does the actual computation or processing of data.

• The control unit controls the movement of data and instructions

into and out of the processor and controls the operation of the ALU.
• In addition, the figure shows a minimal internal memory, consisting
of a set of storage locations, called registers. 37
o Figure below shows a slightly more detailed view of the processor.
o The data transfer and logic control paths are indicated, including an
element labeled internal processor bus.
o This element is needed to transfer data between the various
registers and the ALU because the ALU in fact operates only on
data in the internal processor memory.

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 INSTRUCTION PIPELINING

• Processors make use of instruction pipelining to speed up

execution.
• Instruction pipelining is a technique used in the design of
modern microprocessors, microcontrollers and CPUs to
increase their instruction throughput (the number of
instructions that can be executed in a unit of time).

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Cont…
• pipelining involves breaking up the instruction cycle into a
number of separate stages that occur in sequence, such as
– fetch instruction,
– decode instruction,
– calculate operand addresses,
– fetch operands,
– execute instruction, and
– write operand result
• Each stage can be working on a different instruction at the
same time.
• The occurrence of branches and dependencies between
instructions complicates the design and use of pipelines.
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 • The pipeline has two independent stages.
– The first stage fetches an instruction
and buffers it.
– When the second stage is free, the first
stage passes it the buffered
instruction.
– While the second stage is executing
the instruction, the first stage takes
advantage of any unused memory
cycles to fetch and buffer the next
instruction.
• This is called instruction pre-fetch or
fetch overlap.
• Note: this approach, which involves
instruction buffering, requires more
registers. In general, pipelining requires
Two-Stage Instruction Pipe registers to store data between stages.
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 Figure shows that a six-stage pipeline can reduce the
execution time for 9 instructions from 54 time units to 14 time
units.

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• Several comments are in order: The diagram assumes that each
instruction goes through all six stages of the pipeline. This will not
always be the case.
• For example, a load instruction does not need the WO stage. However,
to simplify the pipeline hardware, the timing is set up assuming that
each instruction requires all six stages. Also, the diagram assumes that
all of the stages can be performed in parallel.
• In particular, it is assumed that there are no memory conflicts. For
example, the FI, FO, and WO stages involve a memory access.
• The diagram implies that all these accesses can occur simultaneously.
Most memory systems will not permit that. However, the desired value
may be in cache, or the FO or WO stage may be null.
• Thus, much of the time, memory conflicts will not slow down the
pipeline.
• Several other factors serve to limit the performance enhancement. If the
six stages are not of equal duration, there will be some waiting involved
at various pipeline stages.
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 Another difficulty is the conditional branch instruction
 indicates the logic needed for pipelining to account for branches and
interrupts.

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Basic five-stage
pipeline in a RISC • The vertical axis is
machine successive instructions,
the horizontal axis is
time.
• So in the green
column, the earliest
instruction is in WB
stage, and the latest
instruction is
undergoing instruction
fetch.
 IF = Instruction Fetch,
 ID = Instruction Decode,
 EX = Execute,
 MEM = Memory access,
 WB = Register write back.
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Example:
A machine has shared a single-memory
pipeline for data and instructions. As a
result, when an instruction contains a
data-memory reference(load), it will
conflict with the instruction reference
for a later instruction (instr 3):

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Solution
 To resolve this, we stall the pipeline for one
clock cycle when a data-memory access
occurs. The effect of the stall is actually to
occupy the resources for that instruction slot.
The following figure shows how the stalls are
actually implemented.
The End of Chapter 2

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