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VLSI Verilog HDL

This document discusses VLSI system on chip design using Verilog HDL. It covers topics such as the VLSI design flow, introduction to Verilog HDL, design methodologies including top-down and bottom-up approaches, different levels of abstraction including gate level, data flow level and behavioral level. It also discusses tasks and functions in Verilog, how to call tasks and functions, and how to use real numbers in port connections using system functions.

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Bhumika Bisht
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52 views22 pages

VLSI Verilog HDL

This document discusses VLSI system on chip design using Verilog HDL. It covers topics such as the VLSI design flow, introduction to Verilog HDL, design methodologies including top-down and bottom-up approaches, different levels of abstraction including gate level, data flow level and behavioral level. It also discusses tasks and functions in Verilog, how to call tasks and functions, and how to use real numbers in port connections using system functions.

Uploaded by

Bhumika Bisht
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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SUBMITTED TO: SUBMITTED BY:

PROF. KULDEEP SINGH BHUMIKA BISHT


B.TECH (ECE)
180151529004
VLSI SoC Design using
Verilog HDL
Index

Why VLSI Design


VLSI Design Flow
Introduction to Verilog HDL
Design Block
Top Down Design
Bottom Down Design
Abstraction
Gate level Abstraction
Data flow level Abstraction
Behavioral level Abstraction
Tasks and Functions
Calling Tasks and Functions
Real number in port connections
Why VLSI Design??

1. VLSI industry designs silicon chips for Automotive, Consumer


Electronics, Medical, IOT, Artificial Intelligence etc.
2. Each silicon will have Millions/ Billions of transistor forming complex
logic circuits to achieve above devices functionally.
3. Latest Technology nodes are 14nm , 10nm, 7nm,5nm which signifies
the capacity of number of transistor logic that can be fabricated on chip 
4. Demand for the chips related to the rapidly growing use of AI will
contribute significantly to the industry’s overall growth.
VLSI Design Flow
Introduction to Verilog HDL

 Programming language
 Hardware Description Language
 Understand the Behavior of Hardware
 Its syntax are similar to C language
 Easy to Learn & Use
 The Verilog HDL is both a behavioral and structural language
 Verilog is case sensitive language
Design Block

Design Methodologies:

Two types of design methodologies


 Top Down Design
 Bottom Up Design

Inputs Design
Block
 In Top Down design methodology, we define the top level block and identify the sub-blocks
necessary to build the top level block. We further divide the sub-block until we come to the leaf
cells, which are the cells which cannot be divided.

Top level block

Sub block 1 Sub block 2 Sub block 3

Leaf Leaf Leaf Leaf Leaf Leaf


cell cell cell cell cell cell
Bottom Up Design

 In a Bottom Up design methodology, we first identify the building blocks, we build bigger
blocks using these building blocks. These cells are then used for high level block until we
build the top level block in the design.

Top level block

Sub block 1 Sub block 2 Sub block 3

Leaf Leaf Leaf Leaf Leaf Leaf


cell cell cell cell cell
cell
Example

 FOUR BIT ADDER (Ripple carry adder)

4 bit adder Ripple carry


adder

Full Full Full Full


adders adders adders adders

XOR, AND and OR XOR, AND OR XOR, AND OR XOR, AND or


gates gates gates gates
Abstraction
Gate Level Abstraction

 This is also known as structural level Abstraction.


 In this level the Design is described in terms of gates.
 It is very easy to design any circuit in Verilog if we have the structure.
 For large circuit its difficult to implement in gate level.
Data Flow level Abstraction

 The gate level approach is very well for small scale logic.
 With the increasing level of structure its difficult to model any design in terms of gates.
 So therefore we move to data flow level.
 With the help of Synthesis Tool we can convert data level code to Gate level code.
 All the Boolean function can be implemented using data flow level.
 Any data flow level can be expressed using continuous assignment.
 Expressions, operators, operands.
Continuous Assignment
Expression, Operators, Operands
Behavioral level Abstraction

 Modeling a circuit with logic gates and continuous assignments is quite complex.
 Behavioral level is the higher level of abstraction in which models can be defined as its
functional behavioral.
 Thus Behavioral procedural constructs are well suited to tackling problems such as
describing a microprocessor or implementing complex timing checks.
 Verilog behavioral models contain structural procedural statements that control the
simulation and manipulate variables of the data types previously described.
 These statements are contained within procedures.
Behavioral level Example
Tasks and Functions

 Tasks and Functions provide the ability to execute common procedures from
several different places in a description.
 They also provide a means of breaking up large procedures into smaller ones to
make it easier to read and debug the source description.
 Input, output, and in out argument values can be passes into and out of both tasks
and functions.
 The next section discuss the example of task.
Example of Task
Function Example
Calling a Task & Function
Real numbers in port connections

 The real data type cannot be directly connected to a port, but rather must be connected
indirectly.
 The system functions $realtobits and $bitstoreal are used for passing the bit patterns
across module ports.

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