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Gate-Level Analysis

Gate level logic simulation allows for: 1) Timing analysis of circuits composed of logic gates and nets 2) Monitoring switching activity of each node to determine frequency of switching and calculate capacitive power dissipation 3) Estimating internal power dissipation of logic gates by characterizing energy of different logic events and their frequency of occurrence

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Saiprasanth Kilaru
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303 views12 pages

Gate-Level Analysis

Gate level logic simulation allows for: 1) Timing analysis of circuits composed of logic gates and nets 2) Monitoring switching activity of each node to determine frequency of switching and calculate capacitive power dissipation 3) Estimating internal power dissipation of logic gates by characterizing energy of different logic events and their frequency of occurrence

Uploaded by

Saiprasanth Kilaru
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Session-10

Gate level logic simulation


• Simulation based gate level timing analysis has been a very mature technique in
today's VLSI design
• The component abstraction at this level is logic gates and nets
• The circuit consists of components having defined logic behavior at its input and
output such as NAND gates, latches and flip flops
• Gate level logic simulation software is one of the earliest CAD tools being
developed
• In present world, Gate level logic simulator can perform full chip simulation up
to several million gates
Basics of Gate level analysis

• Event driven logic simulation


– Eventsare zero-one logic switching of nets in a circuit at a
• particular simulation time point
• Cycle based simulators
• Gate level simulators
– Hardware acceleration
– Hardware emulation
• VHDL and verilog are two popular languages used to describe gate-
level design
Capacitive power estimation

• The major advantage of gate level power analysis is that


the P = C V2 f can be computed precisely
• In non logic abstraction such as SPICE, the notion of the
frequency of a node is not well defined because it has an
analog waveform that is potentially non-periodic and non-
digital
• In logic simulation, the switching activities of each node
can be monitored to determine its frequency
• The capacitive power dissipation of the circuit is

Pc a p  
net i
C iV 2
fi
T – Simulation time elapsed
where (1 ) C- Capacitance
ti – Counter variable
fi  ti /  2 T
Internal switching energy
• The Equation (1) computes the power dissipated due
to charging and discharging of node capacitance
• Switching activities are not accounted
• Short circuit power is also not captured
• The dynamic power dissipated inside the logic cell is
called internal power which consists of short circuit
power and charging and discharging of internal nodes
• Idea is to the “dynamic energy
simulate of the gatedissipation
events” with SPICE or other lower
level power simulation tools
• Switching from 1 to 0 or vice versa consumes
some amount of dynamic energy internally
Internal switching energy
• Computation of dynamic internal power uses the concept of logic
events
• Each gate has a pre-defined set of logic events in which a quantum
of energy is consumed for each event
• The energy value of each event can be computed with SPICE circuit
simulation
• The total dynamic internal power dissipation is given by

Pint    E g, ef g, e


gate g event e

Where E(g,e) is the energy of the event e of gate g obtained from


logic gate characterization
f(g,e) is the occurrence frequency of the event on the gate observed
from logic simulation
E(g,e) depends on process conditions, operating voltage,
temperature, output loading capacitance, input signal slopes etc
Internal switching energy
• For example a simple 4 transistor NAND gate has
four dynamic energy dissipation events as shown in
below Fig.

Dynamic events and static states of a 2-input CMOS NAND gate


Internal switching energy
• The first implementation has only four energy dissipation
events
• Second implementation has two additional events due to
switching of is internal nodes

Two different implementation of NAND gate result in


different dynamic energy dissipation events
Static state power
• A similar event characterization idea can also be used to
compute the static power dissipation of a logic gate
• Here, the power dissipation depends on the state of
the logic gate
• The total static power is

T  Tg, s
g state
Pstat  gate s P g, s

– P(g,s) is the static power dissipation of gate g at state s obtained


from characterization
– State duration T(g,s) is obtained from logic simulation
• It is the total time gate g stays at state s
Gate level capacitance estimation
• As discussed earlier, capacitance is the most important
attribute that affects the power dissipation of CMOS
circuits
• Capacitance also has a impact on delays and signal slopes
of logic gates
• Change gate delay may affect the switching
in of the circuit and influence power
characteristics
dissipation
• Short circuit current is affected by the input signal slopes
and output capacitance loading
• Thus, capacitance has a direct and indirect impact
on power analysis
• The accurate estimation of capacitance is important
for power analysis and optimization
Gate level capacitance estimation
• Two types of parasitic capacitance exist CMOS
in circuits:
– Device parasitic capacitance
– Wiring capacitance
• Parasitic capacitance of MOS devices is associated with
terminals
• The gate capacitance depends on the oxide thickness
of the gate that is process dependent
• Design dependent factors are
– Width, length and shape of the gate
• In general a larger transistor has more capacitance in all
its terminals
• The second source of parasitic capacitance is
wiring capacitance
– Depends on the layer, area and shape of the wire
Gate level power analysis
• The event driven gate level power simulation
is summarized as follows:
– Run logic simulation with a set of input vectors
– Monitor the toggle count for each net
– Obtain capacitive power dissipation Pcap
– Monitor the dynamic energy dissipation events of each
gate
– Obtain internal switching power dissipation Pint
– Monitor the static power dissipation states of
each gate
– Obtain static power dissipation P stat
– Sum up all power dissipation components

P = Pcap + Pint + P stat


Signal glitches - Gate level power analysis
• The major disadvantage of gate level analysis is that
signal glitches cannot be modeled precisely
• Signal glitches are inherently analog phenomena and the
simplified zero-one logic model in gate-level analysis
fails to capture their effects
• The presence of glitches is very sensitive to the signal and
gate delays of the circuit
• As glitches are significant source of
signal
dissipation inpower
some VLSI circuits, it cannot be ignored
• However, it is difficult for any analysis model above the
logic level to account for the signal glitches precisely

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