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Synchronous Lecture Notes Week 5 Tutorial - Updated 18-2-21

The document discusses VLSI defects and yield. It states that yield decreases exponentially with increasing die area and defect density. As an example, it calculates that at a defect density of 1.5 defects/cm^2 and a die size of 1.32 cm^2, the yield would be 13.8%. The document also discusses stuck-at faults in full adders, showing how different input patterns can detect faults at the sum and carry output nodes. Tables show which input patterns will detect faults at each node for both 0 and 1 values.

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51 views

Synchronous Lecture Notes Week 5 Tutorial - Updated 18-2-21

The document discusses VLSI defects and yield. It states that yield decreases exponentially with increasing die area and defect density. As an example, it calculates that at a defect density of 1.5 defects/cm^2 and a die size of 1.32 cm^2, the yield would be 13.8%. The document also discusses stuck-at faults in full adders, showing how different input patterns can detect faults at the sum and carry output nodes. Tables show which input patterns will detect faults at each node for both 0 and 1 values.

Uploaded by

Zulfiqar Ali
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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NHE2483 Digital Systems Integration

VLSI Defects and Yield


Unclustered defects Yield = e-AD

D = Defects/cm2
A = Area cm2:
Note: Area and defect values are related to cm2
Eg

• If D = 1.5/cm2,
IC dimensions 11mm x 12mm = 1.1 x1.2 = 1.32 cm2

Yield = e-(1.5*1.32) x100%


= 13.8%

1
Dr. P.J. Mather
NHE2483 Digital Systems Integration
A
P
Stuck-at-Fault Cout Full Adder B
Sout

If a node is expected to be at ‘1’, G

a s-a-t ‘0’ fault can only be X


Cout
detected, if the final output is the
inverse of what is expected. Cin

A B Cin P G X Cout
100
A B C P G x Cout %
s-0 s-1 s-0 s-1 s-0 s-1 s-0 s-1 s-0 s-1 s-0 s-1 s-0 s-1 s-a-t

0 0 0
0 0 0 0
  
0 0 1
0 0 0 0       
0 1 0
1 0 0 0
     
0 1 1 1 0 1 1
     
1 0 0
1 0 1
1 0 0 0
    
1 1 0
1 0 1 1
    
1 1 1
0 1 0 1
    
0 1 0 1
 
Dr. P.J. Mather
           2
NHE2483 Digital Systems Integration
A
P
Stuck-at-Fault Sout Full Adder B
Sout

If a node is expected to be at ‘1’, G


X
a s-a-t ‘0’ fault can only be Cout
detected, if the final output is the
inverse of what is expected. Cin

A B Cin P G X Sout
100
A B C P G x Sout %
s-0 s-1 s-0 s-1 s-0 s-1 s-0 s-1 s-0 s-1 s-0 s-1 s-0 s-1 s-a-t

0 0 0
0 0 0 0      
0 0 1
0 0 0 1
    
0 1 0
1 0 0 1    
0 1 1 1 0 1 0      
1
1
0
0
0
1
1 0 0 1      
1 1 0
1 0 1 0     
1 1 1
0 1 0 0     
0 1 0 1     
Dr. P.J. Mather
        3
NHE2483 Digital Systems Integration
A
P
Sout
B
Stuck-at-Fault Cout & Sout Full G
Adder X
Cout

Cin

A B Cin P G X Cout Sout


Sout

A B C P G x
Cout

100%
s-a-t
s-0 s-1 s-0 s-1 s-0 s-1 s-0 s-1 s-0 s-1 s-0 s-1 s-0 s-1 s-0 s-1

0 0 0
0 0 0 0 0
       
0 0 1
0 0 0 0 1       
0 1 0
1 0 0 0 1       
0 1 1
1 0 1 1 0 
  
   
1 0 0
1 0 0 0 1
      
1 0
1 0 1
1 0 1

  
     
1 1 0
0 1 0 1 0 
      
0 1 0 1 1
1 1 1        4
Dr. P.J. Mather              
NHE2483 Digital Systems Integration
Example Question
An Automatic Test Equipment (ATE) manufacturing test device is
used to test a section of a digital ASIC containing 30 input pins, 18
internal memory devices and 10,000 logic gates. The ASIC
contains no embedded Design For Test (DFT) structures. The ATE
costs £2 M plus 256 digital test pins costing £15 k, each with linear
depreciation over 4 years: annual operating and maintenance costs
are £0.5 M.
i) If the ATE is operated 24hrs a day for 330 days per year
estimate the cost per second of running the equipment.

ii) If the ATE equipment, used to test the ASIC is running at 100
MHz, calculate the time required and thus cost to test the above
ASIC using exhaustive functional or structural test techniques.

iii) Using appropriate diagrams, discuss the benefits of using


embedded DFT structures, on the above IC, to aid testing.
5
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Example Solution

i) Running time (s) = (sec/min) * (min/hr) * (hr/day) * days


= 60 * 60 * 24 * 330
= 28.512 x106s
Cost/year = (Capital cost)/year + operating cost per year
= (£2M + (256*15k))/4 + £0.5M
= 5.84M/4 + 0.5M = £ 1.96 M
  Running cost = Cost/year / Running time
= £1.96 M/28.512 M = 6.87p /sec
ii) Exhaustive functional test (EF) (sequential logic)
EF test = 2(inputs + FF) = 2(30 + 18)
= 2.81*1014 test vectors (corrected 18/2/21)
Structural test (S)
S test = 2*(number of nodes)
= 2*(inputs + logic element)
Dr. P.J. Mather
= 2*(30 + 18 + 10000) = 20096 test vectors 6
NHE2483 Digital Systems Integration

Example Solution - Continued


ATE test equipment running at 100 MHz
• EF time to test = (time per test vector) * (EF number of test)
= 1/(100*106) * 2.81*1014
= 2.81*106 s
• EF cost to test = (EF time to test) * (running cost/second )
= (2.81*106) * (0.0687)
= £ 193.05 k
• S time to test = (time per test vector) * (S number of test)
= 1/(100*106) * 20096
= 0.2 ms
• S cost to test =
(S time to test) * (running cost per
= second )
0.2*10-3 s * (0.0687) = fraction of a penny
iii) refer to slide on Design For Test (8. Test Lecture notes)
7
Dr. P.J. Mather

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