NHE2483 Digital Systems Integration

Finite State Machine Design

• Finite State Machines (FSMs): A sequential circuit with n variables
has a finite number of states 2n – Simple FSM : counter.
• FSM Design – for given input/s, design a sequential circuit that will
step through internal states so that when the correct input
sequence is identified, the appropriate output will be generated.

Inputs Logic Outputs

0 0 1 0 1 0
Combinational logic structure
Present Next needs to be determined - Outputs
State State and next state conditions

M Memory element (D-type)

E
M
O
need to determine the
R
Y number of given the number
clk of states
Dr. P.J. Mather
NHE2483 Digital Systems Integration

FSM Design Process: Develop State Transition Diagram

Symbol Function Comment/s
RESET
• Start in a Reset state
OP = 0 • Flow to a state after a Decision box (unless
State point 2 Decision box)
n
IP= 1
• Generally, the output condition = 0, unless
y Output the specified sequence has been detected

First
• Does the input signal equal the value
specified Binary decision - ‘yes’ or ‘no’
Yes – generally flows forward (down)
No – generally flows back (to the side and
Wait Decision up)
• If a Wait operation is specified or there is a
requirement to transition to the next state
OP = 0 on the next clock, then no ‘Decision’ box is
required.
State x
Flow • Flow between diagram function boxes
2
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Develop State Transition Diagram

a) Start the diagram with a State box, followed by a flow

arrow to an output (e.g op = 0)
• Initial start State often named ‘reset’.

b) From the output, flow into the first input binary

decision box.

•
Typically, if the input is equal to the specified condition
(yes) the flow is vertical (down) to the next state.
• If the result of the decision box is false/no then the flow
arrow returns to the initial/previous State box.
c) Continue the process for each following state and repeat
until the full state transition diagram has been created.

3
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Developing FSM Circuit Design

Step 1: Develop State Transition Table

a) List all the states (under Present State) as named in the

State transition diagram.
b) Using the State transition diagram determine the flow from
each present state to the next state given the relevant
input conditions.
c) List the output condition for
each state. Next state
Present
input = 0 input =1 Output
State

4
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Step 2: Determine number of FFs and perform State assignment

a) Each state is represented by the combination of the respective

FF outputs (Q).
• Number of possible states = 2n 3 Flip Flops A, B, C gives 23
• where n is the number of flip-flops. possible states
b) List all the named states Number QA QB QC
of states
2 Flip Flops A, B gives 22
possible states
1 0 0 0
QA DA Number QA QB 2 0 0 1
of states
3 0 1 0
1 0 0 4 0 1 1
QB DB
2 0 1 5 1 0 0
3 1 0 6 1 0 1
clk 4 1 1 7 1 1 0
8 1 1 1
5
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Step 2: Determine number of FFs and perform State assignment

(cont)
c) Assign a state condition against each
state.
For consecutive states try to use Gray
codes, as only one FF output changes

state between states. State Assignment

This can reduce the possibility
of the output generating erroneous State codes
‘glitches’. Reset 000
First 001
Second 011
Third 010
Detected 110 6
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Step 3: State Assignment Table

a) Take the state transition table and replace all the states with
the assigned state values as determined in Step 2.

Next state
Present
X= 0 X=1 Output
State

000 0
001 0
011 0
010 0
100 0
101 0
111 0
110 1

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Dr. P.J. Mather
NHE2483 Digital Systems Integration

Determine the Logic structure

IP OP
Logic

Present Next Combinational Logic

State Q1 D1 State Develop K-Maps from
State Assignment Chart
Q0 D0
Generic –EPROM or
Multiplexer (MUX)
clk

Dr. P.J. Mather

NHE2483 Digital Systems Integration

Step 4: Combinational Logic - Karnaugh Mapping

Present Next State Next State

State IP = 0 IP= 1 OP Q1,Q0
(Q1,Q0) (D1,D0) (D1,D0) D1
00 01 11 10
00 0
IP
01 1

10
D1 =
11

Q1,Q0 Q1,Q0
D0 OP
00 01 11 10 00 01 11 10

0 0
IP IP
1 1

D0 = OP =
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Step 5. Combinational Logic based FSM Circuit Structure

OP
IP

Present Next
State State
Q1 D1

Q0 D0

Dr. P.J. Mather clk

NHE2483 Digital Systems Integration

Step 4 Generic – implement using either EPROM or Multiplexer

(MUX) Next state
Present
if not specified. State input = 0 input =1 Output

Present State Next state

IP QA QB Q C DA DB DC Output
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1 Step 4:
0
0
1
1
1
1
0
1
Rearrange State Assignment
1 0 0 0 Table into a truthtable format.
1 0 0 1 Input/s and present state
1 0 1 0
1 0 1 1 represent address/select lines.
1 1 0 0 Next states and Output/s
1 1 0 1
1 1 1 0
represent data/outputs
1 1 1 1
11
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Step 5. Generic Hardware Implementation (Note the EPROM and MUX

implementation are for different examples)

0 000 1 0 0 0 MUX
EPROM 0 001 1 0 0 0 0
0

OP
1 8:1
0 010 1 0 1 0 0
0 MUX
0 011 1 1 1 0 0
1
OP
IP 0 100 1 0 1 0 0

0
0 101 1 0 1 0 1
0
1 8:1
A 0 110 1 0 0 D0
0
1
MUX
D
D 0 111 1 0 0 0 1
1
0
R
E 1 000 0 0 1 0
S
S
1 001 0 1 0 0 0
1
0
1 010 1 1 0 0 D1 0 8:1
0 MUX
1 011 0 1 1 0 0
1

1 100 1 0 0 0 0

1 101 1 1 1 0
1 110 0 0 1 1 Present
1 111 1 1 0 0 State Next
Present QA DA
OP Q1 D1
State
State IP
QB DB

Next Q0 D0
QC DC
State clk
12
clk
Dr. P.J. Mather
NHE2483 Digital Systems Integration

‘One-Hot’ Coding Implementation (steps 1& 2)

Step 1: Number of FFs

a) Using the State Transition Diagram (STD) determine the
number of FFs required - equal to the number of states in the
STD.
Step 2: State equations
a) Develop the Boolean equation for the States.
b) For each state determine all the possible paths
into it, giving the state and the input.

N N IP
IP’ IP = 0
IP = 1

Y Y
IP IP’

13
Dr. P.J. Mather
NHE2483 Digital Systems Integration

‘One-Hot’ Coding Implementation (step 3)

Step 3: Develop the circuit diagram

a) Arrange each FF (one per state) in sequence.
b) In order to set up the initial ‘one-hot’ code connect a reset input
to the ‘preset’ asynchronous input of the reset state FF, and to
the ‘clear’ of all the other FFs.
c) Use the equations developed in Step 2 to form the logic required
between the FFs

10 10 1
0
IP logic Pre
logic logic
D Q D Q D Q

CLK CLK CLK

A B C

Clr Clr
Rst

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Dr. P.J. Mather
NHE2483 Digital Systems Integration

‘One-Hot’ Coding Implementation (example)

Step 1 4 states = 4 FF
RESET (A) Step 2
OP = 0 RESET(A) = A.DET’ + D.DET’
n
= (A + D).DET’
DET = 1
y
Count1 (B)
COUNT1(B) = A.DET + D.DET + B.DET’
OP = 0 = (A + D).DET + B.DET’
n
DET=1
y
Count2 (C)
COUNT2(C) = B.DET + C.DET’
OP = 0

n
DET-=1
y
Count3 (D)
COUNT3(D) = C.DET
OP = 1

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Dr. P.J. Mather
NHE2483 Digital Systems Integration

Step 3: Develop the circuit diagram

IP RST
COUNTER

Pre
OP

CLK CLK CLK CLK

A B C D
Clr Clr Clr

Dr. P.J. Mather

NHE2483 Digital Systems Integration

Multiple FSM: Implementation

Schematic Block Diagram
“DETECTER” “COUNTER”
1 0 0 1 0 1 0 1 0 1 0 0 1 0 1

IP Detects 101 and Counts 3 input OP

outputs a single pulses then outputs
pulse a pulse

Next
State
Present
Q1 D 1 Next Q1 D 1
State State Present
State

Q0 D 0 Q0 D 0

clk

4 States 4 States
2 Flip-Flops 2 Flip-Flops
Dr. P.J. Mather
NHE2483 Digital Systems Integration

5. Finite State Machine Design

Answering Exam/ICT and SAIL Questions
Circuit Design Process

Multi stage Develop State Transition Diagram

Block diagram
Boolean Logic implementation
This will not be specified at this level of the course.
Synchronous
Finite State
Machine
Generic – implement using either EPROM or
(FSM)
Multiplexer (MUX) if not specified.

Assume a
single design
if ‘multi stage’ 1 Hot Coding
is not
specified
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Dr. P.J. Mather
NHE2483 Digital Systems Integration

5. Finite State Machine Design

Answering Exam/ICT and SAIL Questions
Circuit Design Process
Develop State Transition 1. Develop State
Diagram Transition Table

2. Determine number of
Generic – implement FFs and perform
using either EPROM or State assignment Develop Waveform
Multiplexer (MUX) if not the circuit Analysis
specified 3. State Assignment Table design

4. Rearrange into
truthtable format

1 Hot Coding Develop logic functions

directly from flow diagram
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Dr. P.J. Mather
NHE2483 Digital Systems Integration

Example Examination question : Generic FSM design

Design a synchronous sequential circuit with one input (A) and one
output (Z). The machine produces an output Z=1 only whenever
one of the following input sequences occur 1101, 0011. Sequences
may start at any time, so avoid designing the flow diagram so that
sequences are recognized only if they line up on some multiple of
four clock periods. The circuit resets to its initial state after Z=1 has
been generated.
A) Implement the circuit using an appropriate number of
multiplexers and flip-flops.
B) Implement the circuit using an appropriate sized EPROM and
flip-flops.
NOTE the register representation 0 0 1 1
is used to show the valid parts of an input sequence (blue or green for the two
separate sequences). Where part of the input no longer forms part of a valid
sequence it is shown with a orange background
20
Dr. P.J. Mather
NHE2483 Digital Systems Integration
Reset
Develop State Transition Diagram
1 1 0 1 Z=0 0 0 1 1
y n
X=1
1 0
S1_1 S2_1

Z=0
1 0
n
X=1
1 1 y
S1_2

21
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Example Examination question : ‘One-Hot’ Coding FSM design

Design a ‘One-Hot Code’ based Finite State Machine

(FSM) circuit, that outputs a pulse (OP), of one clock cycle,
after it has detected a single occurrence of 101100 on an
input signal (IP) (the Most Significant Bit is the first input
bit). The FSM then immediately resets and recommences
monitoring for the next valid input sequence.

101100

22
Dr. P.J. Mather
NHE2483 Digital Systems Integration
‘One-Hot’ Coding Implementation: Develop State
Transition Diagram
Reset

OP = 0 Valid sequence 101100

0
n
IP=1
1 y

23
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Pipelining: Digital System

The process of dividing long propagation circuit delay paths into
shorted operations and placing registers in between in order to
enable higher clock speeds.

Unpipelined Circuit
Time taken for each stage to perform an operation

2 ns 3 ns 1 ns 2 ns 2 ns Data O/P
Data I/P

Latency = (longest Critical Path(CP) propagation delay)

= 10ns
Maximum clock speed = 1/CP = 1/10ns
= 100 MHz
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Pipelined Circuit: Digital System

2 ns 3 ns 1 ns 2 ns 2 ns
Data I/P Data O/P Pipelined version.
A new computation
clk can be launched
every (longest circuit
Data I/P
block delay) in
pipelined structure.
2 ns 3 ns 1 ns 2 ns 2 ns
Clock speed
= 1/(stage delay)
3 ns 3 ns 3 ns 3 ns = 1/3ns
= 333 MHz

Latency
= stage delay*stages
‘Pipeline registers’ D-type flip-flop break up = 3ns * 4
computation into stages = 12ns

Dr. P.J. Mather

NHE2483 Digital Systems Integration

Guide to Answering
6. Pipelining of Digital Systems
Based Exam Questions
Latency: Time taken for output to
respond for a given input )equal to
Develop a circuit
the overall maximum propagation
block diagram - Non- delay) (critical path - CP).
generally a polynomial pipelined Maximum clock frequency =
function will be
(1/T) where T : Max propagation
specified.
delay (CP)
6. Pipelining
of Digital
Systems Latency: Time taken for output to
Pipelined respond for a given input -
equal to the stage delay (max.
block delay) * number of stages
Restrictions and
Maximum clock frequency =
Hazards when
Next 2 (1/T) where T equal to the block
pipelining a circuit.
slides with the highest propagation delay

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Dr. P.J. Mather
NHE2483 Digital Systems Integration

Pipelining Restrictions

Restrictions to the • Some computations won’t divide

number of Pipeline into smaller logical
stage implementations.
• Pipeline registers
Typically • Increased silicon area
• Stages pipes per requirements
IC: 10-20 • Associated propagation delay
• Number of logic • Set-Up and Hold time (S/H)
gates in a single requirement:
pipeline stage: 10- o Time for input to be stable
20 before read – clock edge
•Control issues

27
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Pipelined Circuit Stage Timings

tclk = clock period – duration of one clock pulse.

tS/H = Set-up hold time required before next clock edge
(clock input for flip-flop)
Propagation delay from clock transition to
output response

tclk

Operating time of logic circuit tS/H

Input data Logic circuitry needs to have completed

change all operations – final output condition for
the given input data
Dr. P.J. Mather
NHE2483 Digital Systems Integration

Pipelining Hazards
Data Hazards
Hazards Instruction depends on result of prior
Complex systems computation which is not ready yet
due to concurrent stage operations
generally incorporate
feedback, thus
complications can Structural Hazards
When two or more instructions want
occur in the form of to use the same hardware resource
hazards in the same cycle.
Overcome by replicating hardware
resources.
• Data
• Structural
• Control Control Hazards
Pipelining of non-sequential branch
operations and other instructions
which change the Program Count
(PC)
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Dr. P.J. Mather
NHE2483 Digital Systems Integration

Pipelining of a Circuit Structure – unpiplined circuit

Step 1: F= a2 +7ac -b
Develop the un-pipelined circuit for a 7 c b
given function.
X X
Note: divide into functional blocks,
where each part of a function requires a
separate operational block (e.g a X + - F
multiplier, adder etc).
In example - X = 3ns 3 ns 3 ns 1 ns 1 ns

+ Latency = 8 ns
- = 1ns
Clock speed = 1/8 ns = 125 MHz

Step 2: Determine the longest signal propagation delay (critical path) from input
to output.
Critical path propagation delay is termed the Latency (un-pipelined circuit)
Maximum operation frequency is determined by 1/longest delay.
Note: If the circuit was clocked at a faster rate, then data samples would be
mixed, producing a non-valid output.
Dr. P. J. Mather
3030
NHE2483 Digital Systems Integration

Step 3: Pipelining of a Circuit Structure –pipelined circuit

• Determine the block/function with the
maximum operation/propagation delay F= a2 +7ac -b
time. clk
• This becomes the time window
between registers. b
• Example – max propagation delay
= multiplier 3ns. c 7
X X
Step 4:
• Place a register after each function
block, unless multiple functions can a X + -
operate within the given time window.
• In the example Add and Subtract – 3 ns 3 ns 3 ns
both = 1ns (no register required
between them) Latency = 3 x 3ns = 9ns
• Ensure there is an equal number of Clock speed =1/3 ns = 333 MHz
registers are placed in each signal path
so the correct sample instances are = n-bit D-types
used. (Register)
Dr. P. J. Mather
31
NHE2483 Digital Systems Integration

clk D4 D7
Waveform representation b
of a Pipelined Circuit c
D3
7
D2 D6
X X

D1 D5
a X + - F

3 ns 3 ns 3 ns
Time(ns)
0 3 6 9 12 15 18
IP a0b0c0 a1b1c1 a2b2c2 a3b3c3 a4b4c4 a5b5c5

Outputs
D1 0 a 02 a 12 a22 a32 a42
D2 0 7a0 7a1 7a2 7a3 7a4
D3 0 c0 c1 c2 c3 c4
D4 0 b0 b1 b2 b3 b4
D5 0 0 a 02 a12 a22 a32
D6 0 0 7a 0c0 7a1c1 7a2c2 7a3c3
D7 0 0 b0 b1 b2 b3
F 0 0 0 a02+7a0c0-b0 a12+7a1c1-b1 a22+7a2c2-b2 32
Dr. P. J. Mather
NHE2483 Digital Systems Integration

Computer Architectures
Stage 1 Stage 2 Stage 3 Stage 4 Stage 5
Instruction Fetch Register - Decode ALU Data Memory Register Write
Back
IF REG(R) ALU DM REG(W)
Current PC Adder
Adder

4 Instruction Memory M
(RAM)
PC U
<<2 X

Read Reg 1
Data Memory
Read (RAM)
Data 1
Zero
Read Reg 2

Write Reg
ALUSrc M
0010101110001011 M Read
U
Data 2
U Write Data M X
1100111000000010 X U
ALU
X
ADD R16,R0,R1
SUB R20,R21,R22 32
16
Sign Extend

Dr. P. J. Mather
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NHE2483 Digital Systems Integration

Computer Instructions - Un-pipelined

Instruction Fetch (IF) = 0.2 ns
Register – Decode- Read (Reg (R)) = 0.1 ns
Arithmetic Logic Unit (ALU) = 0.2 ns
Data Memory (DM) = 0.2 ns
Register Write (Reg(W)) = 0.1 ns

Instructions 3.2 ns to complete 4 instructions

IF REG(R) ALU DM REG(W)
1
IF REG(R) ALU DM REG(W)

2 0.8 ns
IF REG(R) ALU DM REG(W)

3 IF REG(R) ALU DM REG(W)

New instruction completed every 0.8 ns : latency = 0.8 ns

Clock frequency =1.25 GHz 34
Dr. P. J. Mather
NHE2483 Digital Systems Integration

Computer Instructions - Pipelined

Instructions 1.6 ns to complete 4 instructions

IF REG(R) ALU DM REG(W)
1

2
IF REG(R) ALU DM REG(W)

4 IF REG(R) ALU DM REG(W)

IF REG(R) ALU DM REG(W)

New instruction completed every 1.0 ns : latency = 1.0 ns

Clock frequency = 1/ 0.2 ns = 5 GHz
Dr. P. J. Mather
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NHE2483 Digital Systems Integration

Instruction Interference:
After 3 successive instruction functions the first instruction READS register file and the
fourth instruction WRITES to the register file (.
Time
Program Clock
execution Cycle 1 2 3 4 5 6 7 8 9
Reg

SUB R17,R0,R0 REG ALU

W
IF (R) DM R17

ADD R16,R0,R0 REG ALU REG

IF (R) DM (W)

SUB R20,R21,R22 REG ALU REG

IF (R) DM (W)

Reg
ADD R30,R17,R18
R ALU REG
IF R17 DM (W)

 Solution: since the write and read operations take less than half the maximum
block delay both can be performed in the same clock period
 Allow WRITE-then-READ in one clock cycle (termed “double pump”).

Dr. P. J. Mather
36
NHE2483 Digital Systems Integration

Instruction Interference: Removed

Time
Program Clock
execution Cycle 1 2 3 4 5 6 7 8 9

REG ALU REG

ADD R10,R11,R12 IF (R) DM (W)
Reg
SUB R17,R0,R0 REG ALU W
IF (R) DM R17

ADD R16,R0,R0 REG ALU REG

IF (R) DM (W)

SUB R20,R21,R22 REG ALU REG

IF (R) DM (W)

Reg
ADD R30,R17,R18 R ALU REG
IF R17 DM (W)

Dr. P. J. Mather
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NHE2483 Digital Systems Integration

Instruction Conflict

Time
Program Clock
Cycle 1 2 3 4 5 6 7 8 9
execution

REG ALU REG

SUB R5,R6,R7 Writeback
IF (R) DM (W) Writebackresult
result
into
intoR10
R10
ADD R10,R11,R12
REG ALU W
IF (R) DM R10

R ALU REG
ADD R12,R10,R11 IF R10 DM (W)

Read
ReadValue
Value
out
outof
of R10
R10

 The 2nd instruction needs to read the contents of register R10 before the first
instruction has written the result of an instruction into R10.
 Name for this: NO Operation or Pipeline stall.
Dr. P. J. Mather
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NHE2483 Digital Systems Integration

Resolving Instruction Conflict

Time
Program
Clock
execution Cycle 1 2 3 4 5 6 7

REG ALU
W
ADD R10,R11,R12 IF (R) DM R10

ADD R12,R10,R11 R ALU REG

IF R10 DM (W)

ADD R11,R10,R12 R ALU

IF R10 DM

Empty slots in the pipe called “bubbles” or NOP; means no real

instruction work getting saved here

Dr. P. J. Mather
39