Synchronous Lecture Notes Week 2
Synchronous Lecture Notes Week 2
VHDL Coding
VHDL Structure – a VHDL programme has the three following
sections
Libraries
• Libraries
• Entity Entity
• Architecture
A A
P S SOUT OUT
B
B
G
X
COUT
COUT
CIN Cin
Architecture
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Dr. P.J. Mather
NHE2483 Digital Systems Integration
ENTITY name1 IS
GENERIC (name; type, size/value);
PORT (define port name, type and size);
END name1;
ARCHITECTURE level of abstraction OF name1 IS
SIGNAL -- (define internal signal names, type and size, also a default start-up
value can
be specified)
BEGIN
-- Any functions/operations outside of the process will update as soon as signals
inside the Process change state/value
-- multiple Processes can be specified within one Entity.
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Dr. P.J. Mather
NHE2483 Digital Systems Integration
BEGIN
WAIT UNTIL (clk'EVENT AND clk = '1’); -- for sequential logic
-- Note if a sensitivity list isn’t specified then a WAIT UNTIL is required.
-- Use or sequential logic – as the Process will not operate Until the WAIT
-- requirements have been met – in this case positive edge triggered on -- ‘clk’
input.
ENTITY Section
ENTITY Code1 IS
ENTITY name Code1
PORT Defined the (Ports) input and
outputs signals
(clk: IN BIT;
Inputs clk, res single bit
x : IN BIT_VECTOR(4 DOWNTO 0); x input : 5 bit vector
y input : 3 bit vector
y : IN BIT_VECTOR(2 DOWNTO 0);
z output: 8 bit vector
z : OUT BIT_VECTOR(7 DOWNTO 0));
END Code1;
clk clk
5 bit vector 8 bit vector
x x4-0 z7-0
3 bit vector z
y y2-0
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Dr. P.J. Mather
NHE2483 Digital Systems Integration
Generic Code
Generic code that can be modified to accommodate different sizes of input and
output vectors as well as Signal vectors
Set up the Generic parameters in the Entity section before the PORT definition.
ENTITY Code2 IS
GENERIC (n1: natural := 4 -- different values can be specified
n2: natural := 7);
PORT (clk : IN STD_LOGIC;
x : IN BIT_VECTOR(n1-1 DOWNTO 0);
y : OUT BIT_VECTOR(n2-1 DOWNTO 0); );
END Code2 ;
GENERIC – this enables parameters
(n1 and n2) to be set to a value. Can clk clk 7 bit vector
then be used to define the size of the
ENTITY input and outputs as well as y6-0
4 bit vector
the internal registers (signals). x x3-0 y
x input : 4 bit vector (n1 = 4)
y output : 7 bit vector (n2 = 7)
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Dr. P.J. Mather
NHE2483 Digital Systems Integration
Dx- Signal register is a 3 bit vector with the initial default value of
‘000’ . As all the bits are to be the same (other => ‘0’) can be used
A default value isn’t necessarily set at this stage – a reset input can
be used to reset the internal signals to a known state.
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Dr. P.J. Mather
NHE2483 Digital Systems Integration
Writing the 3 bits of the SIPO register into the ‘errorcode’ register.
Note : if the bit locations are not specified for ‘errorcode’ then the
full register is taken and will need to be 3 bits, else an error
message will be displayed when compiling the code.
errorcode <= SIPO(6 downto 4);
Process section
Multiple Processes can be specified within one Entity.
Note; all Processes start with BEGIN and require a ‘END Process’
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Dr. P.J. Mather
NHE2483 Digital Systems Integration
PROCESS
BEGIN
WAIT UNTIL (res = '1' OR (clk'EVENT AND clk = ‘0'));
Process – followed by a WAIT UNTIL statement.
This shows that the process will only operate on a negative ‘clk’
transition (EVENT means there is a transition and clk=‘0’ means
the final value is zero. Thus –ve edge transition on ‘clk’ or ‘res’=1.
This is effectively a synchronous (clocked) process. 11
Dr. P.J. Mather
NHE2483 Digital Systems Integration
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Dr. P.J. Mather
NHE2483 Digital Systems Integration
CASE (errorcode) IS
WHEN "001" => dout <= (sipo(3 downto 0)) XOR ("1101");
WHEN "011" => dout <= (sipo(3 downto 0)) XOR ("1010");
WHEN "111" => dout <= (sipo(3 downto 0)) XOR ("0100 ");
WHEN "110" => dout <= (sipo(3 downto 0)) XOR ("1000");
WHEN OTHERS => dout <= sipo(3 downto 0);
END CASE;
Accum + x
X y
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Dr. P.J. Mather
NHE2483 Digital Systems Integration
z
Dx2
XOR
function Dx3
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Dr. P.J. Mather
NHE2483 Digital Systems Integration