1

Chap. 1: Digital Logic Circuits

• Logic Gates, • Boolean Algebra

• Map Simplification, • Combinational Circuits
• Filp-Flops, • Sequential Circuits

Chap. 2: Digital Components

• Integrated Circuits, • Decoders, • Multiplexers

• Registers, • Shift Registers, • Binary Counters
• Memory Unit

Chap. 3: Data Representation

• Data Types, • Complements

• Fixed Point Representation
• Floating Point Representation
• Other Binary Codes, • Error Detection Codes

Computer Organization Computer Architecture

 2

Chap. 4: Register Transfer and Microoperations

• Register Transfer Language, • Register Transfer

• Bus and Memory Transfers
• Arithmetic Microoperations
• Logic Microoperations, • Shift Microoperations
• Arithmetic Logic Shift Unit

Chap. 5: Basic Computer Organization and Design

• Instruction Codes, • Computer Registers

• Computer Instructions, • Timing and Control
• Instruction Cycle,
• Memory Reference Instructions
• Input-Output and Interrupt
• Complete Computer Description
• Design of Basic Computer
• Design of Accumulator Logic
Computer Organization Computer Architecture
 3

Chap. 6: Programming the Basic Computer

• Machine Language, • Assembly Language

• Assembler, • Program Loops
• Programming Arithmetic and Logic Operations
• Subroutines, • Input-Output Programming

Chap. 7: Microprogrammed Control

• Control Memory, • Sequencing Microinstructions

• Microprogram Example, • Design of Control Unit
• Microinstruction Format

Chap. 8: Central Processing Unit

• General Register Organization

• Stack Organization, • Instruction Formats
• Addressing Modes
• Data Transfer and Manipulation
• Program Control
• Reduced Instruction Set Computer
Computer Organization Computer Architecture
 4

Chap. 9: Pipeline and Vector Processing

• Parallel Processing, • Pipelining

• Arithmetic Pipeline, • Instruction Pipeline
• RISC Pipeline, • Vector Processing

Chap. 10: Computer Arithmetic

• Arithmetic with Signed-2's Complement Numbers

• Multiplication and Division Algorithms
• Floating-Point Arithmetic Operations
• Decimal Arithmetic Unit
• Decimal Arithmetic Operations

Chap. 11: Input-Output Organization

• Peripheral Devices, • Input-Output Interface

• Asynchronous Data Transfer, • Modes of Transfer
• Priority Interrupt, • Direct Memory Access

Computer Organization Computer Architecture

 5

Chap. 12: Memory Organization

• Memory Hierarchy, • Main Memory

• Auxiliary Memory. • Associative Memory
• Cache Memory, • Virtual Memory

Chap. 13: Multiprocessors ()

• Characteristics of Multiprocessors
• Interconnection Structures
• Interprocessor Arbitration
• Interprocessor Communication/Synchronization
• Cache Coherence

Computer Organization Computer Architecture

Register Transfer & -operations 6

SIMPLE DIGITAL SYSTEMS

• Combinational and sequential circuits (learned in Chapters 1 and 2)

can be used to create simple digital systems.

• These are the low-level building blocks of a digital computer.

• Simple digital systems are frequently characterized in terms of

– the registers they contain, and
– the operations that they perform.

• Typically,
– What operations are performed on the data in the registers
– What information is passed between registers

Computer Organization Computer Architecture

Register Transfer & -operations 7

REGISTER TRANSFER AND

MICROOPERATIONS

• Register Transfer Language

• Register Transfer

• Bus and Memory Transfers

• Arithmetic Microoperations

• Logic Microoperations

• Shift Microoperations

• Arithmetic Logic Shift Unit

Computer Organization Computer Architecture

Register Transfer & -operations 8 Register Transfer Language

MICROOPERATIONS (1)

• The operations on the data in registers are called

microoperations.
• The functions built into registers are examples of
microoperations
– Shift
– Load
– Clear
– Increment
– …

Computer Organization Computer Architecture

Register Transfer & -operations 9 Register Transfer Language

MICROOPERATION (2)

An elementary operation performed (during

one clock pulse), on the information stored
in one or more registers

Registers ALU 1 clock cycle

(R) (f)

R  f(R, R)
f: shift, load, clear, increment, add, subtract, complement,
and, or, xor, …
Computer Organization Computer Architecture
Register Transfer & -operations 10 Register Transfer Language

ORGANIZATION OF A DIGITAL SYSTEM

• Definition of the (internal) organization of a computer

- Set of registers and their functions

- Microoperations set

Set of allowable microoperations provided

by the organization of the computer

- Control signals that initiate the sequence of

microoperations (to perform the functions)

Computer Organization Computer Architecture

Register Transfer & -operations 11 Register Transfer Language

REGISTER TRANSFER LEVEL

• Viewing a computer, or any digital system, in this way

is called the register transfer level

• This is because we’re focusing on

– The system’s registers
– The data transformations in them, and
– The data transfers between them.

Computer Organization Computer Architecture

Register Transfer & -operations 12 Register Transfer Language

REGISTER TRANSFER LANGUAGE

• Rather than specifying a digital system in words, a specific

notation is used, register transfer language

• For any function of the computer, the register transfer

language can be used to describe the (sequence of)
microoperations

• Register transfer language

– A symbolic language
– A convenient tool for describing the internal organization of digital
computers
– Can also be used to facilitate the design process of digital systems.

Computer Organization Computer Architecture

Register Transfer & -operations 13 Register Transfer Language

DESIGNATION OF REGISTERS

• Registers are designated by capital letters, sometimes

followed by numbers (e.g., A, R13, IR)
• Often the names indicate function:
– MAR - memory address register
– PC - program counter
– IR - instruction register

• Registers and their contents can be viewed and represented in

various ways
– A register can be viewed as a single entity:

MAR

– Registers may also be represented showing the bits of data they contain

Computer Organization Computer Architecture

Register Transfer & -operations 14 Register Transfer Language

DESIGNATION OF REGISTERS
• Designation of a register
- a register
- portion of a register
- a bit of a register

• Common ways of drawing the block diagram of a register

Register Showing individual bits

R1 7 6 5 4 3 2 1 0

15 0 15 8 7 0
R2 PC(H) PC(L)
Numbering of bits Subfields

Computer Organization Computer Architecture

Register Transfer & -operations 15 Register Transfer

REGISTER TRANSFER

• Copying the contents of one register to another is a register

transfer

• A register transfer is indicated as

R2  R1

– In this case the contents of register R2 are copied (loaded) into

register R1
– A simultaneous transfer of all bits from the source R1 to the
destination register R2, during one clock pulse
– Note that this is a non-destructive; i.e. the contents of R1 are not
altered by copying (loading) them to R2

Computer Organization Computer Architecture

Register Transfer & -operations 16 Register Transfer

REGISTER TRANSFER

• A register transfer such as

R3  R5

Implies that the digital system has

– the data lines from the source register (R5) to the destination
register (R3)
– Parallel load in the destination register (R3)
– Control lines to perform the action

Computer Organization Computer Architecture

Register Transfer & -operations 17 Register Transfer

CONTROL FUNCTIONS
• Often actions need to only occur if a certain condition is true
• This is similar to an “if” statement in a programming language
• In digital systems, this is often done via a control signal, called
a control function
– If the signal is 1, the action takes place
• This is represented as:

P: R2  R1

Which means “if P = 1, then load the contents of register R1 into

register R2”, i.e., if (P = 1) then (R2  R1)

Computer Organization Computer Architecture

Register Transfer & -operations 18 Register Transfer

HARDWARE IMPLEMENTATION OF CONTROLLED TRANSFERS

Implementation of controlled transfer

P: R2 R1

Block diagram Control P Load

R2 Clock
Circuit
n
R1

t t+1
Timing diagram
Clock

Load
Transfer occurs here

• The same clock controls the circuits that generate the control function
and the destination register
• Registers are assumed to use positive-edge-triggered flip-flops

Computer Organization Computer Architecture

Register Transfer & -operations 19 Register Transfer

SIMULTANEOUS OPERATIONS

• If two or more operations are to occur

simultaneously, they are separated with commas

P: R3  R5, MAR  IR

• Here, if the control function P = 1, load the contents

of R5 into R3, and at the same time (clock), load the
contents of register IR into register MAR

Computer Organization Computer Architecture

Register Transfer & -operations 20 Register Transfer

BASIC SYMBOLS FOR REGISTER TRANSFERS

Symbols Description Examples

Capital letters Denotes a register MAR, R2
& numerals
Parentheses () Denotes a part of a register R2(0-7), R2(L)
Arrow  Denotes transfer of information R2 R1
Colon : Denotes termination of control function P:
Comma , Separates two micro-operations A B, B A

Computer Organization Computer Architecture

Register Transfer & -operations 21 Register Transfer

CONNECTING REGISTRS

• In a digital system with many registers, it is impractical to

have data and control lines to directly allow each register
to be loaded with the contents of every possible other
registers

• To completely connect n registers  n(n-1) lines

• O(n2)
– This is not a realistic approach to use in a large digital system

• Instead, take a different approach

• Have one centralized set of circuits for data transfer – the
bus
• Have control circuits to select which register is the
source, and which is the destination

Computer Organization Computer Architecture

Register Transfer & -operations 22 Bus and Memory Transfers

BUS AND BUS TRANSFER

Bus is a path(of a group of wires) over which information is
transferred, from any of several sources to any of several destinations.
From a register to bus: BUS  R
Register A Register B Register C Register D

Bus lines

Register A Register B Register C Register D

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4

B1 C1 D 1 B2 C2 D 2 B3 C3 D 3 B4 C 4 D 4

0 0 0 0
4 x1 4 x1 4 x1 4 x1
MUX MUX MUX MUX

x
select
y

4-line bus

Computer Organization Computer Architecture

 23

BUS SYSTEM FOR FOUR REGISTERS

Computer Organization Computer Architecture

 24

FUNCTION TABLE FOR BUS

When the bus is includes in the statement, the register transfer is

symbolized as follows:

Computer Organization Computer Architecture

Register Transfer & -operations 25 Bus and Memory Transfers

TRANSFER FROM BUS TO A DESTINATION REGISTER

Bus lines

Load
Reg. R0 Reg. R1 Reg. R2 Reg. R3

D 0 D1 D2 D 3
z E (enable)
Select 2x4
w
Decoder

Three-State Bus Buffers

Computer Organization Computer Architecture

 26

BUS LINE WITH THREE STATE-BUFFERS

Computer Organization Computer Architecture

Register Transfer & -operations 27 Bus and Memory Transfers

BUS TRANSFER IN RTL

• Depending on whether the bus is to be mentioned

explicitly or not, register transfer can be indicated as
either
R2 R1
or
BUS R1, R2  BUS

• In the former case the bus is implicit, but in the latter, it is

explicitly indicated

Computer Organization Computer Architecture

Register Transfer & -operations 28 Bus and Memory Transfers

MEMORY (RAM)
• Memory (RAM) can be thought as a sequential circuits
containing some number of registers
• These registers hold the words of memory
• Each of the r registers is indicated by an address
• These addresses range from 0 to r-1
• Each register (word) can hold n bits of data
• Assume the RAM contains r = 2k words. It needs the
following
– n data input lines data input lines
– n data output lines
n
– k address lines
– A Read control line address lines
– A Write control line k
RAM
Read
unit
Write
n
data output lines

Computer Organization Computer Architecture

Register Transfer & -operations 29 Bus and Memory Transfers

MEMORY TRANSFER
• Collectively, the memory is viewed at the register level as
a device, M.
• Since it contains multiple locations, we must specify
which address in memory we will be using
• This is done by indexing memory references

• Memory is usually accessed in computer systems by

putting the desired address in a special register, the
Memory Address Register (MAR, or AR)
• When memory is accessed, the contents of the MAR get
sent to the memory unit’s address lines

M
Memory Read
AR
unit Write

Data out Data in

Computer Organization Computer Architecture

 30

MEMORY TRANSFER

This causes a transfer of information into DR from the

memory word M selected by the address in AR .

Write : M[AR] R1

This causes a transfer of information from R1 into the

memory word M selected by the address in AR .

Computer Organization Computer Architecture

Register Transfer & -operations 31 Bus and Memory Transfers

MEMORY READ
• To read a value from a location in memory and load it into a
register, the register transfer language notation looks like this:

R1  M[MAR]

• This causes the following to occur

– The contents of the MAR get sent to the memory address lines
– A Read (= 1) gets sent to the memory unit
– The contents of the specified address are put on the memory’s
output data lines
– These get sent over the bus to be loaded into register R1

Computer Organization Computer Architecture

Register Transfer & -operations 32 Bus and Memory Transfers

MEMORY WRITE
• To write a value from a register to a location in memory looks like this
in register transfer language:

M[MAR]  R1

• This causes the following to occur

– The contents of the MAR get sent to the memory address lines
– A Write (= 1) gets sent to the memory unit
– The values in register R1 get sent over the bus to the data input
lines of the memory
– The values get loaded into the specified address in the memory

Computer Organization Computer Architecture

Register Transfer & -operations 33 Bus and Memory Transfers

SUMMARY OF R. TRANSFER MICROOPERATIONS

A B Transfer content of reg. B into reg. A

AR DR(AD) Transfer content of AD portion of reg. DR into reg. AR
A  constant Transfer a binary constant into reg. A
ABUS R1, Transfer content of R1 into bus A and, at the same time,
R2 ABUS transfer content of bus A into R2
AR Address register
DR Data register
M[R] Memory word specified by reg. R
M Equivalent to M[AR]
DR  M Memory read operation: transfers content of
memory word specified by AR into DR
M  DR Memory write operation: transfers content of
DR into memory word specified by AR

Computer Organization Computer Architecture

Register Transfer & -operations 34 Arithmetic Microoperations

MICROOPERATIONS

• Computer system microoperations are of four types:

- Register transfer microoperations

- Arithmetic microoperations
- Logic microoperations
- Shift microoperations

Computer Organization Computer Architecture

Register Transfer & -operations 35 Arithmetic Microoperations

ARITHMETIC MICROOPERATIONS
• The basic arithmetic microoperations are
– Addition
– Subtraction
– Increment
– Decrement

• The additional arithmetic microoperations are

– Add with carry
– Subtract with borrow
– Transfer/Load
– etc. …

Summary of Typical Arithmetic Micro-Operations

R3  R1 + R2 Contents of R1 plus R2 transferred to R3
R3  R1 - R2 Contents of R1 minus R2 transferred to R3
R2  R2’ Complement the contents of R2
R2  R2’+ 1 2's complement the contents of R2 (negate)
R3  R1 + R2’+ 1 subtraction
R1  R1 + 1 Increment
R1  R1 - 1 Decrement

Computer Organization Computer Architecture

 36

4-Bit Binary Adder

Computer Organization Computer Architecture

 37

• Above Figure shows the interconnections of four

full-adders (FA) to provide a 4-bit binary adder.
 The augend bits of A and the addend bits of B are
designated by subscript numbers from right to left, with
subscript 0 denoting the low-order bit.
 The carries are connected in a chain through the full-
adders.
 The input carry to the binary adder is C0 and the output
carry is C4.
 The S outputs of the full-adders generate the required
sum bits.

Computer Organization Computer Architecture

 38

4-Bit adder-subtractor

Computer Organization Computer Architecture

 39

 A 4-bit adder-subtractor circuit is shown in above Fig. The

mode input M controls the operation.
 When M = 0 the circuit is an adder and when M = 1 the
circuit becomes a subtractor.
 Each exclusive-OR gate receives input M and one of the
inputs of B.
 When M = 0, we have B ⊕ 0 = B. The full-adders receive the
value of B, the input carry is O, and the circuit performs A
plus B .
 When M = 1, we have B ⊕ 1 = B' and C0 = 1. The B inputs
are all complemented and a 1 is added through the input
carry.
 The circuit performs the operation A plus the 2's
complement of B.

Computer Organization Computer Architecture

Register Transfer & -operations 40 Arithmetic Microoperations

BINARY ADDER / SUBTRACTOR / INCREMENTER

B3 A3 B2 A2 B1 A1 B0 A0
Binary Adder
FA C3 FA C2 FA C1 FA C0

C4 S3 S2 S1 S0

Binary Adder-Subtractor
B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1 C0
FA FA FA FA

C4 S3 S2 S1 S0

Binary Incrementer
A3 A2 A1 A0 1

x y x y x y x y
HA HA HA HA
C S C S C S C S

C4 S3 S2 S1 S0

Computer Organization Computer Architecture

Register Transfer & -operations 41 Arithmetic Microoperations

ARITHMETIC CIRCUIT
Cin
S1
S0
A0 X0 C0
S1 D0
S0 FA
B0 0 4x1 Y0 C1
1 MUX
2
3
A1 X1 C1
S1 FA D1
S0
B1 0 4x1 Y1 C2
1 MUX
2
3
A2 X2 C2
S1 FA D2
S0
B2 0 4x1 Y2 C3
1 MUX
2
3
A3 X3 C3
S1 D3
S0 FA
B3 0 4x1 Y3 C4
1 MUX
2
3 Cout
0 1

S1 S0 Cin Y Output Microoperation

0 0 0 B D=A+B Add
0 0 1 B D=A+B+1 Add with carry
0 1 0 B’ D = A + B’ Subtract with borrow
0 1 1 B’ D = A + B’+ 1 Subtract
1 0 0 0 D=A Transfer A
1 0 1 0 D=A+1 Increment A
1 1 0 1 D=A-1 Decrement A
1 1 1 1 D=A Transfer A
Computer Organization Computer Architecture
Register Transfer & -operations 42 Logic Microoperations

LOGIC MICROOPERATIONS
• Specify binary operations on the strings of bits in registers
– Logic microoperations are bit-wise operations, i.e., they work on the
individual bits of data
– useful for bit manipulations on binary data
– useful for making logical decisions based on the bit value
• There are, in principle, 16 different logic functions that can
be defined over two binary input variables
A B F0 F1 F2 … F13 F14 F15
0 0 0 0 0 … 1 1 1
0 1 0 0 0 … 1 1 1
1 0 0 0 1 … 0 1 1
1 1 0 1 0 … 1 0 1

• However, most systems only implement four of these

– AND (), OR (), XOR (), Complement/NOT
• The others can be created from combination of these

Computer Organization Computer Architecture

Register Transfer & -operations 43 Logic Microoperations

LIST OF LOGIC MICROOPERATIONS

• List of Logic Microoperations
- 16 different logic operations with 2 binary vars.
n
- n binary vars → 2 2 functions

• Truth tables for 16 functions of 2 variables and the

corresponding 16 logic micro-operations
x 0011 Boolean Micro-
Name
y 0101 Function Operations
0000 F0 = 0 F0 Clear
0001 F1 = xy FAB AND
0010 F2 = xy' F  A  B’
0011 F3 = x FA Transfer A
0100 F4 = x'y F  A’ B
0101 F5 = y FB Transfer B
0110 F6 = x  y FAB Exclusive-OR
0111 F7 = x + y FAB OR
1000 F8 = (x + y)' F  A  B)’ NOR
1001 F9 = (x  y)' F  (A  B)’ Exclusive-NOR
1010 F10 = y' F  B’ Complement B
1011 F11 = x + y' FAB
1100 F12 = x' F  A’ Complement A
1101 F13 = x' + y F  A’ B
1110 F14 = (xy)' F  (A  B)’ NAND
1111 F15 = 1 F  all 1's Set to all 1's

Computer Organization Computer Architecture

Register Transfer & -operations 44 Logic Microoperations

HARDWARE IMPLEMENTATION OF LOGIC MICROOPERATIONS

Ai
0
Bi

1
4X1 Fi
MUX
2

3 Select

S1
S0

Function table
S1 S0 Output -operation
0 0 F=AB AND
0 1 F = AB OR
1 0 F=AB XOR
1 1 F = A’ Complement

Computer Organization Computer Architecture

Register Transfer & -operations 45 Logic Microoperations

APPLICATIONS OF LOGIC MICROOPERATIONS

• Logic microoperations can be used to manipulate individual
bits or a portions of a word in a register

• Consider the data in a register A. In another register, B, is bit

data that will be used to modify the contents of A

– Selective-set AA+B
– Selective-complement AAB
– Selective-clear A  A • B’
– Mask (Delete) AA•B
– Clear AAB
– Insert A  (A • B) + C
– Compare AAB
– ...

Computer Organization Computer Architecture

Register Transfer & -operations 46 Logic Microoperations

SELECTIVE SET

• In a selective set operation, the bit pattern in B is used to set

certain bits in A

1100 At
1010 B
1110 At+1 (A  A + B)

• If a bit in B is set to 1, that same position in A gets set to 1,

otherwise that bit in A keeps its previous value

Computer Organization Computer Architecture

Register Transfer & -operations 47 Logic Microoperations

SELECTIVE COMPLEMENT

• In a selective complement operation, the bit pattern in B is

used to complement certain bits in A

1100 At
1010 B
0110 At+1 (A  A  B)

• If a bit in B is set to 1, that same position in A gets

complemented from its original value, otherwise it is
unchanged

Computer Organization Computer Architecture

Register Transfer & -operations 48 Logic Microoperations

SELECTIVE CLEAR

• In a selective clear operation, the bit pattern in B is used to

clear certain bits in A

1100 At
1010 B
0100 At+1 (A  A  B’)

• If a bit in B is set to 1, that same position in A gets set to 0,

otherwise it is unchanged

Computer Organization Computer Architecture

Register Transfer & -operations 49 Logic Microoperations

MASK OPERATION

• In a mask operation, the bit pattern in B is used to clear

certain bits in A

1100 At
1010 B
1000 At+1 (A  A  B)

• If a bit in B is set to 0, that same position in A gets set to 0,

otherwise it is unchanged

Computer Organization Computer Architecture

Register Transfer & -operations 50 Logic Microoperations

CLEAR OPERATION

• In a clear operation, if the bits in the same position in A and

B are the same, they are cleared in A, otherwise they are set
in A

1100 At
1010 B
0110 At+1 (A  A  B)

Computer Organization Computer Architecture

Register Transfer & -operations 51 Logic Microoperations

INSERT OPERATION
• An insert operation is used to introduce a specific bit pattern
into A register, leaving the other bit positions unchanged
• This is done as
– A mask operation to clear the desired bit positions, followed by
– An OR operation to introduce the new bits into the desired
positions
– Example
» Suppose you wanted to introduce 1010 into the low order
four bits of A: 1101 1000 1011 0001 A (Original)
1101 1000 1011 1010 A (Desired)

» 1101 1000 1011 0001 A (Original)

1111 1111 1111 0000 Mask
1101 1000 1011 0000 A (Intermediate)
0000 0000 0000 1010 Added bits
1101 1000 1011 1010 A (Desired)

Computer Organization Computer Architecture

Register Transfer & -operations 52 Shift Microoperations

SHIFT MICROOPERATIONS
• There are three types of shifts
– Logical shift
– Circular shift
– Arithmetic shift
• What differentiates them is the information that goes into
the serial input

• A right shift operation

Serial
input

• A left shift operation Serial

input

Computer Organization Computer Architecture

Register Transfer & -operations 53 Shift Microoperations

LOGICAL SHIFT
• In a logical shift the serial input to the shift is a 0.

• A right logical shift operation:

0

• A left logical shift operation:

0

• In a Register Transfer Language, the following notation is used

– shl for a logical shift left
– shr for a logical shift right
– Examples:
» R2  shr R2
» R3  shl R3
Computer Organization Computer Architecture
Register Transfer & -operations 54 Shift Microoperations

CIRCULAR SHIFT
• In a circular shift the serial input is the bit that is shifted out
of the other end of the register.

• A right circular shift operation:

• A left circular shift operation:

• In a RTL, the following notation is used

– cil for a circular shift left
– cir for a circular shift right
– Examples:
» R2  cir R2
» R3  cil R3
Computer Organization Computer Architecture
Register Transfer & -operations 55 Shift Microoperations

ARITHMETIC SHIFT
• An arithmetic shift is meant for signed binary numbers
(integer)
• An arithmetic left shift multiplies a signed number by two
• An arithmetic right shift divides a signed number by two
• The main distinction of an arithmetic shift is that it must keep
the sign of the number the same as it performs the
multiplication or division

• A right arithmetic shift operation:

sign
bit

• A left arithmetic shift operation:

0
sign
bit

Computer Organization Computer Architecture

Register Transfer & -operations 56 Shift Microoperations

ARITHMETIC SHIFT
• An left arithmetic shift operation must be checked for the
overflow
0
sign
bit

Before the shift, if the leftmost two

V bits differ, the shift will result in an
overflow

• In a RTL, the following notation is used

– ashl for an arithmetic shift left
– ashr for an arithmetic shift right
– Examples:
» R2  ashr R2
» R3  ashl R3

Computer Organization Computer Architecture

Register Transfer & -operations 57 Shift Microoperations

HARDWARE IMPLEMENTATION OF SHIFT MICROOPERATIONS

0 for shift right (down)

Serial Select 1 for shift left (up)
input (IR)

S
MUX H0
0
1
A0

A1 S
MUX H1
0
A2 1

A3
S
MUX H2
0
1

S
MUX H3
0
1

Serial
input (IL)

Computer Organization Computer Architecture

 58

4-Bit Combinational circuit shifter

Computer Organization Computer Architecture

 59

Function Table

Computer Organization Computer Architecture

Register Transfer & -operations 60 Shift Microoperations

ARITHMETIC LOGIC SHIFT UNIT

S3
S2 Ci
S1
S0

Arithmetic D i
Circuit
Select

Ci+1
0 4x1 Fi
1 MUX
2
3
Ei
Logic
Bi
Ai
Circuit
Ai-1 shr
Ai+1 shl

S3 S2 S1 S0 Cin Operation Function

0 0 0 0 0 F=A Transfer A
0 0 0 0 1 F=A+1 Increment A
0 0 0 1 0 F=A+B Addition
0 0 0 1 1 F=A+B+1 Add with carry
0 0 1 0 0 F = A + B’ Subtract with borrow
0 0 1 0 1 F = A + B’+ 1 Subtraction
0 0 1 1 0 F=A-1 Decrement A
0 0 1 1 1 F=A TransferA
0 1 0 0 X F=AB AND
0 1 0 1 X F = A B OR
0 1 1 0 X F=AB XOR
0 1 1 1 X F = A’ Complement A
1 0 X X X F = shr A Shift right A into F
1 1 X X X F = shl A Shift left A into F

Computer Organization Computer Architecture

Basic Computer Organization & Design 61

Instruction set architecture of a CPU

• Computer Registers

• Instruction Execution Cycle

• RTL representation of Instructions

• Addressing modes

• Instruction set

• Outlining instruction sets of some common CPUs

Computer Organization Computer Architecture

Basic Computer Organization & Design 62

INTRODUCTION
• Every different processor type has its own design (different
registers, buses, microoperations, machine instructions, etc)
• Modern processor is a very complex device
• It contains
– Many registers
– Multiple arithmetic units, for both integer and floating point calculations
– The ability to pipeline several consecutive instructions to speed execution
– Etc.
• However, to understand how processors work, we will start with
a simplified processor model
• This is similar to what real processors were like ~25 years ago
• M. Morris Mano introduces a simple processor model he calls
the Basic Computer
• We will use this to introduce processor organization and the
relationship of the RTL model to the higher level computer
processor

Computer Organization Computer Architecture

Basic Computer Organization & Design 63

THE BASIC COMPUTER

• The Basic Computer has two components, a processor and

memory
• The memory has 4096 words in it
– 4096 = 212, so it takes 12 bits to select a word in memory
• Each word is 16 bits long

CPU RAM
0

15 0

4095

Computer Organization Computer Architecture

Basic Computer Organization & Design 64 Instruction codes

INSTRUCTION
S
• Program
– A sequence of (machine) instructions
• (Machine) Instruction
– A group of bits that tell the computer to perform a specific operation
(a sequence of micro-operation)
• The instructions of a program, along with any needed data
are stored in memory
• The CPU reads the next instruction from memory
• It is placed in an Instruction Register (IR)
• Control circuitry in control unit then translates the
instruction into the sequence of microoperations
necessary to implement it

Computer Organization Computer Architecture

Basic Computer Organization & Design 65 Instruction codes

INSTRUCTION
FORMAT
• A computer instruction is often divided into two parts
– An opcode (Operation Code) that specifies the operation for that
instruction
– An address that specifies the registers and/or locations in memory to
use for that operation
• In the Basic Computer, since the memory contains 4096 (=
212) words, we needs 12 bit to specify which memory
address this instruction will use
• In the Basic Computer, bit 15 of the instruction specifies
the addressing mode (0: direct addressing, 1: indirect
addressing)
• Since the memory words, and hence the instructions, are
16 bits long, that leaves 3 bits for the instruction’s opcode

Instruction Format
15 14 12 11 0
I Opcode Address

Addressing
mode

Computer Organization Computer Architecture

Basic Computer Organization & Design 66 Instruction codes

ADDRESSING
• MODES
The address field of an instruction can represent either
– Direct address: the address in memory of the data to use (the address of the
operand), or
– Indirect address: the address in memory of the address in memory of the data to use

Direct addressing Indirect addressing

22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand

1350 Operand

+ +
AC AC

• Effective Address (EA)

– The address, that can be directly used without modification to access an operand for
a computation-type instruction, or as the target address for a branch-type instruction

Computer Organization Computer Architecture

Basic Computer Organization & Design 67 Instruction codes

PROCESSOR
REGISTERS
• A processor has many registers to hold instructions,
addresses, data, etc
• The processor has a register, the Program Counter (PC) that
holds the memory address of the next instruction to get
– Since the memory in the Basic Computer only has 4096 locations, the PC
only needs 12 bits
• In a direct or indirect addressing, the processor needs to keep
track of what locations in memory it is addressing: The
Address Register (AR) is used for this
– The AR is a 12 bit register in the Basic Computer
• When an operand is found, using either direct or indirect
addressing, it is placed in the Data Register (DR). The
processor then uses this value as data for its operation
• The Basic Computer has a single general purpose register –
the Accumulator (AC)

Computer Organization Computer Architecture

Basic Computer Organization & Design 68 Instruction codes

PROCESSOR
REGISTERS
• The significance of a general purpose register is that it can be
referred to in instructions
– e.g. load AC with the contents of a specific memory location; store the
contents of AC into a specified memory location
• Often a processor will need a scratch register to store
intermediate results or other temporary data; in the Basic
Computer this is the Temporary Register (TR)
• The Basic Computer uses a very simple model of input/output
(I/O) operations
– Input devices are considered to send 8 bits of character data to the processor
– The processor can send 8 bits of character data to output devices
• The Input Register (INPR) holds an 8 bit character gotten from an
input device
• The Output Register (OUTR) holds an 8 bit character to be send
to an output device

Computer Organization Computer Architecture

Basic Computer Organization & Design 69 Registers

BASIC COMPUTER
REGISTERS
Registers in the Basic Computer
11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
Computer Organization Computer Architecture
Basic Computer Organization & Design 70 Registers

COMMON BUS
SYSTEM

• The registers in the Basic Computer are connected using a

bus
• This gives a savings in circuitry over complete
connections between registers

Computer Organization Computer Architecture

Basic Computer Organization & Design 71 Registers

COMMON BUS
SYSTEM S2
S1
S0
Bus

Memory unit 7
4096 x 16
Address
Write Read

AR 1

LD INR CLR

PC 2

LD INR CLR

DR 3

LD INR CLR

E
ALU AC 4

LD INR CLR

INPR
IR 5

LD
TR 6

LD INR CLR

OUTR Clock
LD
16-bit common bus

Computer Organization Computer Architecture

Basic Computer Organization & Design 72 Registers

COMMON BUS
SYSTEM
Read
INPR
Memory Write
4096 x 16

Address E ALU

AC

L I C

L I C L

L I C DR IR L I C

PC TR

AR OUTR LD

L I C

7 1 2 3 4 5 6

16-bit Common Bus

S0 S1 S2

Computer Organization Computer Architecture

Basic Computer Organization & Design 73 Registers

COMMON BUS
SYSTEM
• Three control lines, S2, S1, and S0 control which register the
bus selects as its input
S2 S1 S0 Register
0 0 0 x
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory

• Either one of the registers will have its load signal

activated, or the memory will have its read signal activated
– Will determine where the data from the bus gets loaded
• The 12-bit registers, AR and PC, have 0’s loaded onto the
bus in the high order 4 bit positions
• When the 8-bit register OUTR is loaded from the bus, the
data comes from the low order 8 bits on the bus

Computer Organization Computer Architecture

Basic Computer Organization & Design 74 Instructions

BASIC COMPUTER
INSTRUCTIONS
• Basic Computer Instruction Format

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation

Computer Organization Computer Architecture

Basic Computer Organization & Design 75 Instructions

BASIC COMPUTER
Symbol
Hex Code
I=0 I=1
INSTRUCTIONS
Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off

Computer Organization Computer Architecture

Basic Computer Organization & Design 76 Instructions

INSTRUCTION SET
COMPLETENESS
A computer should have a set of instructions so that the user can
construct machine language programs to evaluate any function
that is known to be computable.

• Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory
and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT

Computer Organization Computer Architecture

Basic Computer Organization & Design 77 Instruction codes

CONTROL
UNIT
• Control unit (CU) of a processor translates from machine
instructions to the control signals for the microoperations
that implement them

• Control units are implemented in one of two ways

• Hardwired Control
– CU is made up of sequential and combinational circuits to generate the
control signals
• Microprogrammed Control
– A control memory on the processor contains microprograms that
activate the necessary control signals

• We will consider a hardwired implementation of the control

unit for the Basic Computer

Computer Organization Computer Architecture

Basic Computer Organization & Design 78 Timing and control

TIMING AND
CONTROL
Control unit of Basic Computer
Instruction register (IR)
15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I Combinational
D7 Control Control
logic signals

T 15

T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock

Computer Organization Computer Architecture

Basic Computer Organization & Design 79 Timing and control

TIMING
- Generated by 4-bit sequenceSIGNALS
counter and 416 decoder
- The SC can be incremented or cleared.

- Example: T0, T1, T2, T3, T4, T0, T1, . . .

Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC  0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

Computer Organization Computer Architecture

Basic Computer Organization & Design 80

INSTRUCTION CYCLE

• In Basic Computer, a machine instruction is executed in the

following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an
indirect address
4. Execute the instruction

• After an instruction is executed, the cycle starts again at

step 1, for the next instruction

• Note: Every different processor has its own (different)

instruction cycle

Computer Organization Computer Architecture

Basic Computer Organization & Design 81 Instruction Cycle

FETCH and
DECODE
• Fetch and Decode T0: AR PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)
T1
S2

T0 S1 Bus
S0

Memory 7
unit
Address
Read

AR 1

LD

PC 2

INR

IR 5

LD
Clock
Common bus

Computer Organization Computer Architecture

Basic Computer Organization & Design 82 Instrction Cycle

DETERMINE THE TYPE OF

INSTRUCTION Start
SC 

T0
AR  PC

T1
IR  M[AR], PC  PC + 1

T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7IT3: AR M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
Computer Organization Computer Architecture
Basic Computer Organization & Design 83 Instruction Cycle

REGISTER REFERENCE
INSTRUCTIONS
Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3

r = D7 IT3 => Register Reference Instruction

Bi = IR(i) , i=0,1,2,...,11
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
HLT rB0: S  0 (S is a start-stop flip-flop)
Computer Organization Computer Architecture
Basic Computer Organization & Design 84 MR Instructions

MEMORY REFERENCE
Symbol
Operation
INSTRUCTIONS
Symbolic Description
Decoder

AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1
- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4
AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E
Computer Organization Computer Architecture
Basic Computer Organization & Design 85

MEMORY REFERENCE INSTRUCTIONS

LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC  0
BUN: Branch Unconditionally
D4T4: PC  AR, SC  0
BSA: Branch and Save Return Address
M[AR]  PC, PC  AR + 1
Memory, PC, AR at time T4 Memory, PC after execution

20 0 BSA 135 20 0 BSA 135

PC = 21 Next instruction 21 Next instruction

AR = 135 135 21

136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

Memory Memory

Computer Organization Computer Architecture

Basic Computer Organization & Design 86 MR Instructions

MEMORY REFERENCE INSTRUCTIONS

BSA:
D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0

Computer Organization Computer Architecture

Basic Computer Organization & Design 87 MR Instructions

FLOWCHART FOR MEMORY REFERENCE

INSTRUCTIONS
Memory-reference instruction

AND ADD LDA STA

D T4 D1 T 4 D2 T 4 D 3T 4
0
DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0

D0 T 5 D1 T 5 D2 T 5

AC  AC DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D4 T 4 D5 T 4 D6 T 4

PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D5 T 5 D6 T 5

PC  AR DR  DR + 1
SC  0

D6 T 6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0

Computer Organization Computer Architecture

Basic Computer Organization & Design 88 I/O and Interrupt

INPUT-OUTPUT AND INTERRUPT

A Terminal with a keyboard and a Printer
• Input-Output Configuration
Serial Computer
Input-output communication
terminal registers and
interface flip-flops
Receiver
Printer interface OUTR FGO

AC

Transmitter
Keyboard interface INPR FGI
INPR Input register - 8 bits
OUTR Output register - 8 bits Serial Communications Path
FGI Input flag - 1 bit Parallel Communications Path
FGO Output flag - 1 bit
IEN Interrupt enable - 1 bit

- The terminal sends and receives serial information

- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the terminal
serially and with the AC in parallel.
- The flags are needed to synchronize the timing
difference between I/O device and the computer
Computer Organization Computer Architecture
Basic Computer Organization & Design 89 I/O and Interrupt

PROGRAM CONTROLLED DATA

-- CPU -- TRANSFER
-- I/O Device --
/* Input */ /* Initially FGI = 0 */ loop: If FGI = 1 goto loop
loop: If FGI = 0 goto loop
INPR  new data, FGI  1
AC  INPR, FGI  0

/* Output */ /* Initially FGO = 1 */ loop: If FGO = 1 goto loop

loop: If FGO = 0 goto loop consume OUTR, FGO  1
OUTR  AC, FGO  0

FGI=0 FGO=1
Start Input Start Output

FGI  0
AC  Data
yes yes
FGI=0
FGO=0
no
no
AC  INPR
OUTR  AC

yes More FGO  0

Character
yes More
no Character
END no
END
Computer Organization Computer Architecture
Basic Computer Organization & Design 90

INPUT-OUTPUT INSTRUCTIONS

D7IT3 = p
IR(i) = Bi, i = 6, …, 11

p: SC  0 Clear SC
INP pB11: AC(0-7)  INPR, FGI  0 Input char. to AC
OUT pB10: OUTR  AC(0-7), FGO  0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION pB7: IEN  1 Interrupt enable on
IOF pB6: IEN  0 Interrupt enable off

Computer Organization Computer Architecture

Basic Computer Organization & Design 91 I/O and Interrupt

PROGRAM-CONTROLLED
INPUT/OUTPUT
• Program-controlled I/O
- Continuous CPU involvement
I/O takes valuable CPU time
- CPU slowed down to I/O speed
- Simple
- Least hardware

Input

LOOP, SKI DEV

BUN LOOP
INP DEV

Output
LOOP, LDA DATA
LOP, SKO DEV
BUN LOP
OUT DEV

Computer Organization Computer Architecture

Basic Computer Organization & Design 92

INTERRUPT INITIATED INPUT/OUTPUT

- Open communication only when some data has to be passed --> interrupt.

- The I/O interface, instead of the CPU, monitors the I/O device.

- When the interface founds that the I/O device is ready for data transfer,
it generates an interrupt request to the CPU

- Upon detecting an interrupt, the CPU stops momentarily the task

it is doing, branches to the service routine to process the data
transfer, and then returns to the task it was performing.

* IEN (Interrupt-enable flip-flop)

- can be set and cleared by instructions

- when cleared, the computer cannot be interrupted

Computer Organization Computer Architecture

Basic Computer Organization & Design 93 I/O and Interrupt

FLOWCHART FOR INTERRUPT

CYCLE R = Interrupt f/f
Instruction cycle =0 =1 Interrupt cycle
R

Fetch and decode Store return address

instructions in location 0
M[0]  PC

Execute =0
IEN
instructions
=1 Branch to location 1
PC  1
=1
FGI
=0
=1 IEN  0
FGO R0
=0
R1

- The interrupt cycle is a HW implementation of a branch

and save return address operation.
- At the beginning of the next instruction cycle, the
instruction that is read from memory is in address 1.
- At memory address 1, the programmer must store a branch instruction
that sends the control to an interrupt service routine
- The instruction that returns the control to the original
program is "indirect BUN 0"

Computer Organization Computer Architecture

Basic Computer Organization & Design 94 I/O and Interrupt

REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE

Memory
Before interrupt After interrupt cycle

0 0 256
1 0 BUN 1120 PC = 1 0 BUN 1120

Main Main
255 Program 255 Program
PC = 256 256
1120 1120
I/O I/O
Program Program

1 BUN 0 1 BUN 0

Register Transfer Statements for Interrupt Cycle

- R F/F  1 if IEN (FGI + FGO)T0T1T2
 T0T1T2 (IEN)(FGI + FGO): R  1

- The fetch and decode phases of the instruction cycle

must be modified Replace T0, T1, T2 with R'T0, R'T1, R'T2
- The interrupt cycle :
RT0: AR  0, TR  PC
RT1: M[AR]  TR, PC  0
RT2: PC  PC + 1, IEN  0, R  0, SC  0
Computer Organization Computer Architecture
Basic Computer Organization & Design 95 I/O and Interrupt

FURTHER QUESTIONS ON INTERRUPT

How can the CPU recognize the device

requesting an interrupt ?

Since different devices are likely to require

different interrupt service routines, how can
the CPU obtain the starting address of the
appropriate routine in each case ?

Should any device be allowed to interrupt the

CPU while another interrupt is being serviced ?

How can the situation be handled when two or

more interrupt requests occur simultaneously ?

Computer Organization Computer Architecture

Basic Computer Organization & Design 96 Description
COMPLETE COMPUTER
DESCRIPTION
Flowchart
SC  0, IEN  0, R of
start
0 Operations
=0(Instruction =1(Interrupt
R
Cycle) Cycle)
R’T0 RT0
AR  PC AR  0, TR  PC
R’T1 RT1
IR  M[AR], PC  PC + 1 M[AR]  TR, PC  0
R’T2 RT2
AR  IR(0~11), I  IR(15) PC  PC + 1, IEN  0
D0...D7  Decode IR(12 ~ 14) R  0, SC  0

=1(Register or I/O) =0(Memory Ref)

D7

=1 (I/O) =0 (Register) =1(Indir) =0(Dir)

I I

D7IT3 D7I’T3 D7’IT3 D7’I’T3

Execute Execute AR <- M[AR] Idle
I/O RR
Instruction Instruction
Execute MR D7’T4
Instruction

Computer Organization Computer Architecture

Basic Computer Organization & Design 97 Description
COMPLETE COMPUTER DESCRIPTION
Microoperations
Fetch RT0: AR  PC
RT1: IR  M[AR], PC  PC + 1
Decode RT2: D0, ..., D7  Decode IR(12 ~ 14),
AR  IR(0 ~ 11), I  IR(15)
Indirect AR  M[AR]
D7IT3:
Interrupt
T0T1T2(IEN)(FGI + FGO): R 1
AR  0, TR  PC
RT0: M[AR]  TR, PC  0
RT1: PC  PC + 1, IEN  0, R  0, SC  0
Memory-ReferenceRT2:
AND DR  M[AR]
D0T4: AC  AC  DR, SC  0
ADD D0T5: DR  M[AR]
D1T4: AC  AC + DR, E  Cout, SC  0
LDA DR  M[AR]
D1T5:
AC  DR, SC  0
STA D2T4:
M[AR]  AC, SC  0
BUN D2T5: PC  AR, SC  0
BSA D3T4: M[AR]  PC, AR  AR + 1
D4T4: PC  AR, SC  0
ISZ D5T4: DR  M[AR]
D5T5: DR  DR + 1
D6T4: M[AR]  DR, if(DR=0) then (PC  PC + 1),
D6T5: SC  0
D6T6:

Computer Organization Computer Architecture

Basic Computer Organization & Design 98 Description
COMPLETE COMPUTER DESCRIPTION
Microoperations

Register-Reference
D7IT3 = r (Common to all register-reference instr)
IR(i) = Bi (i = 0,1,2, ..., 11)
r: SC  0
CLA AC  0
rB11:
CLE E0
CMA rB10:
AC  AC
CME rB9: E  E
CIR rB8: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB7: AC  shl AC, AC(0)  E, E  AC(15)
INC rB6: AC  AC + 1
SPA rB5: If(AC(15) =0) then (PC  PC + 1)
SNA rB4: If(AC(15) =1) then (PC  PC + 1)
SZA If(AC = 0) then (PC  PC + 1)
SZE rB3:
If(E=0) then (PC  PC + 1)
HLT rB2: S0
rB1:
Input-Output rB0: (Common to all input-output instructions)
(i = 6,7,8,9,10,11)
D7IT3 = p SC  0
INP IR(i) = Bi AC(0-7)  INPR, FGI  0
OUT p: OUTR  AC(0-7), FGO  0
SKI pB11: If(FGI=1) then (PC  PC + 1)
SKO If(FGO=1) then (PC  PC + 1)
ION pB10:
IEN  1
IOF pB9: IEN  0
pB8:
pB7:
pB6:
Computer Organization Computer Architecture
Basic Computer Organization & Design 99 Design of Basic Computer

DESIGN OF BASIC
Hardware Components ofCOMPUTER(BC)
BC
A memory unit: 4096 x 16.
Registers:
AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
Flip-Flops(Status):
I, S, E, R, IEN, FGI, and FGO
Decoders: a 3x8 Opcode decoder
a 4x16 timing decoder
Common bus: 16 bits
Control logic gates:
Adder and Logic circuit: Connected to AC

Control Logic Gates

- Input Controls of the nine registers
- Read and Write Controls of memory
- Set, Clear, or Complement Controls of the flip-flops
- S2, S1, S0 Controls to select a register for the bus
- AC, and Adder and Logic circuit

Computer Organization Computer Architecture

Basic Computer Organization & Design 100 Design of Basic Computer

CONTROL OF REGISTERS AND

Address Register; AR MEMORY
Scan all of the register transfer statements that change the content of AR:
R’T0: AR  PC LD(AR)
R’T2: AR  IR(0-11) LD(AR)
D’7IT3: AR  M[AR] LD(AR)
RT0: AR  0 CLR(AR)
D5T4: AR  AR + 1 INR(AR)

LD(AR) = R'T0 + R'T2 + D'7IT3

CLR(AR) = RT0
INR(AR) = D5T4
12 12
From bus AR To bus
D'
7
I
LD Clock
T3
T2 INR
CLR
R
T0
D
T4

Computer Organization Computer Architecture

Basic Computer Organization & Design 101 Design of Basic Computer

CONTROL OF
IEN: Interrupt Enable Flag
FLAGS
pB7: IEN  1 (I/O Instruction)
pB6: IEN  0 (I/O Instruction)
RT2: IEN  0 (Interrupt)

p = D7IT3 (Input/Output Instruction)

D
7
p
I
J Q IEN
B
7
T3

B6
K

R
T2

Computer Organization Computer Architecture

Basic Computer Organization & Design 102 Design of Basic Computer

CONTROL OF COMMON BUS

x1
x2 S
2
Multiplexer
x3
Encoder S bus select
x4 1
x5 inputs
x6 S
0
x7

selected
x1 x2 x3 x4 x5 x6 x7 S2 S1 S0 register
0 0 0 0 0 0 0 0 0 0 none
1 0 0 0 0 0 0 0 0 1 AR
0 1 0 0 0 0 0 0 1 0 PC
0 0 1 0 0 0 0 0 1 1 DR
0 0 0 1 0 0 0 1 0 0 AC
0 0 0 0 1 0 0 1 0 1 IR
0 0 0 0 0 1 0 1 1 0 TR
0 0 0 0 0 0 1 1 1 1 Memory

For AR D4T4: PC  AR
D5T5: PC  AR

x1 = D4T4 + D5T5

Computer Organization Computer Architecture

Basic Computer Organization & Design 103 Design of AC Logic

DESIGN OF ACCUMULATOR
Circuits associated with AC
LOGIC
16
Adder and
16 16 16
From DR logic AC
circuit To bus
8
From INPR

LD INR CLR Clock

Control
gates

All the statements that change the content of AC

D0T5: AC  AC  DR AND with DR
D1T5: AC  AC + DR Add with DR
D2T5: AC  DR Transfer from DR
pB11: AC(0-7)  INPR Transfer from INPR
rB9: AC  AC Complement
rB7 : AC  shr AC, AC(15)  E Shift right
rB6 : AC  shl AC, AC(0)  E Shift left
rB11 : AC  0 Clear
rB5 : AC  AC + 1 Increment
Computer Organization Computer Architecture
Basic Computer Organization & Design 104 Design of AC Logic

CONTROL OF AC
REGISTER
Gate structures for controlling
the LD, INR, and CLR of AC

From Adder 16 16 To bus

and Logic AC
D0 AND LD Clock
T5 INR
D1 ADD CLR
D2 DR
T5
p INPR
B11
r COM
B9
SHR
B7
SHL
B6
INC
B5
CLR
B11

Computer Organization Computer Architecture

Basic Computer Organization & Design 105 Design of AC Logic

ALU (ADDER AND LOGIC

CIRCUIT)

One stage of Adder and Logic circuit

DR(i)
AC(i)

AND

C LD
i ADD
FA I J Q
i
AC(i)
DR
C
i+1
K
INPR
From
INPR
bit(i)
COM

SHR

AC(i+1)
SHL

AC(i-1)

Computer Organization Computer Architecture

Programming the Basic Computer 106

PROGRAMMING THE BASIC COMPUTER

Introduction

Machine Language

Assembly Language

Assembler

Program Loops

Programming Arithmetic and Logic Operations

Subroutines

Input-Output Programming

Computer Organization Computer Architecture

Programming the Basic Computer 107 Introduction

INTRODUCTION
Those concerned with computer architecture should
have a knowledge of both hardware and software
because the two branches influence each other.
Instruction Set of the Basic Computer
Symbol Hexa code Description
AND 0 or 8 AND M to AC m: effective address
ADD 1 or 9 Add M to AC, carry to E M: memory word (operand)
LDA 2 or A Load AC from M found at m
STA 3 or B Store AC in M
BUN 4 or C Branch unconditionally to m
BSA 5 or D Save return address in m and branch to m+1
ISZ 6 or E Increment M and skip if zero
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right E and AC
CIL 7040 Circulate left E and AC
INC 7020 Increment AC, carry to E
SPA 7010 Skip if AC is positive
SNA 7008 Skip if AC is negative
SZA 7004 Skip if AC is zero
SZE 7002 Skip if E is zero
HLT 7001 Halt computer
INP F800 Input information and clear flag
OUT F400 Output information and clear flag
SKI F200 Skip if input flag is on
SKO F100 Skip if output flag is on
ION F080 Turn interrupt on
IOF F040 Turn interrupt off
Computer Organization Computer Architecture
Programming the Basic Computer 108 Machine Language

MACHINE LANGUAGE
• Program
A list of instructions or statements for directing
the computer to perform a required data
processing task

• Various types of programming languages

- Hierarchy of programming languages

• Machine-language
- Binary code
- Octal or hexadecimal code

• Assembly-language (Assembler)
- Symbolic code

• High-level language (Compiler)

Computer Organization Computer Architecture

Programming the Basic Computer 109 Machine Language

COMPARISON OF PROGRAMMING LANGUAGES

• Binary Program to Add Two Numbers • Hexa program
Location Instruction
Location Instruction Code
000 2004
0 0010 0000 0000 0100 001 1005
1 0001 0000 0000 0101 002 3006
10 0011 0000 0000 0110 003 7001
11 0111 0000 0000 0001 004 0053
100 0000 0000 0101 0011 005 FFE9
101 1111 1111 1110 1001 006 0000
110 0000 0000 0000 0000

• Program with Symbolic OP-Code • Assembly-Language Program

Location Instruction Comments ORG 0 /Origin of program is location 0
000 LDA 004 Load 1st operand into AC LDA A /Load operand from location A
001 ADD 005 Add 2nd operand to AC ADD B /Add operand from location B
002 STA 006 Store sum in location 006 STA C /Store sum in location C
003 HLT Halt computer HLT /Halt computer
004 0053 1st operand A, DEC 83 /Decimal operand
005 FFE9 2nd operand (negative) B, DEC -23 /Decimal operand
006 0000 Store sum here C, DEC 0 /Sum stored in location C
END /End of symbolic program

• Fortran Program
INTEGER A, B, C
DATA A,83 / B,-23
C=A+B
END

Computer Organization Computer Architecture

Programming the Basic Computer 110 Assembly Language

ASSEMBLY LANGUAGE
Syntax of the BC assembly language
Each line is arranged in three columns called fields
Label field
- May be empty or may specify a symbolic
address consists of up to 3 characters
- Terminated by a comma
Instruction field
- Specifies a machine or a pseudo instruction
- May specify one of
* Memory reference instr. (MRI)
MRI consists of two or three symbols separated by spaces.
ADD OPR (direct address MRI)
ADD PTR I (indirect address MRI)
* Register reference or input-output instr.
Non-MRI does not have an address part
* Pseudo instr. with or without an operand
Symbolic address used in the instruction field must be
defined somewhere as a label
Comment field
- May be empty or may include a comment

Computer Organization Computer Architecture

Programming the Basic Computer 111 Assembly Language

PSEUDO-INSTRUCTIONS
ORG N
Hexadecimal number N is the memory loc.
for the instruction or operand listed in the following line
END
Denotes the end of symbolic program
DEC N
Signed decimal number N to be converted to the binary
HEX N
Hexadecimal number N to be converted to the binary

Example: Assembly language program to subtract two numbers

ORG 100 / Origin of program is location 100

LDA SUB / Load subtrahend to AC
CMA / Complement AC
INC / Increment AC
ADD MIN / Add minuend to AC
STA DIF / Store difference
HLT / Halt computer
MIN, DEC 83 / Minuend
SUB, DEC -23 / Subtrahend
DIF, HEX 0 / Difference stored here
END / End of symbolic program

Computer Organization Computer Architecture

Programming the Basic Computer 112 Assembly Language

TRANSLATION TO BINARY

Hexadecimal Code
Location Content Symbolic Program

ORG 100
100 2107 LDA SUB
101 7200 CMA
102 7020 INC
103 1106 ADD MIN
104 3108 STA DIF
105 7001 HLT
106 0053 MIN, DEC 83
107 FFE9 SUB, DEC -23
108 0000 DIF, HEX 0
END

Computer Organization Computer Architecture

Programming the Basic Computer 113 Assembler

ASSEMBLER - FIRST PASS -

Assembler
Source Program - Symbolic Assembly Language Program
Object Program - Binary Machine Language Program
Two pass assembler
1st pass: generates a table that correlates all user defined
(address) symbols with their binary equivalent value
2nd pass: binary translation

First pass
First pass

LC := 0

Scan next line of code Set LC

yes
no no
Label ORG

yes
yes
Store symbol END
in address-
symbol table
together with no Go to
value of LC second
pass
Increment LC

Computer Organization Computer Architecture

Programming the Basic Computer 114 Assembler

ASSEMBLER - SECOND PASS -

Second Pass

Machine instructions are translated by means of table-lookup procedures;

(1. Pseudo-Instruction Table, 2. MRI Table, 3. Non-MRI Table
4. Address Symbol Table)

Second pass

LC <- 0
Done
Scan next line of code
Set LC

yes yes
Pseudo yes no
ORG END
instr.

no no
DEC or
yes no HEX
MRI Convert
operand
Get operation code to binary
and set bits 2-4 Valid no
non-MRI and store
instr. in location
Search address- given by LC
symbol table for yes
binary equivalent
of symbol address
and set bits 5-16
Store binary Error in
equivalent of line of
yes no instruction code
I in location
given by LC
Set Set
first first
bit to 1 bit to 0

Assemble all parts of

binary instruction and Increment LC
store in location given by LC

Computer Organization Computer Architecture

Programming the Basic Computer 115 Program Loops

PROGRAM LOOPS
Loop: A sequence of instructions that are executed many times,
each with a different set of data
Fortran program to add 100 numbers:

DIMENSION A(100)
INTEGER SUM, A
SUM = 0
DO 3 J = 1, 100
3 SUM = SUM + A(J)

Assembly-language program to add 100 numbers:

ORG 100 / Origin of program is HEX 100

LDA ADS / Load first address of operand
STA PTR / Store in pointer
LDA NBR / Load -100
STA CTR / Store in counter
CLA / Clear AC
LOP, ADD PTR I / Add an operand to AC
ISZ PTR / Increment pointer
ISZ CTR / Increment counter
BUN LOP / Repeat loop again
STA SUM / Store sum
HLT / Halt
ADS, HEX 150 / First address of operands
PTR, HEX 0 / Reserved for a pointer
NBR, DEC -100 / Initial value for a counter
CTR, HEX 0 / Reserved for a counter
SUM, HEX 0 / Sum is stored here
ORG 150 / Origin of operands is HEX 150
DEC 75 / First operand
.
.
.
DEC 23 / Last operand
END / End of symbolic program

Computer Organization Computer Architecture

Programming the Basic Computer 116 Programming Arithmetic and Logic Operations

PROGRAMMING ARITHMETIC AND LOGIC OPERATIONS

Implementation of Arithmetic and Logic Operations

- Software Implementation
- Implementation of an operation with a program
using machine instruction set
- Usually when the operation is not included
in the instruction set

- Hardware Implementation
- Implementation of an operation in a computer
with one machine instruction

Software Implementation example:

* Multiplication
- For simplicity, unsigned positive numbers
- 8-bit numbers -> 16-bit product

Computer Organization Computer Architecture

Programming the Basic Computer 117 Programming Arithmetic and Logic Operations

FLOWCHART OF A PROGRAM - Multiplication -

CTR  - 8
P0
X holds the multiplicand
Y holds the multiplier
E0 P holds the product

Example with four significant digits

AC  Y

X = 0000 1111 P
cir EAC
Y = 0000 1011 0000 0000
0000 1111 0000 1111
Y  AC 0001 1110 0010 1101
0000 0000 0010 1101
=0 =1 0111 1000 1010 0101
E 1010 0101
PP+X

E0

AC  X

cil EAC
cil

X  AC

CTR  CTR + 1

0 =0
CTR Stop

Computer Organization Computer Architecture

Programming the Basic Computer 118 Programming Arithmetic and Logic Operations

ASSEMBLY LANGUAGE PROGRAM - Multiplication -

ORG 100
LOP, CLE / Clear E
LDA Y / Load multiplier
CIR / Transfer multiplier bit to E
STA Y / Store shifted multiplier
SZE / Check if bit is zero
BUN ONE / Bit is one; goto ONE
BUN ZRO / Bit is zero; goto ZRO
ONE, LDA X / Load multiplicand
ADD P / Add to partial product
STA P / Store partial product
CLE / Clear E
ZRO, LDA X / Load multiplicand
CIL / Shift left
STA X / Store shifted multiplicand
ISZ CTR / Increment counter
BUN LOP / Counter not zero; repeat loop
HLT / Counter is zero; halt
CTR, DEC -8 / This location serves as a counter
X, HEX 000F / Multiplicand stored here
Y, HEX 000B / Multiplier stored here
P, HEX 0 / Product formed here
END

Computer Organization Computer Architecture

Programming the Basic Computer 119 Programming Arithmetic and Logic Operations
ASSEMBLY LANGUAGE PROGRAM
- Double Precision Addition -

LDA AL / Load A low

ADD BL / Add B low, carry in E
STA CL / Store in C low
CLA / Clear AC
CIL / Circulate to bring carry into AC(16)
ADD AH / Add A high and carry
ADD BH / Add B high
STA CH / Store in C high
HLT

Computer Organization Computer Architecture

Programming the Basic Computer 120 Programming Arithmetic and Logic Operations
ASSEMBLY LANGUAGE PROGRAM
- Logic and Shift Operations -
• Logic operations

- BC instructions : AND, CMA, CLA

- Program for OR operation

LDA A / Load 1st operand

CMA / Complement to get A’
STA TMP / Store in a temporary location
LDA B / Load 2nd operand B
CMA / Complement to get B’
AND TMP / AND with A’ to get A’ AND B’
CMA / Complement again to get A OR B

• Shift operations - BC has Circular Shift only

- Logical shift-right operation - Logical shift-left operation

CLE CLE
CIR CIL

- Arithmetic right-shift operation

CLE / Clear E to 0
SPA / Skip if AC is positive
CME / AC is negative
CIR / Circulate E and AC

Computer Organization Computer Architecture

Programming the Basic Computer 121 Subroutines

SUBROUTINES
Subroutine

- A set of common instructions that can be used in a program many times.

- Subroutine linkage : a procedure for branching
to a subroutine and returning to the main program

Example

Loc. ORG 100 / Main program

100 LDA X / Load X
101 BSA SH4 / Branch to subroutine
102 STA X / Store shifted number
103 LDA Y / Load Y
104 BSA SH4 / Branch to subroutine again
105 STA Y / Store shifted number
106 HLT
107 X, HEX 1234
108 Y, HEX 4321
/ Subroutine to shift left 4 times
109 SH4, HEX 0 / Store return address here
10A CIL / Circulate left once
10B CIL
10C CIL
10D CIL / Circulate left fourth time
10E AND MSK / Set AC(13-16) to zero
10F BUN SH4 I / Return to main program
110 MSK, HEX FFF0 / Mask operand
END

Computer Organization Computer Architecture

Programming the Basic Computer 122 Subroutines

SUBROUTINE PARAMETERS AND DATA LINKAGE

Linkage of Parameters and Data between the Main Program and a Subroutine
- via Registers
- via Memory locations
- ….

Example: Subroutine performing LOGICAL OR operation; Need two parameters

Loc. ORG 200
200 LDA X / Load 1st operand into AC
201 BSA OR / Branch to subroutine OR
202 HEX 3AF6 / 2nd operand stored here
203 STA Y / Subroutine returns here
204 HLT
205 X, HEX 7B95 / 1st operand stored here
206 Y, HEX 0 / Result stored here
207 OR, HEX 0 / Subroutine OR
208 CMA / Complement 1st operand
209 STA TMP / Store in temporary location
20A LDA OR I / Load 2nd operand
20B CMA / Complement 2nd operand
20C AND TMP / AND complemented 1st operand
20D CMA / Complement again to get OR
20E ISZ OR / Increment return address
20F BUN OR I / Return to main program
210 TMP, HEX 0 / Temporary storage
END
Computer Organization Computer Architecture
Programming the Basic Computer 123 Subroutines

SUBROUTINE - Moving a Block of Data -

/ Main program
BSA MVE / Branch to subroutine
HEX 100 / 1st address of source data
HEX 200 / 1st address of destination data
DEC -16 / Number of items to move
HLT
MVE, HEX 0 / Subroutine MVE
LDA MVE I / Bring address of source
STA PT1 / Store in 1st pointer
ISZ MVE / Increment return address
LDA MVE I / Bring address of destination
STA PT2 / Store in 2nd pointer
ISZ MVE / Increment return address
LDA MVE I / Bring number of items
STA CTR / Store in counter
ISZ MVE / Increment return address
LOP, LDA PT1 I / Load source item
STA PT2 I / Store in destination • Fortran subroutine
ISZ PT1 / Increment source pointer
ISZ PT2 / Increment destination pointer SUBROUTINE MVE (SOURCE, DEST, N)
ISZ CTR / Increment counter DIMENSION SOURCE(N), DEST(N)
BUN LOP / Repeat 16 times DO 20 I = 1, N
BUN MVE I / Return to main program 20 DEST(I) = SOURCE(I)
PT1, -- RETURN
PT2, -- END
CTR, --

Computer Organization Computer Architecture

Programming the Basic Computer 124 Input Output Program

INPUT OUTPUT PROGRAM

Program to Input one Character(Byte)

CIF, SKI / Check input flag

BUN CIF / Flag=0, branch to check again
INP / Flag=1, input character
OUT / Display to ensure correctness
STA CHR / Store character
HLT
CHR, -- / Store character here

Program to Output a Character

LDA CHR / Load character into AC

COF, SKO / Check output flag
BUN COF / Flag=0, branch to check again
OUT / Flag=1, output character
HLT
CHR, HEX 0057 / Character is "W"

Computer Organization Computer Architecture

Programming the Basic Computer 125 Input Output Program

CHARACTER MANIPULATION

Subroutine to Input 2 Characters and pack into a word

IN2, -- / Subroutine entry

FST, SKI
BUN FST
INP / Input 1st character
OUT
BSA SH4 / Logical Shift left 4 bits
BSA SH4 / 4 more bits
SCD, SKI
BUN SCD
INP / Input 2nd character
OUT
BUN IN2 I / Return

Computer Organization Computer Architecture

Programming the Basic Computer 126 Input Output Program

PROGRAM INTERRUPT
Tasks of Interrupt Service Routine
- Save the Status of CPU
Contents of processor registers and Flags

- Identify the source of Interrupt

Check which flag is set

- Service the device whose flag is set

(Input Output Subroutine)

- Restore contents of processor registers and flags

- Turn the interrupt facility on

- Return to the running program

Load PC of the interrupted program

Computer Organization Computer Architecture

Programming the Basic Computer 127 Input Output Program

INTERRUPT SERVICE ROUTINE

Loc.
0 ZRO, - / Return address stored here
1 BUN SRV / Branch to service routine
100 CLA / Portion of running program
101 ION / Turn on interrupt facility
102 LDA X
103 ADD Y / Interrupt occurs here
104 STA Z / Program returns here after interrupt
/ Interrupt service routine
200 SRV, STA SAC / Store content of AC
CIR / Move E into AC(1)
STA SE / Store content of E
SKI / Check input flag
BUN NXT / Flag is off, check next flag
INP / Flag is on, input character
OUT / Print character
STA PT1 I / Store it in input buffer
ISZ PT1 / Increment input pointer
NXT, SKO / Check output flag
BUN EXT / Flag is off, exit
LDA PT2 I / Load character from output buffer
OUT / Output character
ISZ PT2 / Increment output pointer
EXT, LDA SE / Restore value of AC(1)
CIL / Shift it to E
LDA SAC / Restore content of AC
ION / Turn interrupt on
BUN ZRO I / Return to running program
SAC, - / AC is stored here
SE, - / E is stored here
PT1, - / Pointer of input buffer
PT2, - / Pointer of output buffer

Computer Organization Computer Architecture

Microprogrammed Control 128

MICROPROGRAMMED
CONTROL

• Control Memory

• Sequencing Microinstructions

• Microprogram Example

• Design of Control Unit

Computer Organization Computer Architecture

Microprogrammed Control 129 Implementation of Control Unit

COMPARISON OF CONTROL UNIT IMPLEMENTATIONS

Control Unit Implementation
Combinational Logic Circuits (Hard-wired)
Control Data
Memory IR Status F/Fs

Control Unit's State

Timing State
Combinational Control CPU
Logic Circuits Points
Ins. Cycle State

Microprogram
M Control Data
e
m
o IR Status F/Fs
r
y

C Control C
Next Address Storage C
S S D P CPU
Generation A (-program D
Logic s
R memory) R }

Computer Organization Computer Architecture

 130

Control Memory
• When the control signals are generated by hardware using
conventional logic design techniques, the control unit is
said to be hardwired.
• Microprogramming is a second alternative for designing
the control unit of a digital computer. The principle of
microprogramming is an elegant and systematic method
for controlling the micro operation sequences in a digital
computer.
• The control variables at any given time can be represented
by a string of 1's and 0's called a control word. As such,
control words can be programmed to perform various
operations on the components of the system.
• A control unit whose binary control variables are stored in
memory is called a microprogrammed control unit.

Computer Organization Computer Architecture

 131

Control Memory….
• The microinstruction specifies one or more micro-
operations for the system.
• A sequence of microinstructions constitutes a micro
program.
• A memory that is part of a control unit is referred to as a
control memory.
• A computer that employs a microprogrammed control unit
will have two separate memories: a main memory and a
control memory.
• The main memory is available to the user for storing the
programs. The contents of main memory may alter when
the data are manipulated and every time that the program
is changed.
• The user's program in main memory consists of machine
instructions and data.
Computer Organization Computer Architecture
 132

Control Memory….
• The control memory holds a fixed microprogram that
cannot be altered by the occasional user.
• The microprogram consists of microinstructions that
specify various internal control signals for execution of
register microoperations.
• Each machine instruction initiates a series of
microinstructions in control memory.

• These microinstructions generate the microoperations to

fetch the instruction from main memory, to evaluate the
effective address, to execute the operation specified by
the instruction, and to return control to the fetch phase in
order to repeat the cycle for the next instruction.
• The control memory is assumed to be a ROM, within
which all control information is permanently stored.
Computer Organization Computer Architecture
 133

Control Memory….
• The control memory address register specifies the
address of the microinstruction, and the control data
register holds the microinstruction read from memory.
• A microinstruction contains bits for initiating
microoperations in the data processor part and bits that
determine the address sequence for the control memory.

Computer Organization Computer Architecture

 134

Control Memory….
• The next address generator is sometimes called a
microprogram sequencer, as it determines the address
sequence that is read from control memory.
• The address of the next microinstruction can be
specified in several ways, depending on the sequencer
inputs.
• Typical functions of a microprogram sequencer are
incrementing the control address register by one,
loading into the control address register an address from
control memory, transferring an external address, or
loading an initial address to start the control operations.
• The control data register holds the present
microinstruction while the next address is computed and
read from memory. The data register is sometimes called
a pipeline register.

Computer Organization Computer Architecture

 135

Control Memory….
• It allows the execution of the microoperations specified
by the control word simultaneously with the generation
of the next microinstruction.
• This configuration requires a two-phase clock, with one
clock applied to the address register and the other to the
data register.
• The main advantage of the microprogrammed control is
the fact that once the hardware configuration is
established, there should be no need for further
hardware or wiring changes.
• If we want to establish a different control sequence for
the system, all we need to do is specify a different set of
microinstructions for control memory.

Computer Organization Computer Architecture

Microprogrammed Control 136

TERMINOLOGY
Microprogram
- Program stored in memory that generates all the control signals required
to execute the instruction set correctly
- Consists of microinstructions

Microinstruction
- Contains a control word and a sequencing word
Control Word - All the control information required for one clock cycle
Sequencing Word - Information needed to decide
the next microinstruction address
- Vocabulary to write a microprogram

Control Memory(Control Storage: CS)

- Storage in the microprogrammed control unit to store the microprogram

Writeable Control Memory(Writeable Control Storage:WCS)

- CS whose contents can be modified
-> Allows the microprogram can be changed
-> Instruction set can be changed or modified

Dynamic Microprogramming
- Computer system whose control unit is implemented with
a microprogram in WCS
- Microprogram can be changed by a systems programmer or a user

Computer Organization Computer Architecture

Microprogrammed Control 137

TERMINOLOGY

Sequencer (Microprogram Sequencer)

A Microprogram Control Unit that determines
the Microinstruction Address to be executed
in the next clock cycle

- In-line Sequencing
- Branch
- Conditional Branch
- Subroutine
- Loop
- Instruction OP-code mapping

Computer Organization Computer Architecture

 138

Address Sequencing
• Microinstructions are stored in control memory in
groups, with each group specifying a routine.
• Each computer instruction has its own microprogram
routine in control memory to generate the
microoperations that execute the instruction.
• The hardware that controls the address sequencing of
the control memory must be capable of sequencing the
microinstructions within a routine and be able to branch
from one routine to another.
• To appreciate the address sequencing in a
microprogram control unit, let us enumerate the steps
that the control must undergo during the execution of a
single computer instruction.
• An initial address is loaded into the control address
register when power is turned on in the computer.

Computer Organization Computer Architecture

 139

Address Sequencing…..
• This address is usually the address of the first
microinstruction that activates the instruction fetch routine.
• The fetch routine may be sequenced by incrementing the
control address register through the rest of its
microinstructions. At the end of the fetch routine, the
instruction is in the instruction register of the computer.
• The control memory next must go through the routine that
determines the effective address of the operand.
• A machine instruction may have bits that specify various
addressing modes, such as indirect address and index
registers.
• The effective address computation routine in control
memory can be reached through a branch microinstruction,
which is conditioned on the status of the mode bits of the
instruction.

Computer Organization Computer Architecture

 140

Address Sequencing…..
• The next step is to generate the microoperations that
execute the instruction fetched from memory. The
microoperation steps to be generated in processor registers
depend on the operation code part of the instruction.
• Each instruction has its own microprogram routine stored
in a given location of control memory. The transformation
from the instruction code bits to an address in control
memory where the routine is located is referred to as a
mapping process.
• A mapping procedure is a rule that transforms the
instruction code into a control memory address.
• Once the required routine is reached, the microinstructions
that execute the instruction may be sequenced by
incrementing the control address register, but sometimes
the sequence of microoperations will depend on values of
certain status bits in processor registers .

Computer Organization Computer Architecture

 141

Address Sequencing…..
• Microprograms that employ subroutines will require an
external register for storing the return address. Return
addresses cannot be stored in ROM because the unit has
no writing capability.
• The address sequencing capabilities required in a
control memory are:

1. Incrementing of the control address register.

2. Unconditional branch or conditional branch, depending
on status bit conditions.
3. A mapping process from the bits of the instruction to an
address for control memory.
4. A facility for subroutine call and return.

Computer Organization Computer Architecture

 142

Address Sequencing…..

Computer Organization Computer Architecture

 143

Address Sequencing…..
Conditional Branching:
• The branch logic provides decision-making capabilities in
the control unit.
• The status conditions are special bits in the system that
provide parameter information such as the carry-out of an
adder, the sign bit of a number, the mode bits of an
instruction, and input or output status conditions.
• Information in these bits can be tested and actions
initiated based on their condition: whether their value is 1
or 0.
• The status bits, together with the field in the
microinstruction that specifies a branch address, control
the conditional branch decisions generated in the branch
logic.

Computer Organization Computer Architecture

 144

Address Sequencing…..
• The branch logic hardware may be implemented in a variety
of ways. The simplest way is to test the specified condition
and branch to the indicated address if the condition is met,
otherwise, the address register is incremented.
• This can be implemented with a multiplexer. Suppose that
there are eight status bit conditions in the system.
• Three bits in the microinstruction are used to specify any
one of eight status bit conditions. These three bits provide
the selection variables for the multiplexer.
• If the selected status bit is in the 1 state, the output of the
multiplexer is 1, otherwise, it is 0.
• A 1 output in the multiplexer generates a control signal to
transfer the branch address from the microinstruction into
the control address register. A 0 output in the multiplexer
causes the address register to be incremented.

Computer Organization Computer Architecture

 145

Address Sequencing…..

• In this configuration, the microprogram follows one of

two possible paths, depending on the value of the
selected status bit.
• An unconditional branch microinstruction can be
implemented by loading the branch address from control
memory into the control address register.
• This can be accomplished by fixing the value of one
status bit at the input of the multiplexer, so it is always
equal to 1.
• A reference to this bit by the status bit select lines from
control memory causes the branch address to be loaded
into the control address register unconditionally.

Computer Organization Computer Architecture

 146

Mapping of Instruction
A special type of branch exists when a microinstruction
specifies a branch to the first word in control memory where a
microprogram routine for an instruction is located.

The status bits for this type of branch are the bits in the
operation code part of the instruction. For example, a computer
with a simple instruction format as shown in Fig., has an
operation code of four bits which can specify up to 16 distinct
instructions.

Assume further that the control memory has 128 words,

requiring an address of seven bits.

For each operation code there exists a microprogram routine

in control memory that executes the instruction.

One simple mapping process that converts the 4-bit operation

code to a 7-bit address for control memory is shown in Fig..
Computer Organization Computer Architecture
 147

Mapping of Instruction….
 This mapping consists of placing a 0 in the most
significant bit of the address, transferring the four
operation code bits, and clearing the two least
significant bits of the control address register.
 This provides for each computer instruction a
microprogram routine with a capacity of four
microinstructions.
 If the routine needs more than four microinstructions, it
can use addresses 1000000 through 1 1 1 1 1 1 1 .
 If it uses fewer than four microinstructions, the unused
memory locations would be available for other routines.
 One can extend this concept to a more general mapping
rule by using a ROM to specify the mapping function.

Computer Organization Computer Architecture

 148

Mapping of Instruction….

Mapping from instruction code to microinstruction address

Computer Organization Computer Architecture

Microprogrammed Control 149 Sequencing

MICROINSTRUCTION SEQUENCING
Instruction code

Mapping
logic

Status Branch MUX Multiplexers

bits logic select

Subroutine
register
Control address register (SBR)
(CAR)

Incrementer

Control memory (ROM)

select a status
bit
Microoperations
Branch address

Sequencing Capabilities Required in a Control Storage

- Incrementing of the control address register
- Unconditional and conditional branches
- A mapping process from the bits of the machine
instruction to an address for control memory
- A facility for subroutine call and return
Computer Organization Computer Architecture
Microprogrammed Control 150 Sequencing

CONDITIONAL BRANCH
Load address
Control address register

Increment

MUX
Control memory

...
Status bits
(condition)

Condition select Micro-operations

Next address

Conditional Branch
If Condition is true, then Branch (address from
the next address field of the current microinstruction)
else Fall Through
Conditions to Test: O(overflow), N(negative),
Z(zero), C(carry), etc.

Unconditional Branch
Fixing the value of one status bit at the input of the multiplexer to 1
Computer Organization Computer Architecture
Microprogrammed Control 151 Sequencing

MAPPING OF INSTRUCTIONS
Direct Mapping Address
OP-codes of Instructions 0000 ADD Routine
0001 AND Routine
ADD 0000
. 0010 LDA Routine
AND 0001
. 0011 STA Routine
LDA 0010 . 0100 BUN Routine
STA 0011
BUN 0100 Control
Storage

Mapping
Bits 10 xxxx 010 Address
10 0000 010 ADD Routine

10 0001 010 AND Routine

10 0010 010 LDA Routine

10 0011 010 STA Routine

10 0100 010 BUN Routine

Computer Organization Computer Architecture

Microprogrammed Control 152 Sequencing

MAPPING OF INSTRUCTIONS TO MICROROUTINES

Mapping from the OP-code of an instruction to the
address of the Microinstruction which is the starting
microinstruction of its execution microprogram

Machine OP-code
Instruction 1 0 1 1 Address

Mapping bits 0 x x x x 0 0
Microinstruction
address 0 1 0 1 1 0 0

Mapping function implemented by ROM or PLA

OP-code

Mapping memory
(ROM or PLA)

Control address register

Control Memory

Computer Organization Computer Architecture

 153

Subroutines
• Subroutines are programs that are used by other
routines to accomplish a particular task.
• A subroutine can be called from any point within the
main body of the microprogram. Frequently, many
Microprograms contain identical sections of code.
• Microinstructions can be saved by employing
subroutines that use common sections of microcode.

• For example, the sequence of microoperations needed to

generate the effective address of the operand for an
instruction is common to all memory reference
instructions.
• This sequence could be a subroutine that is called from
within many other routines to execute the effective
address computation.
Computer Organization Computer Architecture
 154

Subroutines…
• Microprograms that use subroutines must have a
provision for storing the return address during a
subroutine call and restoring the address during a
subroutine return.
• This may be accomplished by placing the incremented
output from the control address register into a
subroutine register and branching to the beginning of
the subroutine.
• The subroutine register can then become the source for
transferring the address for the return to the main
routine.
• The best way to structure a register file that stores
addresses for subroutines is to organize the registers in
a last-in, first-out (LIFO) stack.

Computer Organization Computer Architecture

Microprogrammed Control 155 Microprogram

MICROPROGRAM EXAMPLE
Computer Configuration

MUX
10 0
AR
Address Memory
10 0 2048 x 16
PC

MUX

15 0
6 0 6 0 DR
SBR CAR

Control memory Arithmetic

128 x 20 logic and
shift unit
Control unit
15 0
AC

Computer Organization Computer Architecture

Microprogrammed Control 156 Microprogram

MACHINE INSTRUCTION FORMAT

Machine instruction format

15 14 11 10 0
I Opcode Address

Sample machine instructions

Symbol OP-code Description
EA is the effective address
ADD 0000 AC AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC  EA)
STORE 0010 M[EA]  AC
EXCHANGE 0011 AC M[EA], M[EA]  AC

Microinstruction Format
3 3 3 2 2 7
F1 F2 F3 CD BR AD

F1, F2, F3: Microoperation fields

CD: Condition for branching
BR: Branch field
AD: Address field

Computer Organization Computer Architecture

Microprogrammed Control 157 Microprogram

MICROINSTRUCTION FIELD DESCRIPTIONS - F1,F2,F3

F1 Microoperation Symbol F2 Microoperation Symbol
000 None NOP 000 None NOP
001 AC  AC + DR ADD 001 AC  AC - DR SUB
010 AC  0 CLRAC 010 AC  AC  DR OR
011 AC  AC + 1 INCAC 011 AC  AC  DR AND
100 AC  DR DRTAC 100 DR  M[AR] READ
101 AR  DR(0-10) DRTAR 101 DR  AC ACTDR
110 AR  PC PCTAR 110 DR  DR + 1 INCDR
111 M[AR]  DR WRITE 111 DR(0-10)  PC PCTDR

F3 Microoperation Symbol
000 None NOP
001 AC  AC  DR XOR
010 AC  AC’ COM
011 AC  shl AC SHL
100 AC  shr AC SHR
101 PC  PC + 1 INCPC
110 PC  AR ARTPC
111 Reserved

Computer Organization Computer Architecture

Microprogrammed Control 158 Microprogram

MICROINSTRUCTION FIELD DESCRIPTIONS - CD, BR

CD Condition Symbol Comments

00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC = 0 Z Zero value in AC

BR Symbol Function
00 JMP CAR  AD if condition = 1
CAR  CAR + 1 if condition = 0
01 CALL CAR  AD, SBR  CAR + 1 if condition = 1
CAR  CAR + 1 if condition = 0
10 RET CAR  SBR (Return from subroutine)
11 MAP CAR(2-5)  DR(11-14), CAR(0,1,6)  0

Computer Organization Computer Architecture

Microprogrammed Control 159 Microprogram

SYMBOLIC MICROINSTRUCTIONS
• Symbols are used in microinstructions as in assembly language
• A symbolic microprogram can be translated into its binary equivalent
by a microprogram assembler.

Sample Format
five fields: label; micro-ops; CD; BR; AD

Label: may be empty or may specify a symbolic

address terminated with a colon

Micro-ops: consists of one, two, or three symbols

separated by commas

CD: one of {U, I, S, Z}, where U: Unconditional Branch

I: Indirect address bit
S: Sign of AC
Z: Zero value in AC

BR: one of {JMP, CALL, RET, MAP}

AD: one of {Symbolic address, NEXT, empty}

Computer Organization Computer Architecture

Microprogrammed Control 160 Microprogram

SYMBOLIC MICROPROGRAM - FETCH ROUTINE

During FETCH, Read an instruction from memory
and decode the instruction and update PC

Sequence of microoperations in the fetch cycle:

AR PC
DR  M[AR], PC  PC + 1
AR  DR(0-10), CAR(2-5)  DR(11-14), CAR(0,1,6)  0

Symbolic microprogram for the fetch cycle:

ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP

Binary equivalents translated by an assembler

Binary
address F1 F2 F3 CD BR AD
1000000 110 000 000 00 00 1000001
1000001 000 100 101 00 00 1000010
1000010 101 000 000 00 11 0000000

Computer Organization Computer Architecture

Microprogrammed Control 161 Microprogram

SYMBOLIC MICROPROGRAM
• Control Storage: 128 20-bit words
• The first 64 words: Routines for the 16 machine instructions
• The last 64 words: Used for other purpose (e.g., fetch routine and other subroutines)
• Mapping: OP-code XXXX into 0XXXX00, the first address for the 16 routines are
0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60

Partial Symbolic Microprogram

Label Microops CD BR AD
ORG 0
ADD: NOP I CALL INDRCT
READ U JMP NEXT
ADD U JMP FETCH
ORG 4
BRANCH: NOP S JMP OVER
NOP U JMP FETCH
OVER: NOP I CALL INDRCT
ARTPC U JMP FETCH
ORG 8
STORE: NOP I CALL INDRCT
ACTDR U JMP NEXT
WRITE U JMP FETCH
ORG 12
EXCHANGE: NOP I CALL INDRCT
READ U JMP NEXT
ACTDR, DRTAC U JMP NEXT
WRITE U JMP FETCH
ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP
INDRCT: READ U JMP NEXT
DRTAR U RET

Computer Organization Computer Architecture

Microprogrammed Control 162 Microprogram

BINARY
MICROPROGRAM
Address Binary Microinstruction
Micro Routine Decimal Binary F1 F2 F3 CD BR AD
ADD 0 0000000 000 000 000 01 01 1000011
1 0000001 000 100 000 00 00 0000010
2 0000010 001 000 000 00 00 1000000
3 0000011 000 000 000 00 00 1000000

BRANCH 4 0000100 000 000 000 10 00 0000110

5 0000101 000 000 000 00 00 1000000
6 0000110 000 000 000 01 01 1000011
7 0000111 000 000 110 00 00 1000000
STORE 8 0001000 000 000 000 01 01 1000011
9 0001001 000 101 000 00 00 0001010
10 0001010 111 000 000 00 00 1000000
11 0001011 000 000 000 00 00 1000000
EXCHANGE 12 0001100 000 000 000 01 01 1000011
13 0001101 001 000 000 00 00 0001110
14 0001110 100 101 000 00 00 0001111
15 0001111 111 000 000 00 00 1000000

FETCH 64 1000000 110 000 000 00 00 1000001

65 1000001 000 100 101 00 00 1000010
66 1000010 101 000 000 00 11 0000000
INDRCT 67 1000011 000 100 000 00 00 1000100
68 1000100 101 000 000 00 10 0000000

This microprogram can be implemented using ROM

Computer Organization Computer Architecture

Microprogrammed Control 163 Design of Control Unit
DESIGN OF CONTROL UNIT
- DECODING ALU CONTROL INFORMATION -

microoperation fields
F1 F2 F3

3 x 8 decoder 3 x 8 decoder 3 x 8 decoder

7 6 54 3 21 0 7 6 54 3 21 0 76 54 321 0

AND
ADD AC
Arithmetic
logic and DR
DRTAC shift unit
PCTAR

DRTAR

From From
PC DR(0-10) Load
AC

Select 0 1
Multiplexers

Load Clock
AR

Decoding of Microoperation Fields

Computer Organization Computer Architecture
Microprogrammed Control 164 Design of Control Unit
MICROPROGRAM SEQUENCER
- NEXT MICROINSTRUCTION ADDRESS LOGIC -
Branch, CALL Address
External RETURN form Subroutine
(MAP)
In-Line
S1S0 Address Source
00 CAR + 1, In-Line 3 2 1 0
S1 MUX1 L
01 SBR RETURN SBR Subroutine
S0 CALL
10 CS(AD), Branch or CALL Address
11 MAP source
selection
Incrementer

Clock CAR

Control Storage

MUX-1 selects an address from one of four sources and routes it into a CAR

- In-Line Sequencing  CAR + 1

- Branch, Subroutine Call  CS(AD)
- Return from Subroutine  Output of SBR
- New Machine instruction  MAP
Computer Organization Computer Architecture
Microprogrammed Control 165 Design of Control Unit
MICROPROGRAM SEQUENCER
- CONDITION AND BRANCH CONTROL -

1 L L(load SBR with PC)

From I MUX2 Test
CPU S T for subroutine Call
BR field Input
Z Select I0 logic
of CS I1
S0 for next address
S1 selection
CD Field of CS

Input Logic
I 1 I0 T Meaning Source of Address S1S0 L

000 In-Line CAR+1 00 0

001 JMP CS(AD) 01 0
010 In-Line CAR+1 00 0
011 CALL CS(AD) and SBR <- CAR+1 01 1
10x RET SBR 10 0
11x MAP DR(11-14) 11 0

S1 = I 1
S0 = I1I0 + I1’T
L = I1’I0T

Computer Organization Computer Architecture

Microprogrammed Control 166 Design of Control Unit

MICROPROGRAM SEQUENCER
External
(MAP)

L
I0 3 2 1 0
Input Load
I1 logic S1 MUX1 SBR
T S0

1 Incrementer
I MUX2 Test
S
Z Select
Clock CAR

Control memory

Microops CD BR AD
... ...

Computer Organization Computer Architecture

Microprogrammed Control 167 Microinstruction Format

MICROINSTRUCTION FORMAT

Information in a Microinstruction
- Control Information
- Sequencing Information
- Constant
Information which is useful when feeding into the system

These information needs to be organized in some way for

- Efficient use of the microinstruction bits
- Fast decoding

Field Encoding

- Encoding the microinstruction bits

- Encoding slows down the execution speed
due to the decoding delay
- Encoding also reduces the flexibility due to
the decoding hardware

Computer Organization Computer Architecture

Microprogrammed Control 168 Microinstruction Format
HORIZONTAL AND VERTICAL
MICROINSTRUCTION FORMAT
Horizontal Microinstructions
Each bit directly controls each micro-operation or each control point
Horizontal implies a long microinstruction word
Advantages: Can control a variety of components operating in parallel.
--> Advantage of efficient hardware utilization
Disadvantages: Control word bits are not fully utilized
--> CS becomes large --> Costly
Vertical Microinstructions
A microinstruction format that is not horizontal
Vertical implies a short microinstruction word
Encoded Microinstruction fields
--> Needs decoding circuits for one or two levels of decoding

One-level decoding Two-level decoding

Field A Field B
Field A Field B
2 bits 6 bits
2 bits 3 bits

2x4 6 x 64
2x4 3x8 Decoder Decoder
Decoder Decoder

Decoder and
1 of 4 1 of 8 selection logic

Computer Organization Computer Architecture

Microprogrammed Control 169 Control Storage Hierarchy

NANOSTORAGE AND NANOINSTRUCTION

The decoder circuits in a vertical microprogram
storage organization can be replaced by a ROM
=> Two levels of control storage
First level - Control Storage
Second level - Nano Storage

Two-level microprogram

First level
-Vertical format Microprogram
Second level
-Horizontal format Nanoprogram
- Interprets the microinstruction fields, thus converts a vertical
microinstruction format into a horizontal
nanoinstruction format.

Usually, the microprogram consists of a large number of short

microinstructions, while the nanoprogram contains fewer words
with longer nanoinstructions.

Computer Organization Computer Architecture

Microprogrammed Control 170 Control Storage Hierarchy

TWO-LEVEL MICROPROGRAMMING - EXAMPLE

* Microprogram: 2048 microinstructions of 200 bits each
* With 1-Level Control Storage: 2048 x 200 = 409,600 bits
* Assumption:
256 distinct microinstructions among 2048
* With 2-Level Control Storage:
Nano Storage: 256 x 200 bits to store 256 distinct nanoinstructions
Control storage: 2048 x 8 bits
To address 256 nano storage locations 8 bits are
needed
* Total 1-Level control storage: 409,600 bits
Total 2-Level control storage: 67,584 bits (256 x 200 + 2048 x 8)
Control address register

11 bits

Control memory
2048 x 8

Microinstruction (8 bits)
Nanomemory address

Nanomemory
256 x 200

Nanoinstructions (200 bits)

Computer Organization Computer Architecture

Central Processing Unit 171

Overview

• Instruction Set Processor (ISP)

• Central Processing Unit (CPU)
• A typical computing task consists of a series of
steps specified by a sequence of machine
instructions that constitute a program.
• An instruction is executed by carrying out a
sequence of more rudimentary operations.

Computer Organization Computer Architecture

Central Processing Unit 172

Fundamental Concepts

• Processor fetches one instruction at a time and

perform the operation specified.
• Instructions are fetched from successive
memory locations until a branch or a jump
instruction is encountered.
• Processor keeps track of the address of the
memory location containing the next instruction
to be fetched using Program Counter (PC).
• Instruction Register (IR)

Computer Organization Computer Architecture

Central Processing Unit 173

Executing an Instruction

• Fetch the contents of the memory location

pointed to by the PC. The contents of this
location are loaded into the IR (fetch phase).
IR ← [[PC]]
• Assuming that the memory is byte addressable,
increment the contents of the PC by 4 (fetch
phase).
PC ← [PC] + 4
• Carry out the actions specified by the instruction
in the IR (execution phase).

Computer Organization Computer Architecture

Central Processing Unit 174

Processor Organization
Internal processor
bus

Control signals

PC

Instruction
Address
decoder and
lines
MDR HAS MAR control logic
TWO INPUTS
Memory
AND TWO bus
OUTPUTS
MDR
Data
lines IR
Datapath
Y

Constant 4 R0

Select MUX

Add
A B
ALU Sub R n - 1 
control ALU
lines
Carry-in
XOR TEMP

Z
Textbook Page 413

Computer Organization Figure 7.1. Single-bus organization of the datapath inside a processor. Computer Architecture
Central Processing Unit 175

Executing an Instruction

• Transfer a word of data from one processor register

to another or to the ALU.
• Perform an arithmetic or a logic operation and store
the result in a processor register.
• Fetch the contents of a given memory location and
load them into a processor register.
• Store a word of data from a processor register into a
given memory location.

Computer Organization Computer Architecture

Central Processing Unit 176

Register Transfers
Internal processor
bus
Riin

Ri

Riout

Yin

Constant 4

Select MUX

A B
ALU

Zin

Zout

Figure 7.2. Input and output gating for the registers in Figure 7.1.
Computer Organization Computer Architecture
Central Processing Unit 177

Register Transfers

• All operations and data transfers are controlled by the processor

clock. Bus

D Q
1
Q
Riout

Ri in
Clock

Figure
Figure7.3. Input and
7.3. Input and output
output gating
gatingfor
forone
oneregister
registerbit.
bit.
Computer Organization Computer Architecture
Central Processing Unit 178

Performing an Arithmetic or Logic

Operation
• The ALU is a combinational circuit that has no
internal storage.
• ALU gets the two operands from MUX and bus.
The result is temporarily stored in register Z.
• What is the sequence of operations to add the
contents of register R1 to those of R2 and store
the result in R3?
1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in

Computer Organization Computer Architecture

Central Processing Unit 179

Fetching a Word from Memory

• Address into MAR; issue Read operation; data into MDR.

Memory-bus Internal processor
data lines MDRoutE MDRout bus

MDR

MDR inE MDRin

Figure
Figure7.4. Connectionand
7.4. Connection and control
control signals
signalsfor
forregister
register MDR.
Computer Organization Computer Architecture
Central Processing Unit 180

Fetching a Word from Memory

• The response time of each memory access

varies (cache miss, memory-mapped I/O,…).
• To accommodate this, the processor waits until
it receives an indication that the requested
operation has been completed (Memory-
Function-Completed, MFC).
• Move (R1), R2
 MAR ← [R1]
 Start a Read operation on the memory bus
 Wait for the MFC response from the memory
 Load MDR from the memory bus
 R2 ← [MDR]

Computer Organization Computer Architecture

Central Processing Unit 181

Step
Timing
1 2 3

Clock

MAR ← [R1]
MARin
Assume MAR
is always available
on the address lines
of the memory bus. Address

Start a Read operation on the memory bus

Read

MR

MDRinE

Data
Wait for the MFC response from the memory

MFC

Load MDR from the memory bus

MDR out

R2 ← [MDR]

Figure 7.5. Timing of a memory Read operation.

Computer Organization Computer Architecture
Central Processing Unit 182

Execution of a Complete
Instruction
• Add (R3), R1
• Fetch the instruction
• Fetch the first operand (the contents of the memory
location pointed to by R3)
• Perform the addition
• Load the result into R1

Computer Organization Computer Architecture

Central Processing Unit 183

Architecture
Internal processor
bus
Riin

Ri

Riout

Yin

Constant 4

Select MUX

A B
ALU

Zin

Zout

Figure 7.2. Input and output gating for the registers in Figure 7.1.
Computer Organization Computer Architecture
Central Processing Unit 184

Execution of a Complete
Instruction Internal processor
bus
Add (R3), R1 Control signals

PC

Instruction
Step Action Address
decoder and
lines
MAR control logic

1 PC out , MAR in , Read, Select4, Add, Zin Memory

bus

2 Zout , PC in , Yin , WMF C MDR

Data
lines IR
3 MDR out , IR in
4 R3out , MAR in , Read Y

Constant 4 R0
5 R1out , Yin , WMF C
6 MDR out , SelectY, Add, Zin Select MUX

7 Zout , R1 in , End Add

A B
ALU Sub R n - 1 
control ALU
lines
Carry-in
XOR TEMP
Figure 7.6. Con trol sequence for execution of the instruction Add (R3),R1.
Z

Computer Organization Computer

Figure 7.1. Single-bus organization of Architecture
the datapath inside a processor.
Central Processing Unit 185

Execution of Branch Instructions

• A branch instruction replaces the contents of PC

with the branch target address, which is usually
obtained by adding an offset X given in the branch
instruction.
• The offset X is usually the difference between the
branch target address and the address immediately
following the branch instruction.
• Conditional branch

Computer Organization Computer Architecture

Central Processing Unit 186

Execution of Branch Instructions

Step Action

1 PCout , MAR in , Read, Select4, Add, Zin

2 Zout , PCin , Yin , WMFC
3 MDRout , IRin
4 Offset-field-of-IRout, Add, Zin
5 Zout , PCin , End

Figure 7.7. Control sequence for an unconditional branch instruction.

Computer Organization Computer Architecture

Central Processing Unit 187

Multiple-Bus Organization
Bus A Bus B Bus C

Incrementer

PC

Register
file

Constant 4

MUX
A

ALU R

Instruction
decoder

IR

MDR

MAR

Memory bus Address

data lines lines

Computer Organization Figure 7.8. Three-b us organization of the datapath. Computer Architecture
Central Processing Unit 188

Multiple-Bus Organization

• Add R4, R5, R6

Step Action

1 PC , R=B, MAR , Read, IncPC

out in
2 WMF C

3 MDR , R=B, IR
outB in
4 R4 , R5 , SelectA, Add, R6 , End
outA outB in

Figure 7.9. Control sequence for the instruction. Add R4,R5,R6,

for the three-bus organization in Figure 7.8.

Computer Organization Computer Architecture

Central Processing Unit 189

Quiz
Internal processor
bus

Control signals

• What is the control PC

sequence for execution Address

Instruction
decoder and

of the instruction
lines
MAR control logic

Memory

Add R1, R2
bus

MDR
Data
IR
including the instruction
lines

fetch phase? (Assume Constant 4

Y
R0

single bus architecture) Select MUX

Add
A B
ALU Sub R n - 1 
control ALU
lines
Carry-in
XOR TEMP

Figure 7.1. Single-bus organization of the datapath inside a processor.

Computer Organization Computer Architecture
Central Processing Unit 190

Control Unit Organization

CLK Control step
Clock counter

External
inputs
Decoder/
IR
encoder
Condition
codes

Control signals

Figure 7.10. Control unit organization.

Computer Organization Computer Architecture

Central Processing Unit 191

Detailed Block Description

CLK
Clock Control step Reset
counter

Step decoder

T 1 T2 Tn

INS 1
External
INS 2 inputs
Instruction
IR Encoder
decoder
Condition
codes
INSm

Run End

Control signals

Figure 7.11. Separation of the decoding and encoding functions.

Computer Organization Computer Architecture
Central Processing Unit 192

Generating Zin

• Zin = T1 + T6 • ADD + T4 • BR + …
Branch Add

T4 T6

T1

Figure 7.12. Generation of the Zin control signal for the processor in Figure 7.1.

Computer Organization Computer Architecture

Central Processing Unit 193

Generating End

• End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +…

Branch<0
Add Branch
N N

T7 T5 T4 T5

End

Figure 7.13. Generation of the End control signal.

Computer Organization Computer Architecture
Central Processing Unit 194

A Complete Processor

Instruction Integer Floating-point

unit unit unit

Instruction Data
cache cache

Bus interface
Processor

System bus

Main Input/
memory Output

Figure 7.14. Block diagram of a complete processor.

Computer Organization Computer Architecture
Microprogrammed Control 195

Overview

• Control signals are generated by a program similar to machine

language programs.
• Control Word (CW); microroutine; microinstruction

MDRout

WMFC
MAR in

Select
PCout

R1out

R3out
Micro -

Read
PCin

R1 in
Z out
Add

End
IRin
Yin
instruction

Zin
1 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0
2 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
4 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0
6 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1

Figure 7.15 An example of microinstructions for Figure 7.6.

Computer Organization Computer Architecture
Microprogrammed Control 196

Overview

Step Action

1 PC out , MAR in , Read, Select4, Add, Zin

2 Zout , PC in , Yin , WMF C
3 MDR out , IR in
4 R3out , MAR in , Read
5 R1out , Yin , WMF C
6 MDR out , SelectY, Add, Zin
7 Zout , R1 in , End

Figure 7.6. Con trol sequence for execution of the instruction Add (R3),R1.

Computer Organization Computer Architecture

Microprogrammed Control 197

Overview

• Control store
Starting
IR address One function
generator cannot be carried
out by this simple
organization.

Clock P C

Control
store CW

Figure 7.16. Basic organization of a microprogrammed control unit.

Computer Organization Computer Architecture
Microprogrammed Control 198

Overview

• The previous organization cannot handle the situation when the

control unit is required to check the status of the condition codes
or external inputs to choose between alternative courses of action.
• Use conditional branch microinstruction.
Address Microinstruction

0 PCout , MARin , Read, Select4, Add, Zin

1 Zout , PCin , Yin , WMFC
2 MDRout , IRin
3 Branch to starting addressof appropriatemicroroutine
. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..
25 If N=0, then branch to microinstruction0
26 Offset-field-of-IRout , SelectY, Add, Zin
27 Zout , PCin , End

Figure 7.17. Microroutine for the instruction Branch<0.

Computer Organization Computer Architecture
Microprogrammed Control 199

Overview
External
inputs

Starting and
branch address Condition
IR codes
generator

Clock  PC

Control
store CW

Figure 7.18. Organization of the control unit to allow

conditional branching in the microprogram.

Computer Organization Computer Architecture

Microprogrammed Control 200

Microinstructions

• A straightforward way to structure microinstructions

is to assign one bit position to each control signal.
• However, this is very inefficient.
• The length can be reduced: most signals are not
needed simultaneously, and many signals are
mutually exclusive.
• All mutually exclusive signals are placed in the same
group in binary coding.

Computer Organization Computer Architecture

Microprogrammed Control 201

Partial Format for the

Microinstructions
Microinstruction

F1 F2 F3 F4 F5

F1 (4 bits) F2 (3 bits) F3 (3 bits) F4 (4 bits) F5 (2 bits)

0000: No transfer 000: No transfer 000: No transfer 0000: Add 00: No action
0001: PCout 001: PCin 001: MARin 0001: Sub 01: Read
0010: MDRout 010: IRin 010: MDRin 10: Write
0011: Zout 011: Zin 011: TEMPin
0100: R0out 100: R0in 100: Yin 1111: XOR
0101: R1out 101: R1in
0110: R2out 110: R2in 16 ALU
functions
0111: R3out 111: R3 in
1010: TEMPout
1011: Offsetout

What is the price paid for

F6 F7 F8 this scheme?

F6 (1 bit) F7 (1 bit) F8 (1 bit)

0: SelectY 0: No action 0: Continue

1: Select4 1: WMFC 1: End

Figure 7.19. An example of a partial format for field-encoded microinstructions.

Computer Organization Computer Architecture
Microprogrammed Control 202

Further Improvement

• Enumerate the patterns of required signals in all

possible microinstructions. Each meaningful
combination of active control signals can then be
assigned a distinct code.
• Vertical organization
• Horizontal organization

Computer Organization Computer Architecture

Microprogrammed Control 203

Microprogram Sequencing

• If all microprograms require only straightforward

sequential execution of microinstructions except for
branches, letting a μPC governs the sequencing
would be efficient.
• However, two disadvantages:
 Having a separate microroutine for each machine instruction results
in a large total number of microinstructions and a large control store.
 Longer execution time because it takes more time to carry out the
required branches.
• Example: Add src, Rdst
• Four addressing modes: register, autoincrement,
autodecrement, and indexed (with indirect forms).

Computer Organization Computer Architecture

Microprogrammed Control 204

- Bit-ORing
- Wide-Branch Addressing
- WMFC

Computer Organization Computer Architecture

Microprogrammed Control 205
Mode

Contents of IR OP code 0 1 0 Rsrc Rdst

11 10 8 7 4 3 0

Address Microinstruction
(octal)

000 PCout, MARin , Read, Select4 , Add, Zin

001 Zout, PCin, Yin, WMFC
002 MDRout, IRin
003 Branch { PC 101 (from Instruction decoder);
 PC5,4  [IR10,9];  PC3  [IR10]  [IR9]  [IR8]}
121 Rsrcout, MARin , Read, Select4, Add, iZ
n

122 Zout, Rsrcin

123 Branch {PC 170;PC0  [IR8]}, WMFC
170 MDRout, MARin, Read, WMFC
171 MDRout, Yin
172 Rdstout , SelectY,Add, Zin
173 Zout, Rdstin, End

Figure 7.21. Microinstruction for Add (Rsrc)+,Rdst.

Note: Microinstruction at location 170 is not executed for this addressing mode.

Computer Organization Computer Architecture

Microprogrammed Control 206

Microinstructions with Next-

Address Field
• The microprogram we discussed requires
several branch microinstructions, which perform
no useful operation in the datapath.
• A powerful alternative approach is to include an
address field as a part of every microinstruction
to indicate the location of the next
microinstruction to be fetched.
• Pros: separate branch microinstructions are
virtually eliminated; few limitations in assigning
addresses to microinstructions.
• Cons: additional bits for the address field
(around 1/6)

Computer Organization Computer Architecture

Microprogrammed Control 207

Microinstructions with Next-

Address Field
IR

External Condition
Inputs codes

Decoding circuits

AR

Control store

Next address I R

Microinstruction decoder

Control signals

Figure 7.22. Microinstruction-sequencing organization.

Computer Organization Computer Architecture
Microprogrammed Control 208
Microinstruction

F0 F1 F2 F3

F0 (8 bits) F1 (3 bits) F2 (3 bits) F3 (3 bits)

Address of next 000: No transfer 000: No transfer 000: No transfer

microinstruction 001: PCout 001: PCin 001: MARin
010: MDRout 010: IRin 010: MDRin
011: Zout 011: Zin 011: TEMPin
100: Rsrcout 100: Rsrcin 100: Yin
101: Rdstout 101: Rdstin
110: TEMP out

F4 F5 F6 F7

F4 (4 bits) F5 (2 bits) F6 (1 bit) F7 (1 bit)

0000: Add 00: No action 0: SelectY 0: No action

0001: Sub 01: Read 1: Select4 1: WMFC
10: Write
1111: XOR

F8 F9 F10

F8 (1 bit) F9 (1 bit) F10 (1 bit)

0: NextAdrs 0: No action 0: No action

1: InstDec 1: ORmode 1: ORindsrc

Figure 7.23. Format for microinstructions in the example of Section 7.5.3.

Computer Organization Computer Architecture

Microprogrammed Control 209

Implementation of the Microroutine

Octal
address F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10

0 0 0 0 0 0 0 0 0 0 1 0 0 1 01 1 0 0 1 0 0 0 0 01 1 0 0 0 0
0 0 1 0 0 0 0 0 0 1 0 0 1 1 00 1 1 0 0 0 0 0 0 00 0 1 0 0 0
0 0 2 0 0 0 0 0 0 1 1 0 1 0 01 0 0 0 0 0 0 0 0 00 0 0 0 0 0
0 0 3 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 00 0 0 1 1 0

121 0 1 0 1 0 0 1 0 1 0 0 01 1 0 0 1 0 0 0 0 01 1 0 0 0 0
122 0 1 1 1 1 0 0 0 0 1 1 10 0 0 0 0 0 0 0 0 00 0 1 0 0 1

1 7 0 0 1 1 1 1 0 0 1 0 1 0 00 0 0 0 1 0 0 0 0 01 0 1 0 0 0
1 7 1 0 1 1 1 1 0 1 0 0 1 0 00 0 1 0 0 0 0 0 0 00 0 0 0 0 0
1 7 2 0 1 1 1 1 0 1 1 1 0 1 01 1 0 0 0 0 0 0 0 00 0 0 0 0 0
1 7 3 0 0 0 0 0 0 0 0 0 1 1 10 1 0 0 0 0 0 0 0 00 0 0 0 0 0

Figure 7.24. Implementation of the microroutine of Figure 7.21 using a

next-microinstruction address field. (See Figure 7.23 for encoded signals.)

Computer Organization Computer Architecture

Microprogrammed Control 210
R15in R15out R0 in R0out

Decoder

Decoder

IR Rsrc Rdst

InstDecout
External
inputs ORmode
Decoding
circuits
Condition ORindsrc
codes

AR

Control store

Next address F1 F2 F8 F9 F10

Rdstout

Rdstin
Microinstruction
decoder
Rsrcout

Rsrcin

Other control signals

Figure 7.25. Some details of the control-signal-generating circuitry.

Computer Organization Computer Architecture
Microprogrammed Control 211

bit-ORing

Computer Organization Computer Architecture

 Pipelining and Vector Processing
212

PIPELINING AND VECTOR PROCESSING

• Parallel Processing

• Pipelining

• Arithmetic Pipeline

• Instruction Pipeline

• RISC Pipeline

• Vector Processing

• Array Processors

Computer Organization Computer Architecture

 Pipelining and Vector Processing Parallel Processing
213

PARALLEL PROCESSING

Execution of Concurrent Events in the computing

process to achieve faster Computational Speed

Levels of Parallel Processing

- Job or Program level

- Task or Procedure level

- Inter-Instruction level

- Intra-Instruction level

Computer Organization Computer Architecture

 Pipelining and Vector Processing Parallel Processing
214

PARALLEL COMPUTERS
Architectural Classification

– Flynn's classification
» Based on the multiplicity of Instruction Streams and
Data Streams
» Instruction Stream
• Sequence of Instructions read from memory
» Data Stream
• Operations performed on the data in the processor

Number of Data Streams

Single Multiple

Number of Single SISD SIMD

Instruction
Streams Multiple MISD MIMD

Computer Organization Computer Architecture

 Pipelining and Vector Processing Parallel Processing
215
COMPUTER ARCHITECTURES FOR PARALLEL
PROCESSING
SISD Superscalar processors
Von-Neuman
based
Superpipelined processors

VLIW

MISD Nonexistence

SIMD Array processors

Systolic arrays
Dataflow
Associative processors

MIMD Shared-memory multiprocessors

Reduction
Bus based
Crossbar switch based
Multistage IN based

Message-passing multicomputers

Hypercube
Mesh
Reconfigurable

Computer Organization Computer Architecture

 Pipelining and Vector Processing Parallel Processing
216

SISD COMPUTER SYSTEMS

Control Processor Data stream Memory
Unit Unit

Instruction stream

Characteristics
- Standard von Neumann machine
- Instructions and data are stored in memory
- One operation at a time

Limitations
Von Neumann bottleneck

Maximum speed of the system is limited by the

Memory Bandwidth (bits/sec or bytes/sec)

- Limitation on Memory Bandwidth

- Memory is shared by CPU and I/O

Computer Organization Computer Architecture

 Pipelining and Vector Processing Parallel Processing
217

SISD PERFORMANCE IMPROVEMENTS

• Multiprogramming
• Spooling
• Multifunction processor
• Pipelining
• Exploiting instruction-level parallelism
- Superscalar
- Superpipelining
- VLIW (Very Long Instruction Word)

Computer Organization Computer Architecture

 Pipelining and Vector Processing Parallel Processing
218

MISD COMPUTER SYSTEMS

M CU P

M CU P
Memory
• •
• •
• •

M CU Data stream
P

Instruction stream

Characteristics
- There is no computer at present that can be
classified as MISD

Computer Organization Computer Architecture

 Pipelining and Vector Processing Parallel Processing
219

SIMD COMPUTER SYSTEMS

Memory
Data bus

Control Unit
Instruction stream

P P ••• P Processor units

Data stream

Alignment network

M M ••• M Memory modules

Characteristics
- Only one copy of the program exists
- A single controller executes one instruction at a time

Computer Organization Computer Architecture

 Pipelining and Vector Processing Parallel Processing
220

TYPES OF SIMD COMPUTERS

Array Processors
- The control unit broadcasts instructions to all PEs,
and all active PEs execute the same instructions
- ILLIAC IV, GF-11, Connection Machine, DAP, MPP

Systolic Arrays
- Regular arrangement of a large number of
very simple processors constructed on
VLSI circuits
- CMU Warp, Purdue CHiP

Associative Processors
- Content addressing
- Data transformation operations over many sets
of arguments with a single instruction
- STARAN, PEPE
Computer Organization Computer Architecture
 Pipelining and Vector Processing Parallel Processing
221

MIMD COMPUTER SYSTEMS

P M P M ••• P M

Interconnection Network

Shared Memory

Characteristics
- Multiple processing units

- Execution of multiple instructions on multiple data

Types of MIMD computer systems

- Shared memory multiprocessors

- Message-passing multicomputers

Computer Organization Computer Architecture

 Pipelining and Vector Processing Parallel Processing
222

SHARED MEMORY MULTIPROCESSORS

M M ••• M

Buses,
Interconnection Network(IN) Multistage IN,
Crossbar Switch

P P ••• P

Characteristics
All processors have equally direct access to
one large memory address space
Example systems
Bus and cache-based systems
- Sequent Balance, Encore Multimax
Multistage IN-based systems
- Ultracomputer, Butterfly, RP3, HEP
Crossbar switch-based systems
- C.mmp, Alliant FX/8
Limitations
Memory access latency
Hot spot problem
Computer Organization Computer Architecture
 Pipelining and Vector Processing Parallel Processing
223

MESSAGE-PASSING MULTICOMPUTER
Message-Passing Network Point-to-point connections

P P ••• P

M M ••• M

Characteristics
- Interconnected computers
- Each processor has its own memory, and
communicate via message-passing

Example systems
- Tree structure: Teradata, DADO
- Mesh-connected: Rediflow, Series 2010, J-Machine
- Hypercube: Cosmic Cube, iPSC, NCUBE, FPS T Series, Mark III

Limitations
- Communication overhead
- Hard to programming
Computer Organization Computer Architecture
 Pipelining and Vector Processing Pipelining
224

PIPELINING
A technique of decomposing a sequential process
into suboperations, with each subprocess being
executed in a partial dedicated segment that
operates concurrently with all other segments.
Ai * Bi + Ci for i = 1, 2, 3, ... , 7
Ai Bi Memory
Ci
Segment 1
R1 R2

Multiplier
Segment 2
R3 R4

Adder
Segment 3

R5

R1  Ai, R2  Bi Load Ai and Bi

R3  R1 * R2, R4  Ci Multiply and load Ci
R5  R3 + R4 Add
Computer Organization Computer Architecture
 Pipelining and Vector Processing Pipelining
225

OPERATIONS IN EACH PIPELINE STAGE

Clock
Pulse Segment 1 Segment 2 Segment 3

Number R1 R2 R3 R4 R5
1 A1 B1
2 A2 B2 A1 * B1 C1
3 A3 B3 A2 * B2 C2 A1 * B1 + C1
4 A4 B4 A3 * B3 C3 A2 * B2 + C2
5 A5 B5 A4 * B4 C4 A3 * B3 + C3
6 A6 B6 A5 * B5 C5 A4 * B4 + C4
7 A7 B7 A6 * B6 C6 A5 * B5 + C5
8 A7 * B7 C7 A6 * B6 + C6
9 A7 * B7 + C7

Computer Organization Computer Architecture

 Pipelining and Vector Processing Pipelining
226

GENERAL PIPELINE
General Structure of a 4-Segment Pipeline
Clock

Input S1 R1 S2 R2 S3 R3 S4 R4

Space-Time Diagram
1 2 3 4 5 6 7 8 9
Clock cycles
Segment 1 T1 T2 T3 T4 T5 T6

2 T1 T2 T3 T4 T5 T6

3 T1 T2 T3 T4 T5 T6

4 T1 T2 T3 T4 T5 T6

Computer Organization Computer Architecture

 Pipelining and Vector Processing Pipelining
227

PIPELINE SPEEDUP
n: Number of tasks to be performed

Conventional Machine (Non-Pipelined)

tn: Clock cycle
: Time required to complete the n tasks
 = n * tn

Pipelined Machine (k stages)

tp: Clock cycle (time to complete each suboperation)
: Time required to complete the n tasks
 = (k + n - 1) * tp

Speedup
Sk: Speedup

Sk = n*tn / (k + n - 1)*tp
tn
lim Sk = ( = k, if tn = k * tp )
n tp

Computer Organization Computer Architecture

 Pipelining and Vector Processing Pipelining
228

PIPELINE AND MULTIPLE FUNCTION UNITS

Example
- 4-stage pipeline
- subopertion in each stage; tp = 20nS
- 100 tasks to be executed
- 1 task in non-pipelined system; 20*4 = 80nS

Pipelined System
(k + n - 1)*tp = (4 + 99) * 20 = 2060nS

Non-Pipelined System
n*k*tp = 100 * 80 = 8000nS

Speedup
Sk = 8000 / 2060 = 3.88

4-Stage Pipeline is basically identical to the system

Ii I i+1 I i+2 I i+3
with 4 identical function units

Multiple Functional Units P1 P2 P3 P4

Computer Organization Computer Architecture

 Pipelining and Vector Processing Arithmetic Pipeline
229

ARITHMETIC PIPELINE
Floating-point adder Exponents
a b
Mantissas
A B
X = A x 2a
Y = B x 2b
R R

[1] Compare the exponents Compare Difference

[2] Align the mantissa Segment 1: exponents
[3] Add/sub the mantissa by subtraction
[4] Normalize the result

Segment 2: Choose exponent Align mantissa

Segment 3: Add or subtract

mantissas

R R

Segment 4: Adjust Normalize

exponent result

R R

Computer Organization Computer Architecture

 Pipelining and Vector Processing Arithmetic Pipeline
230

4-STAGE FLOATING POINT ADDER

A = a x 2p B = b x 2q
p a q b

Stages: Other
Exponent fraction Fraction
S1 subtractor selector
Fraction with min(p,q)
r = max(p,q)
Right shifter
t = |p - q|

S2 Fraction
adder
r c

Leading zero
S3 counter
c
Left shifter
r

d
Exponent
S4 adder

s d
C = A + B = c x 2 r = d x 2s
(r = max (p,q), 0.5  d < 1)

Computer Organization Computer Architecture

 Pipelining and Vector Processing Instruction Pipeline
231

INSTRUCTION CYCLE
Six Phases* in an Instruction Cycle
[1] Fetch an instruction from memory
[2] Decode the instruction
[3] Calculate the effective address of the operand
[4] Fetch the operands from memory
[5] Execute the operation
[6] Store the result in the proper place

* Some instructions skip some phases

* Effective address calculation can be done in
the part of the decoding phase
* Storage of the operation result into a register
is done automatically in the execution phase

==> 4-Stage Pipeline

[1] FI: Fetch an instruction from memory

[2] DA: Decode the instruction and calculate
the effective address of the operand
[3] FO: Fetch the operand
[4] EX: Execute the operation

Computer Organization Computer Architecture

 Pipelining and Vector Processing Instruction Pipeline
232

INSTRUCTION PIPELINE

Execution of Three Instructions in a 4-Stage Pipeline

Conventional

i FI DA FO EX

i+1 FI DA FO EX

i+2 FI DA FO EX

Pipelined

i FI DA FO EX
i+1 FI DA FO EX
i+2 FI DA FO EX

Computer Organization Computer Architecture

 Pipelining and Vector Processing Instruction Pipeline
233

INSTRUCTION EXECUTION IN A 4-STAGE PIPELINE

Segment1: Fetch instruction

from memory

Decode instruction
Segment2: and calculate
effective address

yes Branch?
no
Fetch operand
Segment3: from memory

Segment4: Execute instruction

Interrupt yes
Interrupt?
handling
no
Update PC

Empty pipe
Step: 1 2 3 4 5 6 7 8 9 10 11 12 13
Instruction 1 FI DA FO EX
2 FI DA FO EX
(Branch) 3 FI DA FO EX
4 FI FI DA FO EX
5 FI DA FO EX
6 FI DA FO EX
7 FI DA FO EX

Computer Organization Computer Architecture

 Pipelining and Vector Processing Instruction Pipeline
234

MAJOR HAZARDS IN PIPELINED EXECUTION

Structural hazards(Resource Conflicts)
Hardware Resources required by the instructions in
simultaneous overlapped execution cannot be met
Data hazards (Data Dependency Conflicts)
An instruction scheduled to be executed in the pipeline requires the
result of a previous instruction, which is not yet available
Data dependency
R1 <- B + C ADD DA B,C +

R1 <- R1 + 1
INC DA bubble R1 +1

Control hazards
Branches and other instructions that change the PC
make the fetch of the next instruction to be delayed
JMP ID PC + PC Branch address dependency

bubble IF ID OF OE OS

Hazards in pipelines may make it Pipeline Interlock:

necessary to stall the pipeline Detect Hazards Stall until it is cleared

Computer Organization Computer Architecture

 Pipelining and Vector Processing Instruction Pipeline
235

STRUCTURAL HAZARDS
Structural Hazards
Occur when some resource has not been
duplicated enough to allow all combinations
of instructions in the pipeline to execute

Example: With one memory-port, a data and an instruction fetch

cannot be initiated in the same clock
i FI DA FO EX

i+1 FI DA FO EX

i+2 stall stall FI DA FO EX

The Pipeline is stalled for a structural hazard

<- Two Loads with one port memory
-> Two-port memory will serve without stall

Computer Organization Computer Architecture

 Pipelining and Vector Processing Instruction Pipeline
236

DATA HAZARDS
Data Hazards

Occurs when the execution of an instruction

depends on the results of a previous instruction
ADD R1, R2, R3
SUB R4, R1, R5
Data hazard can be dealt with either hardware
techniques or software technique
Hardware Technique

Interlock
- hardware detects the data dependencies and delays the scheduling
of the dependent instruction by stalling enough clock cycles
Forwarding (bypassing, short-circuiting)
- Accomplished by a data path that routes a value from a source
(usually an ALU) to a user, bypassing a designated register. This
allows the value to be produced to be used at an earlier stage in the
pipeline than would otherwise be possible

Software Technique
Instruction Scheduling(compiler) for delayed load
Computer Organization Computer Architecture
 Pipelining and Vector Processing Instruction Pipeline
237

FORWARDING HARDWARE

Example: Register
file

ADD R1, R2, R3

SUB R4, R1, R5
MUX MUX
3-stage Pipeline Bypass
path
Result
I: Instruction Fetch write bus
A: Decode, Read Registers, ALU

ALU Operations
E: Write the result to the
destination register R4

ALU result buffer

ADD I A E

SUB I A E Without Bypassing

SUB I A E With Bypassing

Computer Organization Computer Architecture

 Pipelining and Vector Processing Instruction Pipeline
238

INSTRUCTION SCHEDULING
a = b + c;
d = e - f;

Unscheduled code: Scheduled Code:

LW Rb, b LW Rb, b
LW Rc, c LW Rc, c
ADD Ra, Rb, Rc LW Re, e
SW a, Ra ADD Ra, Rb, Rc
LW Re, e LW Rf, f
LW Rf, f SW a, Ra
SUB Rd, Re, Rf SUB Rd, Re, Rf
SW d, Rd SW d, Rd

Delayed Load
A load requiring that the following instruction not use its result

Computer Organization Computer Architecture

 Pipelining and Vector Processing Instruction Pipeline
239

CONTROL HAZARDS
Branch Instructions

- Branch target address is not known until

the branch instruction is completed
Branch
Instruction FI DA FO EX

Next
Instruction FI DA FO EX

Target address available

- Stall -> waste of cycle times

Dealing with Control Hazards

* Prefetch Target Instruction

* Branch Target Buffer
* Loop Buffer
* Branch Prediction
* Delayed Branch

Computer Organization Computer Architecture

 Pipelining and Vector Processing Instruction Pipeline
240

CONTROL HAZARDS
Prefetch Target Instruction
– Fetch instructions in both streams, branch not taken and branch taken
– Both are saved until branch branch is executed. Then, select the right
instruction stream and discard the wrong stream
Branch Target Buffer(BTB; Associative Memory)
– Entry: Addr of previously executed branches; Target instruction
and the next few instructions
– When fetching an instruction, search BTB.
– If found, fetch the instruction stream in BTB;
– If not, new stream is fetched and update BTB
Loop Buffer(High Speed Register file)
– Storage of entire loop that allows to execute a loop without accessing memory
Branch Prediction
– Guessing the branch condition, and fetch an instruction stream based on
the guess. Correct guess eliminates the branch penalty
Delayed Branch
– Compiler detects the branch and rearranges the instruction sequence
by inserting useful instructions that keep the pipeline busy
in the presence of a branch instruction

Computer Organization Computer Architecture

 Pipelining and Vector Processing RISC Pipeline
241

RISC PIPELINE
RISC
- Machine with a very fast clock cycle that
executes at the rate of one instruction per cycle
<- Simple Instruction Set
Fixed Length Instruction Format
Register-to-Register Operations

Instruction Cycles of Three-Stage Instruction Pipeline

Data Manipulation Instructions
I: Instruction Fetch
A: Decode, Read Registers, ALU Operations
E: Write a Register

Load and Store Instructions

I: Instruction Fetch
A: Decode, Evaluate Effective Address
E: Register-to-Memory or Memory-to-Register

Program Control Instructions

I: Instruction Fetch
A: Decode, Evaluate Branch Address
E: Write Register(PC)
Computer Organization Computer Architecture
 Pipelining and Vector Processing RISC Pipeline
242

DELAYED LOAD
LOAD: R1  M[address 1]
LOAD: R2  M[address 2]
ADD: R3  R1 + R2
STORE: M[address 3]  R3
Three-segment pipeline timing
Pipeline timing with data conflict

clock cycle 1 2 3 4 5 6
Load R1 I A E
Load R2 I A E
Add R1+R2 I A E
Store R3 I A E

Pipeline timing with delayed load

clock cycle 1 2 3 4 5 6 7
Load R1 I A E
The data dependency is taken
Load R2 I A E care by the compiler rather
NOP I A E than the hardware
Add R1+R2 I A E
Store R3 I A E

Computer Organization Computer Architecture

 Pipelining and Vector Processing RISC Pipeline
243

DELAYED BRANCH
Compiler analyzes the instructions before and after
the branch and rearranges the program sequence by
inserting useful instructions in the delay steps

Using no-operation instructions

Clock cycles: 1 2 3 4 5 6 7 8 9 10
1. Load I A E
2. Increment I A E
3. Add I A E
4. Subtract I A E
5. Branch to X I A E
6. NOP I A E
7. NOP I A E
8. Instr. in X I A E

Rearranging the instructions

Clock cycles: 1 2 3 4 5 6 7 8
1. Load I A E
2. Increment I A E
3. Branch to X I A E
4. Add I A E
5. Subtract I A E
6. Instr. in X I A E

Computer Organization Computer Architecture

 Pipelining and Vector Processing Vector Processing
244

VECTOR PROCESSING
Vector Processing Applications
• Problems that can be efficiently formulated in terms of vectors
– Long-range weather forecasting
– Petroleum explorations
– Seismic data analysis
– Medical diagnosis
– Aerodynamics and space flight simulations
– Artificial intelligence and expert systems
– Mapping the human genome
– Image processing

Vector Processor (computer)

Ability to process vectors, and related data structures such as matrices
and multi-dimensional arrays, much faster than conventional computers

Vector Processors may also be pipelined

Computer Organization Computer Architecture

 Pipelining and Vector Processing Vector Processing
245

VECTOR PROGRAMMING

DO 20 I = 1, 100
20 C(I) = B(I) + A(I)

Conventional computer

Initialize I = 0
20 Read A(I)
Read B(I)
Store C(I) = A(I) + B(I)
Increment I = i + 1
If I  100 goto 20

Vector computer

C(1:100) = A(1:100) + B(1:100)

Computer Organization Computer Architecture

 Pipelining and Vector Processing Vector Processing
246

VECTOR INSTRUCTIONS
f1: V  V
f2: V  S
f3: V x V  V V: Vector operand
f4: V x S  V S: Scalar operand

Type Mnemonic Description (I = 1, ..., n)

f1 VSQR Vector square root B(I)  SQR(A(I))

VSIN Vector sine B(I)  sin(A(I))
VCOM Vector complement A(I)  A(I)
f2 VSUM Vector summation S   A(I)
VMAX Vector maximum S  max{A(I)}
f3 VADD Vector add C(I)  A(I) + B(I)
VMPY Vector multiply C(I)  A(I) * B(I)
VAND Vector AND C(I)  A(I) . B(I)
VLAR Vector larger C(I)  max(A(I),B(I))
VTGE Vector test > C(I)  0 if A(I) < B(I)
C(I)  1 if A(I) > B(I)
f4 SADD Vector-scalar add B(I)  S + A(I)
SDIV Vector-scalar divide B(I)  A(I) / S

Computer Organization Computer Architecture

 Pipelining and Vector Processing Vector Processing
247

VECTOR INSTRUCTION FORMAT

Vector Instruction Format

Operation Base address Base address Base address Vector
code source 1 source 2 destination length

Pipeline for Inner Product

Source
A

Source Multiplier Adder

B pipeline pipeline

Computer Organization Computer Architecture

 Pipelining and Vector Processing Vector Processing
248

MULTIPLE MEMORY MODULE AND INTERLEAVING

Multiple Module Memory

Address bus
M0 M1 M2 M3

AR AR AR AR

Memory Memory Memory Memory

array array array array

DR DR DR DR

Data bus

Address Interleaving

Different sets of addresses are assigned to

different memory modules

Computer Organization Computer Architecture

 249

UNIT-5 The Memory System

Connection of the memory to the processor

Computer Organization Computer Architecture
 250

Semiconductor RAM Memories

1. Internal Organization of Memory Chips

Organization of bit cells in a memory chip

Computer Organization Computer Architecture
 251

Organization of a 1K × 1 memory chip

Computer Organization Computer Architecture
 252

2. Static Memories

A static RAM cell

Read Operation
Write Operation
Computer Organization Computer Architecture
 253

CMOS Cell

An example of a CMOS memory cell

Computer Organization Computer Architecture

 254

3. Asynchronous Dynamic RAMs

A single-transistor dynamic memory cell

Computer Organization Computer Architecture

 255

Internal organization of a 32M × 8 dynamic memory chip

Computer Organization Computer Architecture
 256

4. Synchronous DRAMs

Synchronous DRAM

Computer Organization Computer Architecture

 257

A burst read of length 4 in an SDRAM

Computer Organization Computer Architecture

 258

5. Structure of Larger Memories

Organization of a
2M × 32 memory
module using
512K × 8 static
memory chips
Computer Organization Computer Architecture
 259

Read-only Memories

A ROM cell

ROM
PROM
EPROM
EEPROM
FLASH MEMORY

Computer Organization Computer Architecture

 260

Cache Memories

Use of a cache memory

1. Mapping Functions:
 Direct Mapping
 Associative Mapping
 Set-Associative Mapping

Computer Organization Computer Architecture

 261

Direct-mapped cache

Computer Organization Computer Architecture

 262

Associative-mapped cache

Computer Organization Computer Architecture

 263

Set-associative-mapped cache with two blocks per set

Computer Organization Computer Architecture

 264

2.Replacement Algorithms
3.Examples of Mapping Techniques

An array stored in the main memory

Computer Organization Computer Architecture
 265

• Figure gives the structure of a program that

corresponds to this task.
• We use the variables SUM and AVE to hold the sum
and average values, respectively.
• These variables, as well as index variables i and j, are
held in processor registers during the computation

Task for example

Computer Organization Computer Architecture

 266

Contents of a direct-mapped data cache

Computer Organization Computer Architecture
 267

Contents of an associative Contents of a set-associative

-mapped data cache -mapped data cache
Computer Organization Computer Architecture
 268

Memory Hierarchy

Computer Organization Computer Architecture

 269

Performance Considerations
1. Interleaving
2. Hit Rate and Miss Penalty
3. Caches on the Processor Chip
4. Other Enhancements:
 Write Buffer
 Prefetching
 Lookup-Free cache

Computer Organization Computer Architecture

 270

Virtual Memory

Virtual memory organization

Computer Organization Computer Architecture
 271

Address Translation

Virtual-memory address translation

Computer Organization Computer Architecture
 272

Use of an associative-mapped TLB

Computer Organization Computer Architecture

 273

Secondary Storage
Magnetic Hard Disks:

Magnetic disk principles

Computer Organization Computer Architecture
 274

Magnetic disk principles

Computer Organization Computer Architecture

 275

Organization and Accessing of Data on a Disk

Organization of one surface of a disk

Computer Organization Computer Architecture
 276

Optical Disks
CD Technology: Optical disk

Computer Organization Computer Architecture

 277

Optical disk

CD-ROM
CD-Recordables
CD-ReWritables
DVD Technology
DVD-RAM

Computer Organization Computer Architecture

 278

Magnetic Tape Systems

Organization of data on magnetic tape

Computer Organization Computer Architecture

 279

Unit4 -- Input/Output Organization

A computer system

Computer Organization Computer Architecture

 280

The connection for processor, keyboard, and display

Computer Organization Computer Architecture

 281

Computer Organization Computer Architecture

 282

Registers in the keyboard and display interfaces

Computer Organization Computer Architecture
 283

Computer Organization Computer Architecture

 284

Computer Organization Computer Architecture

 285

Computer Organization Computer Architecture

 286

Computer Organization Computer Architecture

 287

Computer Organization Computer Architecture

 288

 Whenever an interrupt request arrives at the processor,

and processor interrupts are enabled, the processor will
automatically:

1. Save the contents of the program counter, either in a

processor register that holds the return address or on the
processor stack.

2. Save the contents of the status register PS by transferring

them into the IPS register, and clear the IE bit in the PS.

3. Load the address ILOC into the program counter.

Computer Organization Computer Architecture

 289

The Main program has to initialize the interrupt process as

follows:

1. Load the address LINE into a memory location PNTR.

The interrupt-service routine will use this location as a
pointer to store the input characters in the memory.
2. Enable interrupts in the keyboard interface by setting to
1 the KIE bit in the KBD_CONT register.
3. Enable the processor to accept interrupts from the
keyboard by setting to 1 the KBD bit in its control
register IENABLE.
4. Enable the processor to respond to interrupts in general
by setting to 1 the IE bit in the processor status register,
PS.
Computer Organization Computer Architecture
 290

Direct Memory Access

Computer Organization Computer Architecture

 291

Computer Organization Computer Architecture

 292

Bus Arbitration
Bus Master: The device that is allowed to initiate data transfers on bus
at any given time is called the bus master.
1. Centralized
2. Decentralized

Computer Organization Computer Architecture

 293

Computer Organization Computer Architecture

 294

Computer Organization Computer Architecture

 295

BUSES
Synchronous Bus

Computer Organization Computer Architecture

 296

Computer Organization Computer Architecture

 297

Computer Organization Computer Architecture

 298

Asynchronous Bus

Computer Organization Computer Architecture

 299

Computer Organization Computer Architecture

 300

Interface Circuits
Parallel Port

Computer Organization Computer Architecture

 301

Computer Organization Computer Architecture

 302

Computer Organization Computer Architecture

 303

Computer Organization Computer Architecture

 304

Computer Organization Computer Architecture

 305

Computer Organization Computer Architecture

 306

Computer Organization Computer Architecture

 307

A PARALLEL PORT INTERFACE FOR THE BUS, STATE DIAGRAM FOR THE TIMING LOGIC
Computer Organization Computer Architecture
 308

Computer Organization Computer Architecture

 309

Serial Port

Computer Organization Computer Architecture

 310

Standard I/O Interfaces

Computer Organization Computer Architecture

 311

Peripheral Component Interconnect (PCI)

Computer Organization Computer Architecture

 312

Computer Organization Computer Architecture

 313

Computer Organization Computer Architecture

 314

Computer Organization Computer Architecture

 315

Small Computer System Interface 

Computer Organization Computer Architecture

 316

Computer Organization Computer Architecture

 317

Universal Serial Bus

Computer Organization Computer Architecture

 318

Computer Organization Computer Architecture

 319

Computer Organization Computer Architecture

 320

Computer Organization Computer Architecture

 321

Computer Organization Computer Architecture