+

William Stallings
Computer Organization
and Architecture
9th Edition
+
Chapter 3
A Top-Level View of Computer
Function and Interconnection
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Computer Components
 Contemporary computer designs are based on concepts developed by
John von Neumann at the Institute for Advanced Studies, Princeton

 Referred to as the von Neumann architecture and is based on three

key concepts:
 Data and instructions are stored in a single read-write memory
 The contents of this memory are addressable by location, without regard to
the type of data contained there
 Execution occurs in a sequential fashion (unless explicitly modified) from
one instruction to the next

 Hardwired program
 The result of the process of connecting the various components in the
desired configuration
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Hardware
and Software
Approaches
 Software
• A sequence of codes or instructions Software
• Part of the hardware interprets each instruction and
generates control signals
• Provide a new sequence of codes for each new program
instead of rewiring the hardware
Major components:
• CPU I/O
• Instruction interpreter Components
• Module of general-purpose arithmetic and logic
functions
• I/O Components
+ Input module
•
• Contains basic components for accepting data and
instructions and converting them into an internal form
of signals usable by the system
• Output module
• Means of reporting results
 Memory address Memory buffer
MEMORY
register (MAR) register (MBR)
• Specifies the address • Contains the data to
in memory for the be written into
next read or write memory or receives
the data read from
memory

MAR

I/O address I/O buffer

register (I/OAR) register (I/OBR)
+ • Specifies a • Used for the
particular I/O device exchange of data
between an I/O
module and the CPU
MBR
 Computer
Components:
Top Level
View
+
Basic Instruction Cycle
+
Fetch Cycle
 At the beginning of each instruction cycle the processor fetches an
instruction from memory

 The program counter (PC) holds the address of the instruction to be

fetched next

 The processor increments the PC after each instruction fetch so that

it will fetch the next instruction in sequence

 The fetched instruction is loaded into the instruction register (IR)

 The processor interprets the instruction and performs the required

action
Action Categories

• Data transferred from processor to • Data transferred to or

memory or from memory to processor from a peripheral device
by transferring between
the processor and an I/O
module

Processor- Processor-
memory I/O

Data
Control processing

• An instruction may specify that the • The processor may

sequence of execution be altered perform some arithmetic
or logic operation on data
+
+
Example
of
Program
Execution
+
Instruction Cycle State Diagram

How a CPU Works

+
Classes of Interrupts
Program Flow Control
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Transfer of Control via Interrupts
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Instruction Cycle With Interrupts
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Program
Timing:
Short I/O
Wait
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Program
Timing:
Long I/O
Wait
Instruction Cycle State Diagram
With Interrupts
 Transfer of
Control

Multiple
Interrupts

+
+ Time Sequence of Ex
Multiple Interrupts am
ple
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I/O Function
 I/O module can exchange data directly with the processor

 Processor can read data from or write data to an I/O module

 Processor identifies a specific device that is controlled by a particular I/O
module
 I/O instructions rather than memory referencing instructions

 In some cases it is desirable to allow I/O exchanges to occur directly

with memory
 The processor grants to an I/O module the authority to read from or write
to memory so that the I/O memory transfer can occur without tying up the
processor
 The I/O module issues read or write commands to memory relieving the
processor of responsibility for the exchange
 This operation is known as direct memory access (DMA)
+

Bus system on a Main board

+ Computer
Modules
The interconnection structure must support the following
types of transfers:

Memory Processor I/O to or

I/O to Processor
to to from
processor to I/O
processor memory memory

An I/O
module is
allowed to
exchange
Processor
Processor data directly
reads an Processor Processor
reads data with memory
instruction writes a unit sends data to
from an I/O without
or a unit of of data to the I/O
device via an going
data from memory device
I/O module through the
memory
processor
using direct
memory
access
A communication pathway Signals transmitted by any one
connecting two or more devices device are available for reception
• Key characteristic is that it is a shared
transmission medium
by all other devices attached to
the bus Bus
Inter
• If two devices transmit during the same
time period their signals will overlap
and become garbled

conn
Typically consists of multiple
ectio
n
communication lines Computer systems contain a
• Each line is capable of transmitting number of different buses that
signals representing binary 1 and provide pathways between
binary 0 components at various levels of
the computer system hierarchy

System bus
• A bus that connects major computer
components (processor, memory, I/O)
The most common computer
interconnection structures are
based on the use of one or more
system buses
Data Bus
 Data lines that provide a path for moving data among system
modules

 May consist of 32, 64, 128, or more separate lines

 The number of lines is referred to as the width of the data bus

 The number of lines determines how many bits can be transferred at a

time

 The width of the data bus

is a key factor in
determining overall
system performance
+ Address Bus Control Bus

 Used to designate the source or  Used to control the access and the
destination of the data on the data bus use of the data and address lines
 If the processor wishes to read a
word of data from memory it puts
 Because the data and address lines
the address of the desired word on are shared by all components there
the address lines must be a means of controlling their
use
 Width determines the maximum
possible memory capacity of the  Control signals transmit both
system command and timing information
among system modules
 Also used to address I/O ports
 Timing signals indicate the validity
 The higher order bits are used to
of data and address information
select a particular module on the
bus and the lower order bits select  Command signals specify operations
a memory location or I/O port
to be performed
within the module
Bus Interconnection Scheme
+
Elements of Bus Design
 Timing of
Synchronous
Bus Operations
 Timing of
Asynchronous
Bus
Operations
+ Summary A Top-Level View of
Computer Function and
Interconnection
Chapter 3
 Point-to-point interconnect
 Computer components
 QPI physical layer
 Computer function
 QPI link layer
 Instruction fetch and execute
 QPI routing layer
 Interrupts
 QPI protocol layer
 I/O function
 Interconnection structures  PCI express
 Bus interconnection  PCI physical and logical
 Bus structure architecture
 Multiple bus hierarchies  PCIe physical layer
 Elements of bus design  PCIe transaction layer
 PCIe data link layer
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Keyterm

bus disabled interrupt

system bus interrupt handler
address bus interrupt service routine
address lines (ISR)
bus width execute cycle
data bus fetch cycle
data lines instruction cycle
control lines peripheral component
synchronous timing arbitration
asynchronous timing centralized arbitration
interrupt distributed arbitration
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Homework

3.3 3.7 3.12 3.14 3.15 3.17

Recommended reading:

How a CPU Works