A seminar on…..

Very Large Scale Integration

 Content
Introduction-
History, Need N Evolution
Seminar on VLSI

Description-
VLSI Design Flow
Concept of Regularity, Modularity n Locality
VLSI Design Styles
VLSI Fabrication Techniques
VLSI Design Rules
Advantages/Disadvantages
Future Aspects
 Introduction
Definition:
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Very-large-scale integration (VLSI) is the

process of creating integrated circuits by
combining thousands of transitor-based
circuits into a single chip.
 Why Integration?

Perfection of circuits
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Tyranny of numbers
Information Rate and Bandwidth
Personalization
Portability

Therefore complexity…….
 The Beginning
In the summer of 1958 Jack Kilby at
Texas Instruments found a solution to
the problem of integration. . Kilby's idea
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was to make all the components and the

chip out of the same block (monolith) of
semiconductor material.
Later, Robert Noyce came up another
Jack S Kilby
idea which mainly solved the problem of
Photo: Texas Instruments
interconnecting all the components on
the chip. This was done by adding the
metal as a final layer and then removing
some of it so that the wires needed to
connect the components were formed.
Kilbys first chip
Photo: Texas Instruments
 Evolution
ERA DATE COMPLEXITY
(no. of logic blocks per chip)
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Single transistor 1959 less than 1

Unit logic (one gate) 1960 1

Multi-function 1962 2-4

Complex function 1964 5-20

Medium Scale Integration (MSI) 1967 20-200

Large Scale Integration (LSI) 1972 200-2000

Very Large Scale Integration (VLSI) 1978 2000-20000

Ultra Large Scale Integration (ULSI) 1989 20000-?

 Description
The VLSI Design Flow
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Design Process:
The design process starts with a given set of
requirements. Initial design is developed and
tested against these requirements.
 Continued….

Design Flow:
Y-chart shown in Figure
illustrates a design flow for
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most logic chips, using design

activities on three different
axes (domains) which
resemble the letter Y, namely:
-Behavioral domain,
-Structural domain,
-Geometrical layout
domain.

Typical VLSI design flow in three domains (Y-

chart representation).
 Continued….

A more simplified view of VLSI design flow

•Here, the design process has been

described in linear fashion for
simplicity, in reality there are many
iterations back and forth, especially
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between any two neighboring steps,

and occasionally even remotely
separated pairs.

•Although top-down design flow

provides an excellent design process
control, in reality, there is no truly
unidirectional top-down design flow.
Both top-down and bottom-up
approaches have to be combined.
 Design Hierarchy

The use of hierarchy or “divide and

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conquer” technique involves dividing a

module into sub- modules and then
repeating this operation on the sub-
modules until the complexity of the
smaller parts becomes manageable.
 Continued….

Structural decomposition of a four-bit adder circuit;

showing the hierarchy down to gate level
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Hierarchical decomposition
of a four-bit adder in
physical (geometrical)
description domain
 Concepts of Regularity, Modularity
and Locality
Regularity: This means that the hierarchical decomposition of a large system
should result in not only simple, but also similar blocks, as much as possible.
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.
 Concepts of Regularity,
Modularity and Locality
Modularity: Modularity in design means that the various functional
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blocks which make up the larger system must have well-defined

functions and interfaces

  Locality: By defining well-characterized interfaces for each module in

the system, we effectively ensure that the internals of each module
become unimportant to the exterior modules. Internal details remain at
the local level
 VLSI Design Styles
Field Programmable Gate Array (FPGA)
A field-programmable gate array is a semiconductor device
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containing programmable logic components called "logic blocks",

and programmable interconnects. Logic blocks can be programmed
to perform the function of basic logic gates such as AND, and XOR,
or more complex combinational functions such as decoders or
simple mathematical functions. In most FPGAs, the logic blocks also
include memory elements, which may be simple flip-flops or more
complete blocks of memory.

Logic Block Pin Locations Typical logic block

 PS : The largest advantage of FPGA-based design is the very
short turn-around time

Switch box topology

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 Gate Array Design
A gate array circuit is a prefabricated silicon chip circuit with no
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particular function in which transistors, standard NAND or NOR logic

gates, and other active devices are placed at regular predefined
positions and manufactured on a wafer, usually called a master slice.
Creation of a circuit with a specified function is accomplished by
adding a final surface layer or layers of metal interconnects to the
chips on the master slice late in the manufacturing process, joining
these elements to allow the function of the chip to be customized as
desired. This layer is analogous to the copper layer(s) of a printed
circuit board PCB.
 Standard-Cells Based Design
In this design style, all of the commonly used logic cells are
developed, characterized, and stored in a standard cell library.
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A typical library may contain a few hundred cells including

inverters, NAND gates, NOR gates, complex AOI, OAI gates,
D-latches, and flip-flops. Each gate type can have multiple
implementations to provide adequate driving capability for
different fanouts.

After chip logic design is done using standard cells in the library,
the most challenging task is to place individual cells into rows
and interconnect them in a way that meets stringent design
goals in circuit speed, chip area, and power consumption. Many
advanced CAD tools for place-and-route have been developed
and used to achieve such goals.
 Full Custom Design
Although the standard-cells based design is often called full
custom design, in a strict sense, it is somewhat less than fully
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custom since the cells are pre-designed for general use and the
same cells are utilized in many different chip designs. In a fuller
custom design, the entire mask design is done anew without
use of any library.
The most rigorous full custom design can be the design of a
memory cell, be it static or dynamic. Since the same layout design
is replicated, there would not be any alternative to high density
memory chip design.
In digital CMOS VLSI, full-custom design is rarely used due to
the high labor cost.
 Fabrication Process

CMOS requires both nMOS and pMOS

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be built on same chip substrate

CMOS fabrication can be done by three
major methods:
1. n-Well CMOS fabrication.
2. twin-tub CMOS
3. Silicon-on-insulator(SOI) CMOS process
 Fabrication Process flow
Create n-well regions &
Channel-stop regions
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Grow field oxide

& gate oxide

Deposit and pattern

Polysilicon layer

Implant source &drain

regions, substrate contacts

create contact
windows,deposit
& pattern metal layer
 Fabrication Process
LITHOGRAPHY-The process used to transfer a pattern to layer
on the chip.
The CMOS n-well process
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 Continued….

The process is carried out in below specified order

 p-type Silicon substrate is moderately doped (1015 cm3 )

Oxide layer is grown on entire surface.
n-well region is created.
The active areas for nMOS & pMOS are defined.
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 Continued….

 Field oxide & Gate oxide are grown

 The polysilicon layer is deposited using CVD &patterned
 n & p regions and ohmic contacts are implanted
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 Continued….

 Insulating SiO2 layer is deposited using CVD

 The contacts are etched away to expose contact window
 The interconnections are completed using metal layer
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 Continued….

 The passivation layer is deposited over entire chip except

wire-bounding areas .
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 Continued….

Advanced fabrication technologies

1. TWIN-TUB(TWIN-WELL) CMOS PROCESS

2. SILICON-ON-INSULATOR CMOS PROCESS
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1. TWIN-TUB CMOS PROCESS

 Provides separate optimization of nMOS & cMOS transistors

 Threshold voltage, body effect ,& channel transconductance can
be tuned independently
 Avoids unbalanced drain problems
 Continued….
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Cross-section of nMOS & pMOS in TWIN-TUB process

 Continued….

2. SILICON-ON-INSULATOR PROCESS

 Uses insulating substrate to improve process

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characteristics.
 Allows creation of independent , completely isolated
nMOS & pMOS transistor
 It has higher integration density .
 complete avoidance of latch-up problem.
 Layout Design Rules

The physical mask layout of any circuit to

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be manufactured using a particular

process must conform to a set of
geometric constraints or rules, which are
generally called layout design rules
 Continued…. RULE NO. DESCRIPTION L-Rule

R1 Minimum active area width 2L

R2 Minimum active area spacing 3L

R3 Minimum poly width 2L

R4 Minimum poly spacing 2L

R5 Minimum gate extension of poly over active 2L

R6 Minimum poly-active edge spacing 1L

(poly outside active area)

R7 Minimum poly-active edge spacing 31

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(poly inside active area)

R8 Minimum metal width 3L

R9 Minimum metal spacing 3L

R10 Poly contact size 2L

R11 Minimum poly contact spacing 2L

R12 Minimum poly contact to poly edge spacing 1L

R13 Minimum poly contact to metal edge spacing 1L

R14 Minimum poly contact to active edge spacing 3L

R15 Active contact size 2L

R16 Minimum active contact spacing 2L

(on the same active region)

R17 Minimum active contact to active edge spacing 1L

R18 Minimum active contact to metal edge spacing 1L

Illustration of some of the R19 Minimum active contact to poly edge spacing 3L
typical layout design rules listed R20 Minimum active contact spacing 6L
above (on different active regions)
 Advantages

Less area/volume and therefore,

compactness
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Less power consumption

Less testing requirements at system level
Higher reliability, mainly due to improved
on-chip interconnects
Higher speed, due to significantly reduced
interconnection length
Significant cost savings
 Disadvantages

However, ICs with nanometer-scale

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devices are not without their problems,

principal among which is leakage current
although these problems are not
insurmountable and will likely be solved.
 Future Scope

ULSI (Ultra Large Scale Integration)

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WSI(Wafer Scale Integration)

SoC or SOC(System-on-Chip)
3D-IC(Three Diementional IC)
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