General Presentation

UNIFEID POWER FORMAT

Kiran .N
CGB0910003
M. Sc. (Engg.) in VLSI System Design

Module leader: Selva Kumar .R

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 Session Objectives
After completing this session, we will be able to:
• Know more about power issues for designs
• Know more about steps taken to reduce power consumption
in designs
• Know what UPF is and how it helps in reducing power
consumption

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 Session Topics
• Power issues

• Role of EDA tools in power optimization

• Introduction to UPF standard

• Working of UPF

• Advantages of UPF in designs

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 Power Issues
As consumer electronic goods are becoming more and more
compact there is an increasing need to make them power efficient.
The design engineers are working on different power reduction
techniques to overcome the battery life constraint.

Its draining away!!

Where is my charger???????
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 Power Issues cont..
As we scale down the level of Vdd also has to reduce because the
power dissipation is directly proportional to Vdd2 .

As we reduce the Vdd the effects of leakage currents increase. The
ITRS (International Technology Roadmap for Semiconductors)
released a study that indicated that at the 45-nm node, the ITRS
predicts, dynamic-power and leakage-power density will increase to
2 and 6.5 times, respectively.

In reality, designs in high speed 65-nm processes lose as much as

half their power to leakage. Many in the industry believe that, by the
45-nm node, ICs will lose as much as 60% of their power to leakage.

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 Power issues cont….

As manufactures opt for faster transistors and lower voltage levels

the power leakage increases exponentially.

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 Power reduction techniques
The various age old power reduction techniques are

Multi VT

Clock gating

Pipelining architecture

Multi VDD
Clock gating
Power gating

Using power aware memories

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 EDA’s to the rescue
With the growing demand for handheld and portable devices power
has attained the highest priority for most deigns.
As a result, designing for low power has become a dominant
concern for the electronic design- automation (EDA) industry and its
customers.
Today's EDA methodologies and tools have evolved to handle
dynamic-power issues well. Yet addressing static or leakage-based
power consumption requires new techniques and standards that fall
outside the scope of traditional HDL based flows.
EDA companies and their customers have gone on individual
quests to address this need. This trend has resulted in confusion,
customer frustration, and-ultimately-the demand for a standard that
would work across a broad spectrum of EDA tools and flows.

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 Unified Power Format
This is where UPF comes into picture. The demand for a standard
has led to the creation of the Unified Power Format (UPF), a
standard developed under the auspices of Accellera.
Accellera is an electronics industry organization focused on
electronic-design-automation standards. As standards go, UPF
proved to be a standard that was done the right way. It was
developed in record time with unprecedented collaboration and
cooperation between competing EDA companies and key customers.
 From the outset, the development of the UPF standard has been
open. Any company that wants to participate can join others in
developing the standard. Contribution to the standard doesn't require
membership, legal agreements, licenses, or fees.

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Participating companies and their products

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 UPF
UPF provides the ability for electronic systems to be designed
with power as a key consideration early in the process. It
accomplishes this through the ability to allow the specification of
implementation-relevant power information early in the design
process — RTL (register transfer level) or earlier.

UPF provides a consistent format to specify power-aware design

information that cannot be specified in HDL (hardware description
language) code or when it is undesirable to directly specify within
the HDL logic, as doing so would tie the logic specification directly
to a constrained power implementation.

It captures the low-power design specification from register

transfer level (RTL) to end with consistent language throughout the
design and verification flow. 
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 UPF cont..
As indicated in figure , combined
with the RTL, the UPF files are
used to describe the intent of the
designer.

This collection of source files is

the input to several tools, e.g.,
simulation tools, synthesis tools,
and formal verification tools.

A UPF-aware logical equivalence

checker can read the full design
files and perform checks-including
the results of the UPF commands-
to ensure equivalence. 
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 Power domains
Designing electronics to meet low power design constraints
requires the specification of a power supply network that can
control the distribution of that supply to minimize energy
consumption.

A UPF specification defines how to create a supply network to

supply power to each design element, how the individual supply
nets behave with respect to one another, and how the logic
functionality is extended to support dynamic power switching to
these logic design elements.

To help manage the complexity of the supply network

specification, power domains are defined to group elements from
the logic hierarchy that share common supply needs. By default, all
logic elements in a power domain use the same primary supply.
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Power domains cont..

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 Isolation and Retention
UPF defines extensions of the logic design with power-specific
capabilities and constraints without modifying the original logic
specification.

This provides designers the guarantee they intuitively expect: by

adding a UPF power specification to a logic design or by changing or
replacing an existing UPF specification for a logic design, they do
not need to touch the original logic specification or re-verify the
(non-power aware) logic functionality independent of the power
specification.

Figure illustrates how UPF extends the logic design by adding

power-aware functionality while leaving the original functionality
unmodified using retention and isolation blocks.

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Retention and Isolation cont..
Isolation is required to ensure
undefined outputs from powered-down
design elements do not drain power
from those design elements that are not
powered down.

Retention is the ability to save the

value of a sequential element in a
power domain prior to switching off
the power to that element and then later
restoring its value after power has been
enabled for the element.

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 Commands
1. create_power_domain
Syntax : create_power_domain domain_name
[-elements list]
The create_power_domain command defines a power supply
distribution network, usually for a list of design elements in the
power domain.

2. set_isolation
Syntax: set_isolation isolation_name
-domain domain_name
The set_isolation command specifies the elements in the domain to
isolate using the specified strategy to meet power constraints.

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 Advantages of UPF
The UPF file is the input to several tools (e.g., simulation,
synthesis, formal verification, and place-and-route tools).

Synthesis tools can read the RTL/UPF design input files and
produce a netlist.

The UPF file may be reused without change later in the tool flow.

A UPF specification can be included with the other deliverables

of intellectual-property (IP) blocks and reused along with the other
delivered IP files.

The same standard can be used in a multi-vendor tool flow

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 CONCLUSIONS
With growing need fro handheld and compact consumer
electronic goods it necessary to make them power efficient.

With decreasing channel lengths the amount of leakage power

increases exponentially.

Corrective measures which are different from what is being

used today is required to overcome the leakage power constraint.

Using UPF will help reducing this problem because it designed

with power as it main objective and is very helpful since a single
UPF file can be used for the entire design flow.

Using from the RTL level right up to the manufacturing stage

will definitely make the design power efficient
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 References
[1] Michael Santarini, ”Taking a bite out of power:Techniques for low-power-
ASIC design“ EDN Europe, 01 Jul 2007.

[2] Karen Bartleson, “The Unified Power Format -- A Standard Done the Right
Way”, Chip Design Magazine,  August/ September 2007.

[3] Unified Power Format (UPF) Standard, accellera, Version 1.0 ,February 22,
2007.

[4] Unified Power Format (UPF) Solutions Guide,accellera,version January

2008.

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Thank You

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