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Digital Logic Circuits (Part 2) Digital Logic Circuits (Part 2)

Digital Logic Circuits (Part 2) discusses implementing a demultiplexer using a generic decoder in MultiSIM, timing considerations in digital circuits including propagation delay and critical paths, timing diagrams, edge detection logic, using clocks to synchronize inputs and outputs, latches for data storage including SR and D latches, D flip-flops as edge-triggered latches, sequential logic circuits using memory elements, reading and writing individual bits and words from groups of flip-flops, and an overview of random access memory.

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71 views25 pages

Digital Logic Circuits (Part 2) Digital Logic Circuits (Part 2)

Digital Logic Circuits (Part 2) discusses implementing a demultiplexer using a generic decoder in MultiSIM, timing considerations in digital circuits including propagation delay and critical paths, timing diagrams, edge detection logic, using clocks to synchronize inputs and outputs, latches for data storage including SR and D latches, D flip-flops as edge-triggered latches, sequential logic circuits using memory elements, reading and writing individual bits and words from groups of flip-flops, and an overview of random access memory.

Uploaded by

maddy13rocks
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital

Digital Logic
Logic Circuits
Circuits
(Part
(Part 2)
2)

Computer Architecture
Implementing DeMux in MultiSIM
• MultiSIM does not include a classical DeMux
– It includes a generic decoder (DCD_2TO4, DCD_3TO8, and
DCD_4TO16) that can be adapted to operate as a DEMUX as shown
below:
• Basically need to invert the input and the outputs to/from DCD_2TO4
Timing
• Gates take time to work
– Outputs don’t stabilize for some time
• Stabilization time is usually in nanoseconds
• Gate delays compound in circuits
– Final output is not ready until all gates are stable
• Propagation delay
– Time taken for changes at the input to propagate to output
– Typically, the longest path from input to output
• This is often called the “critical path” in a circuit
Example

A A•B
2ns
B A•B•C•D
2ns
C
2ns
D C•D

Total delay = 4ns


Timing Diagrams
• Illustrate change in inputs & outputs in a
circuit with respect to time
– In the form of a graph
• Time on X-axis
• Selected inputs / outputs on the Y-axis
Timing Diagram Example
A A•B
2ns
B A•B•C
2ns
C

A.B

A.B.C

2ns 4ns 6ns 8ns


Mind Bender
• What is the output from this circuit when
– Input C transitions from 1→0
– Input C transitions from 0→1

C
2ns

1ns

• This is an Edge detection logic circuit


Clocks
• Delays require careful timing
• Otherwise results will be incorrect or garbled
– Particularly when multiple inputs are to be processed
• I/O is synchronized using a Clock
– Clock is a alternating sequence of 1 and 0
• With a given periodicity or frequency
– Frequency = 1/Period
• Frequency is determined by the gate delays and circuit
complexity

0
Clock Example
• Clocked I/O
– Minimum clock period = 4ns
– Maximum Frequency = 1/4ns = 250 MHz

A
2ns A•B•C
Clock 2ns
2ns
B

4 ns
Triggering
• Clocks transitions are used in different ways
– Level triggering
• When clock is in a given state
– Edge triggering
• Raising edge triggered
– When the clock is in transition from 0 → 1
• Falling edge triggered
– When the clock is in transition from 1 → 0

Rising Falling
edge Clock edge
Latches
• Latches maintain state
– Can be set to a specific value
– Output of latches does not change even after
Inputs change to 0!
• Fundamental units for storage
– Building blocks for memory
• Latches always store data when the clock is
at a fixed level
– Hence they are also called as level triggered
device
Set-Reset (SR) Latch
S
Q

Q
R

S R Q
0 0 No change
1 0 1
0 1 0
1 1 Unstable
Clocked S-R Latch
S Q

Clock /
Enable
Q
R

• Latch stores (or changes) value only when clock is


high
– Clock must be at logic level 1 to store data in the latch.
– Data can be read at any time
D-Latch
D Q

Clock /
Enable
Q

• Advantages over S-R Latch


– Single input to store 1 or 0
– Avoid spurious input of S=1 and R=1
D-Flip Flop
• An edge triggered D-Latch is a D-Flip Flop
D Q
Clock

• Stores data only on raising edge


– Changes at input at other times is ignored
• Suitable clock frequency permits data to be stored only
after inputs have settled
• Data can be read at any time!
Abstract Representations
D Q D Q

CK CK

D-Latch D-Flip Flop


(Positive Level Triggered) (Rising Edge Triggered)

D Q D Q

CK CK

D-Latch D-Flip Flop


(Negative Level Triggered) (Falling Edge Triggered)
Representations in MultiSIM

Positive Edge Triggered Positive Edge Triggered


D-Latch. Clock must be D-Flip Flop. Clock input is
tied to EN input. labeled CLK.
Asserted: Terminology
• Flip Flops use positive or negative logic
– Same concept applies to other devices
– In order to ease discussion the term “asserted” is
used
• Positive logic
– A “1” triggers the working of the device
• Negative logic
– A “0” triggers the working of the device
Sequential Logic Circuits
• Involve one or more memory elements
– Output depends on value in memory element
• Typically based on earlier computations or history
– Opposite of combinatory logic circuits
– Also known as Combinatorial logic circuits
– Circuits we have been dealing with so far
• Does not include a memory element
• Outputs depend purely on primary inputs
Typical Sequential Circuits
• Clocks control timings
– Ensure values are not stored when they are
transient
• Have to wait for the signals to stabilize
– State elements store values between
computations

Memory Combinational Memory Combinational


Elements Logic Elements Logic
Circuit to read a Bit
• Given 4 Flip Flops, develop a logic circuit to
select and read a given Flip Flop.

D Q D Q D Q D Q
CK CK CK CK

4 X 1 Multiplexer

Select Lines Output


Circuit to write a Bit
• Given 4 Flip Flops, develop a logic circuit to
select and change data in a given Flip Flop.
Input D Q
1X4 CK

Clock to trigger one of the D Q


De-
D FFs to store the input bit CK
Mux
D Q
CK
D Q
CK

Select Lines
Word
• A fixed number of D-Flip Flops
– Usually powers of 2 (2, 4, 8, 16, 32, 64)
– Operate as a single unit
• Store/Read n-bits at a time
D0 D1 D2 D3

D Q D Q D Q D Q

CK CK CK CK

Q Q1 Q Q3
0 2
Reading & Writing Words
• A fixed number of D-Flip Flops
I1 I2 I3

DeMux DFF DFF DFF DFF DFF DFF

S0

Mux #1 Mux #2 Mux #3

O1 O2 O3
CLK RD
(1=Read, O=Write)
Random Access Memory (RAM)
• RAM is the common form of main memory that is used to
store data and programs in modern computers.
– It is typically designed as a collection of flip flops as shown in
the previous slide
• However fabrication technology is different to reduce cost and
improve transistor densities
– Terminology:
• Lines that carry input or output data are referred to as data lines or
data bus
• The select lines associated with the Mux and DeMux are called the
address bus
– The selection data is called address
– In programming terminology it is called a pointer or a reference.

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