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Clock Gating: K.Harshavardhan 19021D6802 M-Tech (Vlsi & Es)

Clock gating is a technique to reduce clock power by disabling the clock to circuits when they are not in use. It works by ANDing the clock signal with a gating control signal. There are three levels of clock gating based on granularity: module-level gating shuts off entire blocks, register-level gates individual registers or sets of registers, and cell-level gating is done within cells like registers. While clock gating reduces dynamic power, it introduces challenges like increased clock latency and skew. The advantages are lower dynamic power, while disadvantages include added complexity and area from the gating controller.

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1K views14 pages

Clock Gating: K.Harshavardhan 19021D6802 M-Tech (Vlsi & Es)

Clock gating is a technique to reduce clock power by disabling the clock to circuits when they are not in use. It works by ANDing the clock signal with a gating control signal. There are three levels of clock gating based on granularity: module-level gating shuts off entire blocks, register-level gates individual registers or sets of registers, and cell-level gating is done within cells like registers. While clock gating reduces dynamic power, it introduces challenges like increased clock latency and skew. The advantages are lower dynamic power, while disadvantages include added complexity and area from the gating controller.

Uploaded by

Bunny harsha
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CLOCK GATING

K.Harshavardhan
19021D6802
M-tech(vlsi & es)
CONTENTS
Introduction
Principle of clock gating
Levels of clock gating
Challenges in clock gating
Advantages and Disadvantages of clock gating
INTRODUCTION
 Clock-gating is a well-known technique to reduce clock power. Because individual circuit usage varies within
and across applications, not all the circuits are used all the time, giving rise to power reduction opportunity.

 By ANDing the clock with a gate-control signal, clock gating essentially disables the clock to a circuit
whenever the circuit is not used, avoiding power dissipation due to unnecessary charging and discharging of
the unused circuits.

 Specifically, clock-gating targets the clock power consumed in pipeline latches and dynamic CMOS-logic
circuits
PRINCIPAL OF CLOCK GATING
The clock network in a microprocessor feeds clock to sequential elements like
flip-flops and latches, and to dynamic logic gates, which are used in high-
performance execution units and array address decoders.

At a high level, gating the clock to a latch or a logic gate by ANDing the
clock with a control signal prevents the unnecessary charging/discharging of
the capacitances when the circuit is idle, and saves the circuit’s clock power.
• Fig. 2.1 shows the schematic of a latch element. Cg is the latch’s cumulative gate
capacitance connected to the clock. Because the clock switches every cycle, Cg
charges and discharges every cycle and consumes significant amount of power.
Even if the inputs do not change from one clock to the next, the latch still
consumes clock power.
• In Fig. 2.2, the clock is gated by ANDing it with a control signal, which we refer as
Clk-gate signal. When the latch is not required to switch state, Clk-gate signal is
turned off and the clock is not allowed to charge/discharge Cg, saving clock power.
Because the latches of an operand can be driven by an AND gate, the capacitance of
the AND gate itself is much smaller than the sum of multiple Cg of these latches.
Hence, we can get a net power saving.
LEVELS OF CLOCK GATING
• Based on the granularity, the CG can be categorized into the following
three levels:
• Module-level CG
• Register-level CG
• Cell-level CG
Module-Level CG
• This involves shutting off an entire block or module in the design leading
to large power savings. Typical examples are blocks which are explicitly
used for some specific purpose such as transmitter/receiver, ADC, MP3
player, etc.
• For example, the transmitter can be turned off when the receiver is in use
and vice versa. Normally, this is to be identified by the designer and
incorporated in the register transfer language (RTL) code.
Register-Level Gating
• The clock to a single register or a set of registers is gated in register-level CG.

• Figure shows a synchronous load-enabled register bank typically implemented using


clocked D flip-flops and a recirculating multiplexer. Here, the register bank is clocked
in every cycle, irrespective of whether a new value (D_in) is loaded into it or not.
• The clock-gated version of the same register bank is shown in Figure. In this
clock-gated version, the register does not get the clock in the cycles when no new
data is to be loaded. The elimination of the multiplexer circuit (MUX) from the
clock-gated version also saves power
Cell-Level Gating
• Cell designer introduces cell-level CG by incorporating CG circuit as part
of a cell, thereby removing the burden of the circuit designer.
• For example, a register bank can be designed such that it receives clock
only when new data need to be loaded. Similarly, memory banks can be
clocked only during active memory access cycles.
• Although it does not involve any flow issue and design is simple, it may
not be efficient in terms of area and power.
Challenges in clock gating

• Although CG helps to reduce dynamic power dissipation, it introduces several


challenges in the application-specific integrated circuit (ASIC) design flow.
• Some of the important issues are as follows:
• Clock latency
• Effect of clock skew
• Clock tree synthesis
• Physical CG
• Testability concern
Advantages & Disadvantages
• Advantages:
It will decrease the Dynamic Power consumption.
• Disadvantages
Complexity in implementing the gating controller
Additional area brought by the clock gate controller.
THANK YOU

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