Shanghai PD Training - Placement

Jenny Jiemin Sun & Srikanth Yarlagadda

09/14/2009
Agenda
 Introduction
 Overview
 Params & Controls
 Tunables
 Placement & Modes
 QoR – Timing & Congestion
 Strategies to Fix Congestion
 Guidelines & Best Practices
Introduction

 What to expect during placement

 Placement of logic gates and flops in the core area
 Placement based on interconnectivity of cells, modules, macros and IO’s
 Placement based on Timing, Power and Congestion constraints
 Alignment of cells placement to placement grid

 Placement results can give initial picture on

 Utilization
 Timing
 Routing Congestion
 Placement Density

 Critical stage in the PD flow. If it is bad it will affect all other

steps in the PD flow
Placement Overview
Placement Overview – Available Tools

 CHOSEN_PLACER = ? (choices are Fe, Ic or Sp)

 IcPlace
– Default in TB flow and best QoR

– Excellent module placement

 FePlace
– Pure placement with limited capability of optimization

 SpPlace
– New placer and worth trying, correlate better with post-CTS/post-
Route optimization
Placement Overview – Inputs/Outputs
Placement Params & Controls – IcPlace
 Params  grep for “IcPlace” from tile.params
zgrep IcPlace tile.params | grep -v #
IcPlace_OPTIMIZATION_SEQUENCE = AREASENS

IcPlace_USE_GLOBAL_ROUTER =0  Use global router during placement

IcPlace_BUILD_HFN =0  Buffer high fan-out nets

IcPlace_OPTIMIZE_DFT =0  Optimize scan chains during placement

OPTIMIZATION_IcPlace_MMMC_CHECK_LIST = setup setup Turn on single or multiple mode/corner optimization

could potentially have better QoR result. Depending
OPTIMIZATION_IcPlace_MMMC_LIB_LIST = tt0p85v0c tt0p765v0c on your tile area/congestion situation, you can choose
to set single worst corner or add multiple mode/corner
OPTIMIZATION_IcPlace_MMMC_RC_LIST = typrc0c typrc0c to optimization list during IcPlace.

OPTIMIZATION_IcPlace_MMMC_MODE_LIST = FuncTT0p85v FuncTT0p765v

 Controls  grep for “IcPlace” from target.controls

zgrep IcPlace target.controls | grep –v #
TILEBUILDERCHECKLOGS_IcPlace_ALERT_PATTERN += /MWDC-126/

TILEBUILDERCHECKLOGS_IcPlace_IGNORE_PATTERN += /Error: Unable to get layer 0 from CEL/

TILEBUILDERCHECKLOGS_IcPlace_IGNORE_PATTERN += /Error: Floorplan loading track information failed/

TILEBUILDERCHECKLOGS_IcPlace_IGNORE_PATTERN += /Error: Floorplan loading failed/

TILEBUILDERCHECKLOGS_IcPlace_IGNORE_PATTERN += /No such file or directory/

Placement Tunables – IcPlace

tune/IcPlace/IcPlace.extra0.tcl
Set Options

Load Libraries

Load Design &

Constraints

Set Modes & Corners

tune/IcPlace/IcPlace.extra1.tcl
• Add physical constraints here …
Placement &
tune/IcPlace/IcPlace.extra2.tcl
Optimization
tune/IcPlace/IcPlace.extra3.tcl
• Remove placement specific physical
constraints before saving the design Save Design
Placement – IcPlace
 Performs fast placement and multi-pass physical
synthesis to achieve best congestion, timing,
power and area
Set Options
 MMMC placement capability
Load Libraries
 Strategies during placement

Load Design &

Coarse
Constraints Placement

Set Modes & Corners AHFS

place_opt
Placement & Physical
Optimization Optimization
psyn_opt
Placement
Save Design Legalization
Placement – Modes (IcPlace)

 IcPlace_OPTIMIZATION_SEQUENCE
– TIMPLACE: Timing driven placement only
– CONGPLACE: Congestion driven placement
– AREASENS: Good for congestion and area sensitive designs
– CONGSENS: Good for congestion sensitive designs, but
increases runtime and might hurt timing
– TUNE: Source user tunable file (extra2.tcl) and just run user
requests
– HIGHEFFORT: Usually the best qor but expect 3X runtime
QoR – Timing
 Check rpts/IcPlace/qor.rpt.gz for summary of timing and
*max.rpt.gz for detailed reports for each path group
 If timing is bad after placement and post place optimization,
check the design:
– What did the path look like in pretiming?
– Check zero wireload and wireload

– Are budgeted timing constraints reasonable and accurate? Any

multi-cycle path and false path missing?
– Is path well placed?
– Are you seeing lots of buffering in the path?
– If not, what’s pulling it apart?
– Can you fix what’s pulling it apart?
– Will you break something else if you fix this?
– Can the frontend help?
QoR – Congestion & Utilization

 Utilization
– Post placement utilization not too high < 80%
 zgrep "Standard cell utilization“ logs/PixPlace.log.gz
– Utilization increase after placement too much? Like >10%
– Check placement density. Should not be any major hot spots
 rpts/PixPlace/utilization.gif
 Congestion
– Total OverCon < 1.0%
 zgrep “# Total“ logs/PixPlace.log.gz
– Check congestion maps. Should not be any major hot spots
 rpts/PixPlace/horizontal.gif
 rpts/PixPlace/vertical.gif
 QoR – Congestion & Utilization

Horizontal congestion Vertical congestion Placement density

• xv • xv rpts/PixPlace/vertical.gif • xv
rpts/PixPlace/horizontal.gif rpts/PixPlace/utilization.gif
QoR – Module Placement
 Purpose of module
placement review

 Gives an idea of how the

modules are placed

 Are the modules placed as

per the dataflow diagram
from FE

 Are they placed wrt module

interaction
QoR – Causes of Timing/Congestion

 Several potential causes of congestion

 Floorplan issues
– Crowded IO pins
– Macros that need many wires routed over them
 Placement issues
– High local density areas
 Connectivity issues
– Too many wires crossing an area
– Macros placed far apart causing extra wiring
 Logic connections
– Logic wired in a crossbar fashion
Strategies to Fix Congestion

 Add Physical Constraints thru tunables (Examples are

ICC specific commands)
• Adjust cell density in congested areas (Density screens)
• Add/modify Blockages
• Cell Padding
• Create Groups and Regions
 Modify the Floorplan
• Change Macro locations
• Change tile shape/size (Feedback PD Integration team)
• Move pins (Feedback PD Integration team)
Strategies to Fix Congestion – Cell Density

Cell density can be up to

95% by default
• Density level can also be
applied to specific region
Lower cell density in
congested areas using
“coordinate” option

set_congestion_options –max_util 0.4 –coordinate {x1 y1 x2 y2}

Strategies to Fix Congestion – Blockages
 Global Placement Blockages
set physopt_hard_keepout_distance 10
set physopt_soft_keepout_distance 25
(obsolete soon in new version, use below new options instead)

set place_soft_keepout_chennel_width 25

 Macro Blockage Margin

set_keepout_margin -type hard \
-outer {10 0 10 0} RAM5
{left bottom right top}

 Coordinate Based Placement Blockage

create_placement_blockage –name CORNER_1 -type hard –bbox \
{{x1 y1} {x2 y2}}
Strategies to Fix Congestion – Cell Padding

 Use cell padding for cells where Keepout margin

placement density is higher
• Generally AOI & OAI cells will have more pins top
and
may need more routing resource
left right

• Cell padding leaves more space around the cell Cell/Inst

• Cell padding can be used cell/inst specific bottom

• set_keepout_margin -type hard -outer {0.28 0.0 0.28 0.0} \

[get_cells "*" -hier -filter "ref_name =~ *AOI*"]
• set_keepout_margin -type hard -outer {0.28 0.0 0.28 0.0} \
[get_cells "*" -hier -filter "ref_name =~ *OAI*"]
• set_keepout_margin -type hard -outer {0.28 0.0 0.28 0.0} \
[get_cells "*" -hier -filter "ref_name =~ *IOA*"]
Strategies to Fix Congestion – Groups/Regions

 Group and/or region certain modules to place timing

critical logic cells close to each other to help timing
and congestion
 Just create group
create_bounds –name b1 [get_cells cgtt_tile/*]
 Create group and region. They can be soft, hard or exclusive
– Soft regions specify placement goals, with no guarantee that the
cells will be placed inside regions
– Hard regions force placement of the specified cells inside the regions
– Exclusive regions force placement of the specified cells inside the
regions and all other cells must be placed outside the regions
create_bounds –name b2 –coordinate {-40 -40 0 0} \
[–type soft|hard] [-exclusive] [get_cells cgtt_tile/*]
Strategies to Fix Congestion – Modify Floorplan

 Macro placement
– Main way for altering results is macro placement
– Follow and check macro placement guidelines

 Change pin placements

– Must look at overall chip impact
– Will end up changing results in neighboring tiles
– Typically only done for challenging tiles

 Change tile shape

– Usually tile shape will be constrained by fullchip floorplan.
– Typically only done for challenging tiles. Before requesting must try all
the options and run experiments
– Data must be present to show the difference and need high level
approval
Guidelines and Best Practices
 If the IO constraints are not good, can keep low priority on IO path
groups
group_path –name flop_to_io –weight 0.1
group_path –name io_to_flop –weight 0.1
group_path –name io_to_io –weight 0.1
 If some paths need high priority, create path group and assign
high weight
group_path –name group1 –weight 10 –from {A/*} –to {B/*}
 Modify critical range when needed. Critical range specifies a
margin of delay for path groups in optimization . Below is current
default in our template:
set_critical_range 1000 [current_design] (meaning all violating paths)
This may cause a lot of area blowup and congestion degradation in some
tiles. Change it to only on some path group may achieve best QoR.
group_path -name SCLK -critical_range 1.0 –weight 1
 Lab Exercises

2
Tasks (sxs_t tile from Ibiza)
1. Take the previous lab “sxs_t” floorplan database to ICC Placement

2. Go through “IcPlace” target command files, report files and log files
 Command files: cmds/IcPlace.cmd
 Log files: logs/IcPlace.log
 Report files: rpts/IcPlace/*

3. Understand the timing/utilization/congestion reports

 rpts/IcPlace/qor.rpt.gz (Timing)
 rpts/IcPlace/*max.rpt.gz (Timing)
 rpts/PixPlace/*gif (Utilization and Congestion)
 logs/PixPlace.log (Utilization and Congestion)

4. Branch TB from IcPlace and run at least two different flavors of

placement
1. Can be with different physical constraints, different IcPlace params etc
2. Review the differences b/n two runs

5. If the IcPlace QoR is very bad, go back to macro placement and

redo the labs
Questions?

 Answer the following

– Pre-Placement Utilization:
– Post-Placement Utilization:
– Placement Timing:
 SCLK WNS:
 SCLK TNS:
 SCLK Violating Paths:

– Post-Placement Congestion:
 Horizontal Congestion:
 Vertical Congestion:

– “sxs_t” top-level Module names: