EE895KR

Advanced VLSI Design

Kaushik Roy

Purdue University
Dept. of ECE

[email protected]
 Course Overview
• Targeted for graduate students who have
already taken basic VLSI design classes
• Real world challenges and solutions in
designing high-performance and low-power
circuits
• Relations to VLSI Design
– Recent developments in digital IC design
– Project oriented
– Student participation: class presentation

2
 Prerequisite
• MOS VLSI Design or equivalent
– MOS transistor
– Static, dynamic logic
– Adder
• Familiarity with VLSI CAD tools
– Magic or Cadence: LVS, DRC
– HSPICE
• Basic knowledge on solid-state physics

3
 Class Materials
• Lecture notes: primary reference
• K. Roy, S. Prasad, Low Power CMOS VLSI
Circuit Design, John Wiley
• A. Chandrakasan, W. Bowhill, F. Fox, Design of
High-Performance Microprocessor Circuits,
IEEE Press, 2001.
• Y. Taur, T. Ning, Fundamentals of Modern VLSI
Devices, Cambridge University Press, 2002.
• J. Rabaey, A. Chandrakasan, B. Nikolic, Digital
Integrated Circuits: A Design Perspective,
Prentice Hall, 2nd edition, 2003. (prerequisite)

4
 Class Organization
• One exam (40% of overall grade)
• Term-long project (60%)
– Proposal (5%)
– Midterm presentation (15%) – background
material and proposed work
– Final presentation (20%)
– Final report (20%)

5
 CAD Tools
• Cadence
– Schematic editor, layout editor, DRC, LVS
• HSPICE, awaves
• Technology files
– TSMC 0.18μm, BPTM 70nm, …
• Synopsys design compiler, library compiler
• Taurus-device, Taurus-medici

• Everyone should have some experience with

these tools

6
 Term Project
• Single person project
• Proposal (~week 3)
– 2 pages
– Topic, problem statement, research plan, references
• Midterm presentation (~week 7)
– 15 mins
– Literature survey
– Off campus students can give presentations over the
phone
• Final presentation (early December)
– 20 mins
– Background, final results, contributions
• Final report (Dec. 10)
– Publishable quality
7
 Project Topic
• Students pick the research topic they want to work on
• After the literature survey, choose a paper that you
would like to evaluate yourself
• Has to be on digital VLSI circuit DESIGN
– Op-amp design alone is not acceptable
– Op-amp design for digital applications is acceptable
• Show the paper’s claim using your own simulations
• Your contribution must be clearly shown at the end
– Improve previous design
– New circuit, modeling technique
– Show limitation of previous techniques
• Talk to the instructor in case you need help

8
 How to Find a Project Topic?
• Conferences
– International Solid-State Circuits Conference (ISSCC,
top conference!): slides posted on IEEExplore
– Symposium on VLSI Circuits (VLSIC), DAC, ICCAD
– Custom Integrated Circuits Conference (CICC)
• Journal
– IEEE TVLSI, IEEE TCAD, IEEE TED
– IEEE Journal of Solid-State Circuits (JSSC)
– Intel Technology Journal
– IBM Journal on R & D

9
 How to Find a Project Topic?
• Funding agencies
– Research needs document (www.src.org)
• Presentation
– University of Michigan VLSI seminar series
(www.eecs.umich.edu/vlsi_seminar/)
– Design automation conference (www.dac.com)

• Pick a recent issue in VLSI design (< 5 years)

• I suggest you start doing the literature survey
ASAP (deadline coming up in 3 weeks)

10
 Acknowledgements
• Prof. Chris Kim
• Intel circuit research labs (S. Borkar and many
others)
• IBM
• Copy right 2002 J. Rabaey et al.

11
 Academic Misconduct
• Students caught engaging in an academically
dishonest practice will receive a failing grade
for the course.
• University policy on academic dishonesty will
be followed strictly.

12
 Course Topics
• Scaling issues
• High performance design
– High performance logic family, clocking strategies,
interconnects
• Low power design
– Low voltage designs, leakage control techniques,
circuit/device/technology issues, low power SRAM
• Variation tolerant design
– Process compensating techniques
• Power delivery, interconnect, reliability
• Bulk and SOI

13
A physical system as a computing
medium
• We need to create a bit first. Information processing always
requires physical carrier, which are material particles.

• First requirement to physical realization of a bit implies creating

distinguishable states within a system of such material particles.

• The second requirement is conditional change of state.

• The properties of distinguishability and conditional change of

state are two fundamental properties of a material subsystem to
represent information. These properties can be obtained by
creating energy barriers in a material system.

14
Particle Location is an Indicator of State

1 1 0 0 1 0

15
 Barrier engineering in
semiconductors
By doping, it is possible to create a built-in field and energy barriers of
controllable height and length within semiconductor. It allows one to achieve
conditional complex electron transport between different energy states inside
semiconductors that is needed in the physical realization of devices for
information processing.

n n

17
 Kroemer’s Lemma of Proven
Ignorance

• If in discussing a semiconductor problem,

you cannot draw an Energy-Band-
Diagram, this shows that you don’t know
what are you talking about

• If you can draw one, but don’t, then your

audience won’t know what are you talking
about

18
 Moore’s Law

 Intel founder and chairman Gordon Moore predicted in

1965 that the number of transistors on a chip will double
every 18-24 months

19
 Transistor Scaling

 Constant E-field scaling: voltage and dimensions (both

horizontal and vertical) are scaled by the same factor k,
(~1.4), such that the electrical field remains unchanged.

20
 Technology Scaling
Dimensions scale
   , Vt scales
 0.7, Vdd scales  

kW 0.7
I (Vdd  Vt ) scales
   
Tox 0.7

CVdd 0.7  
D 
scales
 0.7 (30% delay reduction)
I 

2
E  CVdd  0.7 
scales 2

21
 IC Frequency & Power Trends

• Clock 1000
1000 1000
Power
R
Pentium II 1000
frequency Processor

Frequency (MHz)
improves 100
100 800
Chip Power (W)
Pentium R 800

Frequency (M Hz)
Chip Power (W)
50% Processor
• Gate delay 10
10 600
600
improves 486DX
~30% 11 CPU 400
386
• Power
0.1
0.1 200
increases Frequency
50%
0.01
• Power = 0.01 1 2 3 4 5 6 7 00
CL V2 f 1.0 0.8 0.6 .35 .25 .18
Technology Generation (m)
 Active switched capacitance “CL” is increasing.

22
 Vdd vs. Vt scaling
• Recently: 5
constant e-field 5 V CC
4
scaling, aka 4

VCC or VT (V)
(V)
voltage scaling 3

T
3 (V C C - V T ) V C C =1.8V

V CC or V
• VCC  1V G ate over drive
22
• VCC & modest VT VT V T =.45V
11
scaling
• Loss in gate 00 0 1 2 3 4 5 6 7

1.4 1.0 0.8 0.6 .35 .25 .18

overdrive (VCC-VT)
Tech nology G eneration (m )
 Voltage scaling is good for controlling IC’s active power,
but it requires aggressive VT scaling for high performance

23
 Delay
CL
d  Long Channel MOSFET
W V
C LV DD ( ) C oxV DD (1  T ) 2
d  2L V DD
ID
CL
d  Short Channel MOSFET
V
WC ox SAT (1  T )
V DD

CL0.5T 0.5 1 2.2

 ox (  ) [1]
0.3 V 13
. W W
T
V (0.9  V ) n p
DD DD

[1] C. Hu, “Low Power Design Methodologies,”

Kluwer Academic Publishers, p. 25.
Performance significantly degrades when VDD approaches 3VT.

24
 VT Scaling: VT and IOFF Trade-off
Performance vs Leakage:
VT  IOFF  ID(SAT) 
ID(SAT)
Low VT

IDS
High VT
Weff
I OFF  I subth  K1e (VGS VT )
Leff
IOFFL VD = VDD
Weff fixed Tox
I D ( SAT )  K 2 (VGS  VT ) 2
Leff IOFFH

VTL VTH
I D ( SAT )  K 3Weff Cox SAT (VGS  VT ) VG
 As VT decreases, sub-threshold leakage increases
 Leakage is a barrier to voltage scaling

25
 Constant Field Scaling
Device and circuit parameters Factor
Scaling Device dimensions (tox, L, W, Xj) 1/k
assumptions Doping concentration (Na, Nd) k
Voltage (V) 1/k
Device Electric field (E) 1
parameters Capacitance (C=εA/t) 1/k
Current (I) 1/k
Channel resistance (Rch) 1
Circuit Delay (CV/I) 1/k
parameters Power (VI) 1/k2
Switching energy (CV2) 1/k3
Circuit density (1/A) k2
Power density (P/A) 1

26
 Scaling in the Vertical Dimension

• Transistor Vt rolls off as the channel length is

reduced
• Shallow junction depth reduces Vt roll-off
• However, sheet resistance increases

27
 Scaling in the Vertical Dimension

• Vertical dimension scales less than horizontal

• Aggravates short channel effect (Vt roll-off)
28
 Constant Voltage Scaling
Device and circuit parameters Factor
Scaling Device dimensions (tox, L, W, Xj) 1/k
assumptions Doping concentration (Na, Nd) k
Voltage (V) 1
Device Electric field (E) k
parameters Capacitance (C=εA/t) 1/k
Current (I) k
Channel resistance (Rch) 1/k
Circuit Delay (CV/I) 1/k2
parameters Power (VI) k
Switching energy (CV2) 1/k
Circuit density (1/A) k2
Power density (P/A) k3

29
 Constant Voltage Scaling
• More aggressive scaling than constant field
• Limitations
– Reliability problems due to high field
– Power density increases too fast

• Both constant field and constant voltage

scaling have been followed in practice
• Field and power density has gone up as a
byproduct of high performance, but till now
designers are able to handle the problems

30
 ITRS Roadmap

• International Technology Roadmap for Semiconductors

2002 projection (http://public.itrs.net/)

31
 Transistor Scaling

 90nm is in production, 65nm in research phase

 New technology generation introduced every 2-3 years

32
 Cost per Transistor

 You can buy 10M transistors for a buck

 They even throw in the interconnect and package for free

33
 Transistors Shipped Per Year

 Today, there are about 100 transistors for every ant

- Gordon Moore, ISSCC ‘04

34
 Transistors per Chip

 1.7B transistors in Montecito (next generation Itanium)

 Most of the devices used for on-die cache memory

35
 Chip Frequency

 30% higher frequency every new generation

37
 Die Size

 ~15% larger die every new generation

 This means more than 2X increase in transistors per chip

38
 Supply Voltage Scaling

 Supply voltage is reduced for active power control

Pactive  C Vdd2 f
39
4 Decades of Transistor Scaling:
Itanium 2 Processor

40
 Power Density
Power density (W/cm2)

Year
 High-end microprocessors: Packaging, cooling
 Mobile/handheld applications: Short battery life

41
 Active and Leakage Power
Power (W)

Year
CL Vt
delay  Ileak  exp( )
V
1 t mkT / q
Vdd
 Transistors are becoming dimmers

42
Leakage Power Crawling Up in Itanium 2

 Transistor leakage is perhaps the biggest problem

43
 Leakage Power versus Temp.
56%

49%
70 70 41%
0.18, 15mm die, 1.4V Leakage 33%

Power (Watts)
Power (Watts)

60 60
Active 26%
50 50 19%
9% 14%
0% 0% 1% 1% 2% 3% 5% 7% 6% 9%
40 40
0.1, 15mm die, 0.7V
30 30
Leakage
20 20 Active
10 10
- -
30
40
50

70
80
90
60

0
0

30
40
50
60
70
80
90

0
0
10
11

10
11
Temp (C) Temp (C)

 Leakage power is problematic in active mode for

high performance microprocessors
44
 Thermal Runaway
Increased
heating

Higher Higher power

leakage dissipation

Increased
static current

 Destructive positive feedback mechanism

 Leakage increases exponentially with temperature
 May destroy the test socket  thermal sensors required

45
 Gate Oxide Thickness

 Electrical tox > Physical tox

 Due to gate depletion and carrier quantization in the
channel

46
 Gate Tunneling Leakage

 MOSFET no longer have infinite input resistance

 Impacts both power and functionality of circuits

47
 Process Variation in Microprocessors

 Fast chips burn too much power

 Slow chips cannot meet the frequency requirement

48
 Process Variation in Transistors
1.4 NMOS
PMOS
Normalized ION

1.2

1.0 2X
0.8

0.6
100X
150nm, 110°C
0.4
0.01 0.1 1 10 100
Normalized IOFF
 More than 2X variation in Ion, 100X variation Ioff
 Within-dies, die-to-die, lot-to-lot

49
 Sources of Process Variation

 Intrinsic parameter variation (static)

- Channel length, random dopant fluctuation
 Environmental variation (dynamic)
- Temperature, supply variations

50
Sub-wavelength Lithography

51
 Line Edge/Width Roughness

• Ioff and Idsat impacted by LER and LWR

52
 Random Dopant Fluctuation

 Vt variation caused by non-uniform channel

dopant distribution
53
 Supply Voltage Integrity

• IR noise due to large current consumption

• Ldi/dt noise due to new power reduction techniques
(clock gating, power gating, body biasing) with
power down mode

54
 Supply Voltage Integrity
• Degrades circuit
performance
• Supply voltage
overshoot causes
reliability issues
• Power wasted by
parasitic resistance
causes self-heating
• Vdd fluctuation should
be less than 10%
Courtesy IBM

55
 Productivity Gap

 Design complexity surpasses manpower

 Effective CAD tools, memory dominated chips

56
 Lithography Tool Cost

 What will end Moore’s law, economics or physics?

57
 Interconnect Scaling
• Global interconnects get longer due to larger
die size
• Wire scaling increases R, L and C

• Example: local vs. global interconnect delay

58
 Interconnect Delay Problem
1997 SIA
technology
roadmap

 Local interconnect has sped up (shorter wires)

 Global interconnect has slowed down (RC doesn’t scale)

59
 Interconnect Metal Layers
M6

M5

M4
M3
M2
M1

 Local wires have high density to accommodate the

increasing number of devices
 Global wires have low RC (tall, wide, thick, scarce wires)

60
Interconnect distribution scaling trends
• RC/m scaling trend is only one side of the story...

Pentium Pro (R)

Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II
(Log Scale)
No of nets

Source: Intel
10 100 1,000 10,000 100,000
Length (u)
 Power Delivery & Distribution Challenges
• High-end microprocessors approaching > 10 GHz
• How to deliver and distribute ~100A at < 1V for < $20!
• On-die power density >>> hot-plate power density
• crossover happened back in 0.6m technology!
• di/dt noise only worsening with scaling: drivers are one of the sources.

1.E+08 Lead Processors 70

1.E+07 First compaction 60

1.E+06 Second compaction
50
1.E+05
di/dt in AU

Watts/cm 2
40
1.E+04 P6 30
1.E+03 P5
20
1.E+02
1.E+01 P4 10
P3
1.E+00 0
1
1.5

0.8
0.6
0.35
0.25

0.13

0.06
0.18

0.09

62
Example multi-layer system
M7 Al
1.00 x 1.80m
2.00m

M6
1.00 x 1.80m
2.00m

M5 0.80 x 1.6m
1.6m

M4 0.80 x 1.6m
1.6m
M3 0.32 x 0.64m
0.64m
M2 0.32 x 0.64m
0.64m
M1 0.25 x 0.48m
0.50m
Poly K. Soumyanath et. al. [2]
Substrate
 Cross Talk Noise

 As wires are brought closer with scaling, capacitive

coupling becomes significant
 Adjacent wires on same layer have stronger coupling

64
 Cross Talk Noise

 Multiple aggressors multiple victims possible

 Cross talk noise can cause logic faults in dynamic circuits

65
 Cross Talk and Delay
 Capacitive cross talk
can affect delay
 If aggressor(s) switch
in opposite direction,
effective coupling
capacitance is doubled
 On the other hand, if
aggressor(s) switch in
the same direction, Cc
is eliminated
 Significant difference in
RC delay depending on
adjacent switching
activity

66
 Soft Error In Storage Nodes
Logic 1 Logic 0

Vinduced

• Soft errors are caused by

– Alpha particles from package materials
– Cosmic rays from outer space

67
 Soft Error In Storage Nodes

• Error correction code

• Shielding
• SOI
• Radiation-hardened
cell

68
 More Roadblocks
 Memory stability
 Long term reliability
 Mixed signal design issues
 Mask cost
 Testing multi-GHz processors
 Skeptics: Do we need a faster computer?
…

 Eventually, it all boils down to economics

69
 Summary
 Digital IC Business is Unique
 Things Get Better Every Few Years
 Companies Have to Stay on Moore’s Law Curve to
Survive
 Benefits of Transistor Scaling
 Higher Frequencies of Operation
 Massive Functional Units, Increasing On-Die Memory
 Cost/MIPS Going Down
 Downside of Transistor Scaling
 Power (Dynamic and Static)
 Process Variation
 Design/Manufacturing Cost
 ….

70