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Unit 3 Programmable Digital Signal Processors

The document discusses the program control unit of a digital signal processor. It contains the program counter, hardware for program counter functions, a hard stack, repeat counters, and status registers. The program counter addresses memory in different ways depending on the instruction, such as branching to an immediate value, calling a subroutine, interrupting to a vector, or returning from a stack.

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38 views29 pages

Unit 3 Programmable Digital Signal Processors

The document discusses the program control unit of a digital signal processor. It contains the program counter, hardware for program counter functions, a hard stack, repeat counters, and status registers. The program counter addresses memory in different ways depending on the instruction, such as branching to an immediate value, calling a subroutine, interrupting to a vector, or returning from a stack.

Uploaded by

akshay
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Unit 3

Programmable Digital Signal Processors


• Commercial digital signal processing
devices

10/8/2015
TMS320C54xx Internal Block Diagram
• Memory Access
– 4 16 bit internal bus pairs
– C,D for data read
– E for data write
– P for program
• Others
– 2 40-bit Accumulator.
– 40-bit Barrel shifter
– 40-bit ALU
– 17bx17b multiplier and 40b dedicated adder perform a non
pipelined single-cycle MAC
– Compare, select and store unit
– Exponent adder
– DAGEN and PAGEN
Status register
Temporary register

Functional diagram of Central processing


unit

12/8/2015
Functional diagram of Barrel shifter
Functional diagram of multiplier/adder unit

14/8/2015
Internal memory mapped (CPU) registers
Peripheral registers
Processor mode status register(PMST)
• Data addressing modes

17/8/2015
Immediate and Accumulator Addressing

• The instruction syntax contains the specific value of the


operand
– LD #80h, A

• Immediate values can be 3,5,8,9, or 16 bits in length

• Accumulator addressingUses the accumulator as an address


– READA Smem

EE201A, Spring 2003, Yung-Szu Tu, Chun-


15
Ching, UCLA - Memory Addressing
Absolute addressing
• Addresses are always 16 bits long, addressing types
depend on instructions
• Data-memory address (dmad) addressing uses a specific
value to specify an address in data space
– MVKD SAMPLE, *AR5

• Program-memory address (pmad) addressing uses a


specific value to specify an address in data space
– MVPD TABLE, *AR7-

• Port address (PA) addressing uses a specific value to


specify an external I/O port address
– PORT FIFO, *AR5

• *(lk) addressing uses a specific value to specify an address


in data space
– Instructions with ingle data-memory operand
EE201A, Spring 2003, Yung-Szu Tu, Chun-
16
– LD *(BUFFER), A Ching, UCLA - Memory Addressing
Direct addressing
• Uses the accumulator
as an address
– READA Smem

• With direct addressing,


Instructions contain the
lower 7 bits of the data-
memory address (dma)
– Combined with a base address, data-
page pointer (DP) or stack pointer (SP)
to form a 16-bit data-memory address
– ADD SAMPLE, B
– DR-referenced
– SP-referenced

EE201A, Spring 2003, Yung-Szu Tu, Chun-


17
Ching, UCLA - Memory Addressing
Memory-mapped register addressing

• Used to modify the memory-mapped registers


without affecting the current data-page
pointer (DP) or stack-pointer (SP)
– Overhead for writing to a register is minimal
– Works for direct and indirect addressing
– SCRATCH-PAD ram LOCATED ON DATA PAGE 0 CAN BE MODIFIED

• STM #x, DIRECT


• STM #tbl, AR1

EE201A, Spring 2003, Yung-Szu Tu, Chun-


18
Ching, UCLA - Memory Addressing
Stack addressing
• Used to automatically store the program
counter during interrupts and subroutines
• Can be used to store additional items of
context or to pass data values
• Uses a 16-bit memory-mapped register, the
stack pointer (SP)
• PSHD X2

EE201A, Spring 2003, Yung-Szu Tu, Chun-


19
Ching, UCLA - Memory Addressing
Indirect addressing
• 8 auxiliary registers (AR), and 2 auxiliary
register arithmetic units (ARAU)

19/8/2015
EE201A, Spring 2003, Yung-Szu Tu, Chun- Example 5.1 20
Ching, UCLA - Memory Addressing
Indirect addressing (cont’d)

EE201A, Spring 2003, Yung-Szu Tu, Chun-


21
Ching, UCLA - Memory Addressing
Indirect addressing (cont’d)
• Circular address modifications (MOD=8,9,10,11 or 14) for
convolution, correlation, FIR filters, etc.
– Circular buffer is a sliding window containing the most recent data

• Circular-buffer size register (BK) specifies the size of the


circular 2buffer
N
> R
– Circular buffer of size R must start on a N-bit boundary, where

– 32-word circular buffer starts at xxxx xxxx xx00 0000


– BK=32
– Index is the N LSBs
of ARx
– Index is incremented
or decremented by
step

EE201A, Spring 2003, Yung-Szu Tu, Chun-


22
Ching, UCLA - Memory Addressing
Indirect addressing (cont’d)

Example 5.2,5.3
EE201A, Spring 2003, Yung-Szu Tu, Chun-
23
Ching, UCLA - Memory Addressing
Indirect addressing (cont’d)
• Bit-Reversed Address Modifications (MOD=4
or 7) N N- 1
2 2
– Enhances execution speed and program memory for FFT algorithms that use a
variety of radixes

• Assume FFT size is , then AR0=


– An ARx points to the physical location of a data value

EE201A, Spring 2003, Yung-Szu Tu, Chun-


24
Ching, UCLA - Memory Addressing
Dual operand addressing
• Memory space

24/8/2015
Example 5.4,5.5
• Program Control
It contains program counter (PC), the program counter related H/W, hard
stack, repeat counters &status registers.
PC addresses memory in several ways namely:
Branch: The PC is loaded with the immediate value following the branch
instruction
Subroutine call: The PC is loaded with the immediate value following the
call instruction
Interrupt: The PC is loaded with the address of the appropriate interrupt
vector.
 Instructions such as BACC, CALA, etc ;The PC is loaded with the
contents of the accumulator low word
End of a block repeat loop: The PC is loaded with the contents of the block
repeat program address start register.
Return: The PC is loaded from the top of the stack.

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