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Verification of Vlsi Circuits Using Systemverilog: Vinay Reddy

This document discusses object oriented programming in SystemVerilog for verifying VLSI circuits. It covers classes, handles, objects, encapsulation, and creating objects using the new constructor. Custom constructors are described as a way to initialize nested class handles. Variable assignment copies the value, while handle assignment results in two handles pointing to the same object. Methods are called using the object handle.

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78 views167 pages

Verification of Vlsi Circuits Using Systemverilog: Vinay Reddy

This document discusses object oriented programming in SystemVerilog for verifying VLSI circuits. It covers classes, handles, objects, encapsulation, and creating objects using the new constructor. Custom constructors are described as a way to initialize nested class handles. Variable assignment copies the value, while handle assignment results in two handles pointing to the same object. Methods are called using the object handle.

Uploaded by

varsha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Verification of VLSI Circuits using

SystemVerilog
Vinay Reddy
Department of Electronics & Communication Engineering

1
VERIFICATION OF VLSI CIRCUITS USING
SYSTEMVERILOG

Classes (OOP - 1)

Vinay Reddy
Department of Electronics and Communication Engineering
2
VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Object Oriented Programming (OOP)

3
VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

4
VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

What is difference between classes & Structures?

Classes are dynamic data type.


Structures are static data type.
Called as members of the class
Structures contain only variables (Properties)
Classes contain both variables & Methods

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

Properties of class named packet

members of class named packet

Methods of class named packet

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

Properties of class named packet

members of class named packet

Methods of class named packet

Grouping all the members


into a class named packet is
called Encapsulation

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

reg a;
a is a variable of the data type reg

pkt is a handle of type packet and packet is a class data type

For class data type we declare handles, rest all available data
types in the language we declare variables.

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

Step 1 : Class definition


Step 2 : Handle Declaration
Step 3 : Constructing the object

How to create object?

Inbuilt in the language


It allocates memory to all the members (Now they are physically present)

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

Step 1 : Class definition


Step 2 : Handle Declaration
Step 3 : Constructing the object

How to create object?

new() constructor Inbuilt in the language


It allocates memory to all the members (Now they are physically present – object is created)

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The two jobs of new()
VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

Here pkt is called handle

Here pkt is called object

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

pkt is pointing to null since the object is not yet created

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

Now you can access the contents of the class


The handle will point to the object

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

Note :

4 + 4 = 8 bytes
4 * 8 = 32 bytes
Total = 40 bytes

Functions and tasks will be


allocated stack when ever
they are called.

Tasks are automatic by


default inside the class.

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

Step 1 : Class definition

Step 2 : Handle declaration


Step 3 : Object Creation

https://www.edaplayground.com/x/3QQs
SV OOP : All Examples - EDA Playground

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

Transaction A1, A2;

A1 = new;

Custom constructor

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

a1 handle belonging to class A inside class B

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

Memory allocation will not happen to the nested handle when we define the
object for the top handle

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

How to allocate memory to a1?

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

Two step process (Maintenance Issue)

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

Custom constructor

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

What is the output of the code snippet ?


reg [3:0] a,b;
initial
begin
a = 10;
b = a;
$display (b);
a = 20;
$display (b);
end

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

reg [3:0] a,b; What is the output of these code snippets ?

initial
begin
a = 10;
b = a; // Variable Assignment
$display (b);
a = 20;
$display (b);
end

always@(a)
b = a; 27
VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

// Handle Assignment

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Classes

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes
One car with two keys.
One object with two handles

What is a2.m ?

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

This is called as garbage in System


Verilog and will be cleaned automatically

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

This is called as garbage in System


Verilog and will be cleaned automatically

Note: In order to have handle assignment – both objects


should be of same class

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

Handle Assignment

Now how do we do Variable assignment ?

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

Two classes a1 and a2

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

An object is created for a2 and the


contents of a1 are copied to a2

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Classes

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Classes

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Classes

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Classes

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Classes

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Classes

Deep Copy

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Classes

Both are related, You cannot call it as a complete Copy

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Classes

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
this

this keyword is used to refer


class properties explicitly.

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
this

this keyword is used to refer


class properties explicitly.

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
this

this keyword is used to refer


class properties explicitly.

Note: This problem exist only when the argument name and the property name are same

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
this

Note: This problem exist only when the argument name and the property name are same

this keyword is used to


refer class properties
explicitly.

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Out – of – block declarations

• Class has properties and Methods

• To make the class look more neat and readable we


can write the methods out of the class block

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Out – of – block declarations

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Out – of – block declarations

Now my class looks more readable and neat

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Passing Objects to Methods

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Passing Objects to Methods

It returns a object

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Passing Objects to Methods

The function is called

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Passing Objects to Methods

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Passing Objects to Methods

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Passing Objects to Methods

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Passing Objects to Methods

p1 handle

Address : 0X4000

a1 handle

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Passing Objects to Methods

p1 handle

h1 handle

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Passing Objects to Methods

h1 will point to p1

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Writing Copy Function

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Writing Copy Function

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Writing Copy Function

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Writing Copy Function

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Writing Copy Function

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Writing Copy Function

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Writing Copy Function

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Writing Copy Function

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Writing Copy Function

a2.addr = a1.addr
a2.data = a1.data

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Writing Copy Function

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Writing Copy Function - Deep Copy

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Static Class Properties

1. Static variable exist in the memory always


2. We can access that variable always (no object is necessary)

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Static Class Properties

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Static Class Properties

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Static Class Properties

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Static Class Properties

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Static Class Properties

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Static Class Properties

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Static Class Properties

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Static Class Properties

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Static Class Properties

Note: Static methods are allowed to


access only static properties else you
will get compile error.

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Static Class Properties

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SYSTEMVERILOG

Classes (OOP - 2)

Vinay Reddy
Department of Electronics and Communication Engineering
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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Inheritance

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Inheritance

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Inheritance

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Inheritance

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Inheritance

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Inheritance

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Inheritance

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Inheritance

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Inheritance

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Super

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Super

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Inheritance

Custom constructor

Object d1

m=?
K=0

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Inheritance

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Inheritance

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Inheritance

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Is SV Single or Multi Inheritance

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Overridden Methods

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Overridden Methods

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Overridden Methods

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Overridden Methods

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Overridden Methods

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Overridden Methods

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Overridden Methods

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Overridden Methods

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Overridden Methods

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Overridden Methods

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Overridden Methods

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Data Hiding

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Data Hiding

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Data Hiding

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Parameterized Classes

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Parameterized Classes

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Polymorphism

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Polymorphism

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Polymorphism

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Polymorphism

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Polymorphism

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Polymorphism

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Polymorphism

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Handle Assignment

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Handle Assignment

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Handle Assignment

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Randomization

Edit code - EDA Playground


Edit code - EDA Playground
Edit code - EDA Playground
Edit code - EDA Playground
Edit code - EDA Playground
SV Topic12 Randomization Simple example - EDA Playground
Edit code - EDA Playground

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Randomization
Case 1 – Pseudo randomization Case 2 – Randomization with seed Case 3 – Randomization with constraints

Edit code - EDA Playground


Edit code - EDA Playground
Edit code - EDA Playground

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Randomization
Case 1 – Pseudo randomization Case 2 – Randomization with seed Case 3 – Randomization with constraints

Lets move all these constraints and


the random variables into a class

Edit code - EDA Playground


Edit code - EDA Playground Edit code - EDA Playground

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Randomization

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Randomization

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Randomization

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Randomization

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Randomization

Edit code - EDA Playground

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Randomization

output

Edit code - EDA Playground 134


VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Randomization

Edit code - EDA Playground 135


VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Randomization

Conflicting Constraints

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Randomization

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Randomization

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Randomization

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Randomization

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Randomization

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Randomization

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Randomization

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Randomization Edit code - EDA Playground

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Randomization

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Randomization

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Randomization

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Randomization

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Randomization SV Topic12 Randomization Simple example - EDA Playground

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Randomization

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Randomization

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Randomization

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Randomization

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Randomization

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Randomization

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Randomization

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Randomization

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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Randomization SV Topic 12 : soft constraints example - EDA Playground

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Randomization
pre_randomize and post_randomize

ou cannot pass arguments to randomize, pre_randomize, post_randomize

SV Topic 12 post_randomize application - EDA Playground


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Randomization

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Randomization

SV Topic12 Randomization Inheritance - EDA Playground


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Randomization
SV Topic12 Randomization Inheritance - EDA Playground

Derived class constraints have overridden the base class constraints


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VERIFICATION OF VLSI CIRCUITS USING SYSTEMVERILOG
Randomization - Polymorphism By default the constraints are virtual

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Randomization

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Randomization

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THANK YOU

Vinay Reddy
Department of Electronics & Communication Engineering
[email protected]
+91 9945730244

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