VERILOG

Prepared and Presented

by:
ISHAN LUTHRA
(Lect., ECE/LSE/LPU)
 VERILOG AS HDL

In the semiconductor and electronic design industry, Verilog is a hardware

description language (HDL) used to model electronic systems. Verilog
HDL, not to be confused with VHDL, is most commonly used in the design,
verification, and implementation of digital logic chips at the register
transfer level (RTL) of abstraction.

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Hardware description languages such as Verilog, differ
from software programming languages because they
include ways of describing the propagation of time and
signal dependencies (sensitivity). There are two
assignment operators, a blocking assignment (=), and a
non-blocking (<=) assignment. The non-blocking
assignment allows designers to describe a state-
machine update without needing to declare and use
temporary storage variables unlike any general
programming language in which we need to define
some temporary storage spaces for the operands to be
operated on subsequently; those are temporary storage
variables.

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A Verilog design consists of a hierarchy of modules.
Modules encapsulate design hierarchy, and
communicate with other modules through a set of
declared input, output, and bidirectional ports.
Internally, a module can contain any combination
of the following: net/variable declarations (wire,
reg, integer, etc.), concurrent and sequential
statement blocks, and instances of other modules
(sub-hierarchies). Sequential statements are
placed inside a begin/end block and executed in
sequential order within the block

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A subset of statements in the Verilog language are
synthesizable. Verilog modules that conform to a
synthesizable coding-style, known as RTL (register
transfer level), can be physically realized by
synthesis software. Synthesis-software
algorithmically transforms the (abstract) Verilog
source into a netlist, a logically-equivalent
description consisting only of elementary logic
primitives (AND, OR, NOT, flipflops, etc.) that are
available in a specific FPGA or VLSI technology.
Further manipulations to the netlist ultimately lead to
a circuit fabrication blueprint

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Examples:

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A simple example of two flip-flops

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 The "<=" operator in verilog is another aspect of its being a
hardware description language as opposed to a normal
procedural language. This is known as a "non-blocking"
assignment. Its action doesn't register until the next clock
cycle. This means that the order of the assignments are
irrelevant and will produce the same result: flop1 and flop2
will swap values every clock.
 The other assignment operator, "=", is referred to as a blocking
assignment. When "=" assignment is used, for the purposes of
logic, the target variable is updated immediately. In the above
example, had the statements used the "=" blocking operator
instead of "<=", flop1 and flop2 would not have been
swapped. Instead, as in traditional programming, the compiler
would understand to simply set flop1 equal to flop2.

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Initial and Always
There are two separate ways of declaring a verilog process.
These are the always and the initial keywords. The
always keyword indicates a free-running process. The
initial keyword indicates a process executes exactly
once. Both constructs begin execution at simulator time
0, and both execute until the end of the block. Once an
always block has reached its end, it is rescheduled
(again). It is a common misconception to believe that an
initial block will execute before an always block. In fact,
it is better to think of the initial-block as a special-case
of the always-block, one which terminates after it
completes for the first time.

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 These are the classic uses for these two keywords, but there are two significant additional uses

These are the classic uses for these two keywords, but there are two significant
additional uses as follows:

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An always keyword without the @(...)
sensitivity list

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Use of the initial keyword with the addition of the forever
keyword.

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 Fork/Join

 The fork/join pair are used by Verilog to

create parallel processes. All statements (or
blocks) between a fork/join pair begin
execution simultaneously upon execution
flow hitting the fork. Execution continues
after the join upon completion of the longest
running statement or block between the fork
and join.

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The way the above is written, it is possible to have either the sequences "ABC" or
"BAC" print out

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Race Conditions

What will be printed out for the values of a and b? Depending on the order of
execution of the initial blocks, it could be zero and zero, or alternately zero and some
other arbitrary uninitialized value. The $display statement will always execute after
both assignment blocks have completed, due to the #1 delay

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System tasks
 $display - Print to screen a line followed by an automatic newline.
 $write - Write to screen a line without the newline.
 $swrite - Print to variable a line without the newline.
 $sscanf - Read from variable a format-specified string.
 $fopen - Open a handle to a file (read or write)
 $fdisplay - Write to file a line followed by an automatic newline.
 $fwrite - Write to file a line without the newline.
 $fscanf - Read from file a format-specified string.
 $fclose - Close and release an open file-handle.

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 $readmemh - Read hex file content into a memory array.
 $readmemb - Read binary file content into a memory
array.
 $monitor - Print out all the listed variables when any
change value.
 $time - Value of current simulation time.
 $dumpfile - Declare the VCD (Value Change Dump)
format output file name.
 $dumpvars - Turn on and dump the variables.
 $dumpports - Turn on and dump the variables in
Extended-VCD format.
 $random - Return a random value.

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HDL Model Abstraction
Here un shaded
blocks show the
design representation
and description level.
Shaded blocks show
the process in the
design flow.

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Design Methodologies

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Top-Down Design Methodology

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Bottom-Up Design Methodology

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4 Bit Ripple Carry Counter

The ripple carry counter shown in the figure is made up of negative edge
triggered T flip flops and each T flip flop is made up of negative edge triggered
D flip flop and inverter.

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Thus the ripple carry counter is built in a hierarchical fashion by using building
blocks.

Diagram for the Design Hierarchy

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Modules

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With respect to the previous example, ripple
carry counter, T flip flop, D flip flop and
inverter are the examples of modules.
In Verilog a module is declared by the keyword
module and a corresponding keyword
endmodule must appear at the end of the
module definition.
Each module must have a module_name,
which is the identifier for the module and a
module_terminal_list which describes the
input and output terminals of the module

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Syntax for defining a Module
Module <module_name> (<module_terminal_list>);
………….
………….
<module_internals>
………….
endmodule

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Module Instances
A module provides a template from which you can
create actual objects. When a module is invoked,
verilog creates a unique object from the
template. Each object has its own name,
variables, parameters and I/O interfaces. The
process of creating objects from module
templates is called instantiation and the objects
are called instances.

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GATE LEVEL MODELING
Gate level modeling technique is very
commonly used in designing digital circuits
because it is vey easy to understand the
working of logic gates for the designer as
well as the user.

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TYPES OF GATES USED IN
DESIGNING
 AND GATE
 NAND GATE
 OR GATE
 NOR GATE
 XOR GATE
 XNOR GATE
 NOT GATE
 BUF GATE

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DESIGNING AND TESTING OF 4 TO 1
MUX

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VERILOG DESCRIPTION OF
MULTIPLEXER

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TESTING OF MODULE WITH
STIMULUS

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OUTPUT OF THE
STIMULUS

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DATA FLOW MODELING
Data flow modeling technique has been adopted
by the designers to overcome the disadvantage
of gate level modeling of instantiating every
individual gate, because it becomes quite
cumbersome in the case of large circuits. In
data flow modeling the designers concentrate
on implementing the function at a level of
abstraction. In this case the circuit is designed
in terms of data flow between registers.

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CONTINUOUS ASSIGNMENTS
A continuous assignment is the most basic
statement in data flow modeling. A
continuous assignment replaces gates in the
description of a circuit and describes the
circuit at a higher level of abstraction.

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SYNTAX
<continuous_assign> ::= assign
<drive_strength>?<delay>?<list of
assignments>;
The drive strength is optional and its default
value is strong0 or strong1.
Delay is also optional and can be used to
specify delay on assign, just as in the case of
gates.

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SOME USEFUL TERMS
Drive Strength: Verilog supports 4 value
levels and their 8 strength levels which are
used to resolve conflicts between drivers of
different strengths in digital circuits.
Nets: Nets represent connections between
hardware elements. Just as in real circuits,
nets have values continuously driven on
them by the outputs of the devices that they
are connected to.

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Registers: Registers represent data storage
elements. Registers retain a value until
another value is placed onto them. However
these are not the hardware registers. In
Veilog register is just a variable that can
hold a value.
Vectors: Nets or Registers can be declared as
vectors, i.e. multiple bit widths. If bit width
is not specified the default is scalar, i.e. 1-
bit.

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EXAMPLE OF CONTINUOUS
ASSIGNMENT
1. assign addr[15:0]= addr1[15:0]^addr2[15:0]
Here,
addr[15:0] is a 16-bit vector net and
addr1[15:0], addr2[15:0] are 16-bit vector registers.
2. wire out;
assign out= i1 & i2;

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IMPLICIT CONTINUOUS
ASSIGNMENT
Example:
wire out=i1 & i2;

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DELAY
Delay values control the time between the
change in a right hand side operand and
when the new value is assigned to the left
hand side.
Three ways of specifying delays are:
 Regular assignment delay
 Implicit continuous assignment delay
 Net declaration delay

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SYNTAX
 Regular assignment delay:
assign #10 out=i1 & i2;
 Implicit continuous assignment delay:

wire #10 out=i1 & i2;

 Net declaration delay:

wire #10 out;

assign out=i1 & i2;

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OPERATOR TYPES
Verilog provides many different operator types.
Operators can be
arithmetic,logical,relational,equality,
bitwise, reduction, shift, concatenation or
conditional.

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EXAMPLE OF 4 TO 1 MUX

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BEHAVIORAL/ ALGORITHMIC
MODELING
Structured Procedures

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Initial statement

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Always statement

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Case statement

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4 to 1 MUX

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SWITCH LEVEL
MODELING

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SYNTAX

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CMOS SWITCHES

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SYNTAX FOR CMOS

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LOGIC TABLES

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BIDIRECTIONAL
SWITCHES

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POWER AND GROUND

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RESISITIVE SWITCHES

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2 TO 1 MUX

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TASKS AND FUNCTIONS

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TASKS

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TASK DECLARATION AND INVOCATION

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EXAMPLE OF TASK
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FUNCTIONS

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FUNCTION DECLARATION AND INVOCATION

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EXAMPLE OF PARITY CALCULATOR

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ADVANCED MODELING TECHNIQUES

PROCEDURAL CONTINUOUS ASSIGNMENTS

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assign and deassign

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Example of negative edge triggered
D Flip-Flop

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force and release

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OVER RIDING PARAMETERS
Overriding parameters can be used to pass a
distinct set of parameter values to each
module during compilation regardless of
predefined parameter values.

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defparam statement

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MODULE INSTANCE
PARAMETER VALUES

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CONDITIONAL COMPILATION AND
EXECUTION

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TIME SCALES

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