MICROPROCESSORS AND

MICROCONTROLLERS
Leka K
Assistant Professor
Biomedical Engineering
Erode Sengunthar Engineering College
THE 8085 ADDRESSING MODES
 The instructions MOV B, A or MVI A, 82H are to copy
data from a source into a destination.
 In these instructions the source can be a register, an

input port, or an 8-bit number (00H to FFH).

 Similarly, a destination can be a register or an output

port.
 The sources and destination are operands.
 The various formats for specifying operands are called

the ADDRESSING MODES.

Types Of Addressing Modes:

 Immediate addressing mode.

 Register addressing mode.
 Direct addressing mode.
 Indirect addressing mode.
IMMEDIATE ADDRESSING MODE

 Data is present in the instruction.

 Load the immediate data to the destination provided.

 Example: MVI R, data.

REGISTER ADDRESSING MODE

 Data is provided through the registers.

 Example: MOV Rd, Rs

 DIRECT ADDRESSING MODE
 Used to accept data from outside devices to store in the
accumulator or send the data stored in the accumulator
to the outside device.
 Accept the data from the port 00H and store them into

the accumulator or Send the data from the accumulator

to the port 01H.

 Example: IN 00H or OUT 01H

INDIRECT ADDRESSING MODE

 This means that the Effective Address is calculated by

the processor.
 And the contents of the address (and the one following)

is used to form a second address.

 The second address is where the data is stored.
 Note that this requires several memory accesses; two

accesses to retrieve the 16-bit address and a further

access (or accesses) to retrieve the data which is to be
loaded into the register.
 INSTRUCTION SET CLASSIFICATION
 An instruction is a binary pattern designed inside a
microprocessor to perform a specific function.
 The entire group of instructions, called the instruction set,

determines what functions the microprocessor can perform.

 These instructions can be classified into the following five

functional categories:
 Data transfer (copy) instructions,
 Arithmetic instructions,
 Logical instructions,
 Branching instructions, and
 Machine-control instructions.
DATA TRANSFER INSTRUCTIONS
 The data transfer instructions move data between registers or
between memory and registers.

MOV Move
MVI Move Immediate
LDA Load Accumulator Directly from Memory
STA Store Accumulator Directly in Memory
LHLD Load H & L Registers Directly from Memory
SHLD Store H & L Registers Directly in Memory
 An 'X' in the name of a data transfer instruction implies that it
deals with a register pair (16-bits);

LXI Load Register Pair with Immediate data

LDAX Load Accumulator from Address in Register Pair
XCHG Exchange H & L with D & E
XTHL Exchange Top of Stack with H & L
STAX Store Accumulator in Address in Register Pair
ARITHMETIC INSTRUCTIONS
 The arithmetic instructions add, subtract, increment, or
decrement data in registers or memory.

 ADD Add to Accumulator

 ADI Add Immediate Data to Accumulator
 ADC Add to Accumulator Using Carry Flag
 ACI Add Immediate data to Accumulator Using Carry
 SUB Subtract from Accumulator
 SUI Subtract Immediate Data from Accumulator
 SBB Subtract from Accumulator Using Borrow (Carry)

Flag
 SBI Subtract Immediate from Accumulator Using

Borrow (Carry) Flag

 INR Increment Specified Byte by One
 DCR Decrement Specified Byte by One
 INX Increment Register Pair by One
 DCX Decrement Register Pair by One
 DAD Double Register Add; Add Content of Register

Pair to H & L Register Pair

 LOGICAL INSTRUCTIONS
 This group performs logical (Boolean) operations on data in
registers and memory and on condition flags.
 The logical AND, OR, and Exclusive OR instructions enable you to
set specific bits in the accumulator ON or OFF.
 ANA Logical AND with Accumulator
 ANI Logical AND with Accumulator Using Immediate Data
 ORA Logical OR with Accumulator
 OR Logical OR with Accumulator Using Immediate Data
 XRA Exclusive Logical OR with Accumulator
 XRI Exclusive OR Using Immediate Data
 The Compare instructions compare the content of an 8-bit value
with the contents of the accumulator;
 CMP Compare
 CPI Compare Using Immediate Data
 The rotate instructions shift the contents of the accumulator one
bit position to the left or right:
 RLC Rotate Accumulator Left
 RRC Rotate Accumulator Right
 RAL Rotate Left Through Carry
 RAR Rotate Right Through Carry
 Complement and carry flag instructions:
 CMA Complement Accumulator
 CMC Complement Carry Flag
 STC Set Carry Flag
 BRANCH INSTRUCTIONS
 The branching instructions alter normal sequential
program flow, either unconditionally or conditionally.
 The unconditional branching instructions are as

follows:
 JMP Jump
 CALL Call
 RET Return
 Conditional branching instructions examine the status

of one of four condition flags to determine whether the

specified branch is to be executed.
 The conditions that may be specified are as follows:

 NZ Not Zero (Z = 0)
 Z Zero (Z = 1)
 NC No Carry (C = 0)
 C Carry (C = 1)
 PO Parity Odd (P = 0)
 PE Parity Even (P = 1)
 P Plus (S = 0)
 M Minus (S = 1)
 Thus, the conditional branching instructions are
specified as follows:
 Jumps Calls Returns
 C CC RC (Carry)
 INC CNC RNC (No Carry)
 JZ CZ RZ (Zero)
 JNZ CNZ RNZ (Not Zero)
 JP CP RP (Plus)
 JM CM RM (Minus)
 JPE CPE RPE (Parity Even)
 JP0 CPO RPO (Parity Odd)
 Two other instructions can affect a branch by replacing
the contents or the program counter:

 PCHL Move H & L to Program Counter

 RST Special Restart Instruction Used with Interrupts
 POP Pop Two Bytes of Data off the Stack
 XTHL Exchange Top of Stack with H & L
 SPHL Move content of H & L to Stack Pointer
 I/0 INSTRUCTIONS
 IN Initiate Input Operation
 OUT Initiate Output Operation

 MACHINE CONTROL INSTRUCTIONS

 EI Enable Interrupt System

 DI Disable Interrupt System
 HLT Halt
 NOP No Operation
 SAMPLE PROGRAM
 Write an assembly program to add two numbers
Program

 MVI D, 8BH
 MVI C, 6FH
 MOV A, C
 ADD D
 OUT PORT1
 HLT
 TIMING DIAGRAM OF 8085
 Timing Diagram is a graphical representation.
 It represents the execution time taken by each

instruction in a graphical format.

 The execution time is represented in T-states.
 Instruction Cycle:

The time required to execute an instruction .

 Machine Cycle:

The time required to access the memory or

input/output devices .
 T-State:
 The machine cycle and instruction cycle takes multiple

clock periods.
 A portion of an operation carried out in one system

clock period is called as T-state.

 TIMING DIAGRAMS
 The 8085 microprocessor has 7 basic machine cycle.
They are,
1. Op-code Fetch cycle(4T or 6T).
2. Memory read cycle (3T)
3. Memory write cycle(3T)
4. I/O read cycle(3T)
5. I/O write cycle(3T)
6. Interrupt Acknowledge cycle(6T or 12T)
7. Bus idle cycle
1.OPCODE FETCH CYCLE(4T OR 6T)
 OPCODE FETCH
 The Opcode fetch cycle, fetches the instructions from
memory and delivers it to the instruction register of the
microprocessor.
 Opcode fetch machine cycle consists of 4 T-states.
 T1 State:
 During the T1 state, the contents of the program

counter are placed on the 16 bit address bus.

 The higher order 8 bits are transferred to address bus

(A8-A15) and lower order 8 bits are transferred to

multiplexed A/D (AD0-AD7) bus.
 ALE (address latch enable) signal goes high. As soon
as ALE goes high, the memory latches the AD0-AD7
bus.
 At the middle of the T state the ALE goes low.

 T2 State:
 During the beginning of this state, the RD’ signal goes

low to enable memory. It is during this state, the

selected memory location is placed on D0-D7 of the
Address/Data multiplexed bus.
 T3 State:
 In the previous state the Opcode is placed in D0-D7 of

the A/D bus.

 In this state of the cycle, the Opcode of the A/D bus is

transferred to the instruction register of the

microprocessor.
 Now the RD’ goes high after this action and thus

disables the memory from A/D bus.

 T4 State:
 In this state the Opcode which was fetched from the

memory is decoded.
2. MEMORY READ CYCLE (3T)
 These machine cycles have 3 T-states.

 T1 state:
 • The higher order address bus (A8-A15) and lower

order address and data multiplexed (AD0-AD7) bus.

 ALE goes high so that the memory latches the (AD0-

AD7) so that complete 16-bit address are available.

 The mp identifies the memory read machine cycle from

the status signals IO/M’=0, S1=1, S0=0. This

condition indicates the memory read cycle.
 T2 state:
 Selected memory location is placed on the (D0-D7) of

the A/D multiplexed bus. RD’ goes LOW

 T3 State:
 The data which was loaded on the previous state is

transferred to the microprocessor.

 In the middle of the T3 state RD’ goes high and

disables the memory read operation.

 The data which was obtained from the memory is then

decoded.
3. MEMORY WRITE CYCLE (3T)
 These machine cycles have 3 T-states.

 T1 state:
 The higher order address bus (A8-A15) and lower

order address and data multiplexed (AD0-AD7) bus.

ALE goes high so that the memory latches the (AD0-
AD7) so that complete 16-bit address are available.

 The mp identifies the memory read machine cycle from

the status signals IO/M’=0, S1=0, S0=1. This
condition indicates the memory read cycle.
 T2 state:
 Selected memory location is placed on the (D0-D7) of

the A/D multiplexed bus. WR’ goes LOW

 T3 State:
 In the middle of the T3 state WR’ goes high and

disables the memory write operation.

 The data which was obtained from the memory is then

decoded.
4.I/O READ CYCLE(3T)
5.I/O WRITE CYCLE(3T)
 It require 4 m/c cycles 13 T states

 1.opcode fetch(4T)
 2.memory read(3T)
 3.memory read(3T)
 4.Memory write(3T)