Dynamic Random Access Memories (DRAMs)

Design & Test Considerations

• DRAMs are in many ways similar to SRAMs

• DRAMs memories use charge storage on a

capacitor to represent binary data values.

• Complex operating mode, the advantages of cost

per bit and high density have made DRAMs the
most widely used semiconductor memories in
commercial applications
 DRAM Technology Development

• In 1970s- the DRAM cell designs of 6-T to a 1-T configuration were

proposed.

• In 1973, 1-T cell became standard for 4K DRAMs

• First commercial DRAM, a I kb chip using three transistor cells in p-

channel silicon gate technology by Intel in 1970.

• 4 kb DRAMs in a single-polysilicon, single-aluminum metallization in

typically 10 um feature size.

• DRAMs density increases exponentially with rapid improvement in the

cell design, its supporting circuit tech, photolithographic techniques
L. Boonstra et al., "A 4096-b one-transistor per bit random-access memory with internal
timing and low dissipation," IEEE J. Solid-State Circuits, vol. SC-8, p. 305, Oct. 1973.
• Key circuit technologies –
– vertical cell structures with trench and stacked
capacitors,
– improvements in differential sensing
– Folded data-line arrangement for noise reduction
– Use of dynamic amplifiers and drivers
– CMOS circuits etc..

• capacitance is larger than that of an SRAM cell

making DRAMs less sensitive to soft errors.
• A significant improvement in the DRAM
evolution was the switch from three-transistor
designs to one-transistor (1-T) cell design

• This cell has been used to fabricate dynamic

memories to 1 Mb densities
H. Yoon, et al., “A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM,”
IEEE Journal of Solid-State Circuits, Vol. 34, No. 11,11/1999, pp. 1589-99.

shrinking geometries
allow greater memory to
be placed on each chip

More challenge, new

fault models, greater
redundancy to optimal
implementaion

Embedded DRAM size trend per chip for mass production

 DRAM TRENDS

International Technology Roadmap for Semiconductors, 2001 Edition,

http://public.itrs.net/Files/2001ITRS/Home.htm.

This value approximates

minimum feature size. These
reduction challenge the
advanced processing
techniques

DRAM Half Pitch trend

• Densities have generally DRAMs (4:1), mainly
because of the greater number of transistors in a
static RAM cell

• DRAM cells must be read and refreshed at periodic

intervals-complex operating mode – adv. Cost/bit
and high density

• Importance of reducing cost/bit of memory led to

simpler, small-area memory cells that could be
more densely packed on a chip
 THE DRAM CELL

 DRAM cell has one transistor and one capacitor

B. Keeth, R.J. Baker, DRAM Circuit Design: A

Tutorial, IEEE Solid-State Circuit Society,
2001.

1T DRAM cell
 Charge Stored on
C1 represents stored binary data

SRAM cell with pull-ups removed Separate R/W wordline because charge
Stored on C1 would be lost if M4 is turned on
during reading
When the wordline is raised, the two access transistors turn on. Charge sharing occurs
between b and q to keep node q high.

While discharges through M4 and M2 . Since this cell relies on charge storage to
maintain the value of a node, it is a dynamic cell

Contrary to SRAM, this cell design doesn’t require internal device ratios for proper operation
• The first half of each read or write cycle is devoted
to a precharge phase during which the columns Din
and Dout are charged to a valid high logic level.

• A "1" is assumed to represent a high level stored on

C1, and is written by turning on M4 after Din is high.

• The Din line is highly capacitive since it is connected

to many cells.
• A "0" is written by turning on M4 after the
precharge phase is over, then simultaneously
discharging Din and C1 via a grounded-source
pull-down device (not shown) in the read-write
circuit.

• The read operation is performed by turning on

M3 after the precharge is over.

• If a "1" is stored, Dout will be discharged through

M1 and M3
• If a “0" is stored, there will be no conducting path
through M1, so Dout will not change significantly

• 1T –DRAM Cell
– Most modern DRAMs have capacities of Mega and
Giga bits or more
– Use of 1T- cell with a storage capacitor
Selection for reading or writing is accomplished by turning on M1 with single row line

Data are stored as a high or low level on C1.

Write operation into the cells is performed by forcing
High or low level on the selected column

There are many variations in the detailed realization of this cell,

Depending on number of polysi layers, methods of capacitor
Formation, conductors used for row and columns etc.
• When reading the cell, charge stored on C1 is
shared with C2 which is 10times larger

• If the bitline capacitance is too large, results of

charge sharing will not be significant enough
to detect stored value of the cell

• Large value of C1 would solve this problem –

Requirement of large C1 is in conflict with cell
size requirements for high density - two
approaches to address this issue
• DRAM trench and stack capacitor 1T DRAM cell

Trench capacitor cross section where vertical cut

Is made in the substrate and filled with an insulator –poly
Sandwich forming the capacitor
Stacked capacitor where two additional
Poly layers are deposited above the
tr. with a dielectric material sandwiched
• Both yields capacitance values between 20-30 fF ,
bitline capacitance in the range of 200-300fF for
proper read operation

• During read, the internal value of the cell is

disturbed. The read process is destructive read
since the value of the cell is modified due to
charge sharing.
– As a result stored data must be regenerated every time
they are read, in addition to refresh
– Read amplifier design is difficult aspect of 1T-DRAM
Since the detection of a small voltage change in single-ended configuration is difficult,
Bitlines are split and equal capacitances are connected to each side

Simplified schematic for a read-refresh circuit . Open-bit architecture

SA detects small data signal and restores the high or low signal level.

The amount of voltage change can be computed using charge sharing mechanism
 DRAM Cell Layout
DRAM layout is highly optimized to reduce the amount of space it requires.

Word lines run vertically, as opposed to the convention in SRAMs where they run
Horizontally and the bit lines run vertically
• This cell is referred to as 8F2 cell.
– The pitch in the bit dimension includes an F for the
width of the bit line and another F for the spacing
bit lines, resulting in 2F
• Number of ways to reduce DRAM cell area to
6F2 and 4F2 which largely depends on overall
DRAM architecture
 DRAM Operation
• The read operation of a DRAM involves
transferring charge from the storage capacitor
of the cell onto a bit line.
• Once specified address has been determined,
appropriate WL becomes active.

• SA is activated after access turns on raising or lowering

BL potential as charge from the cell is transferred

• Only one BL shifts in potential. The other BL remains

at its pre-charge value, since it accessed no cell, is
used as reference.
– When a different word line is activated this BL will be one
which shifts in potential and the other bit line will be the
reference
 Typical DRAM Sense Amplifier
BL potentials are applied to the inputs of NFET and PFET of the sense amplifier latch
• Once the sense amplifier is set, the data is re-
written to the cell. For every read there must
be a write-back operation.

• The bit-line arrangement is critical to the

overall area of the DRAM and to the amount
of noise that can be tolerated
• A folded BL topology is shown in fig. where
the BL pair accesses an adjacent pair of DRAM
rows. Two BL are adjacent to each other.
– Less noise sensitive
An open bit-line configuration allows the line to contact every cell that it passes over.

Any noise is now differential, which is often not tolerable.

Other methods for keeping area of the DRAM down include rotating the array, including the
a vertical transistor, and tilting the active area
• DRAMs are dense circuits
• DRAMs require proper fault modeling and test
development
• Since analog effects are more severe in
DRAMs, more test patterns and special voltage
potentials need to be applied to test

• All cells naturally bleed charge from the DRAM

capacitor, certainly data retention must be
well tested
 Memory bit (Mbit) cell

In memory block construction DRAM elements understanding is essential. Successful

cost-effective DRAM designs require huge process technology
This Mbit is also referred BOC 1T1C DRAM cell

Fig. Layout of a modern buried capacitor

DRAM mbit pair DRAM Mbits are constructed in pairs

Mbit is capable of holding binary

Buried means Capacitor is below the
information in the form of stored charge
digitline, sharing a contact significantly
on the capacitor
reduces overall cell size

Digitline contacts can be shared For most processes, the wordline poly is silicided
to reduce the sheet resistance
• Main adv. Of DRAM over other types of memory
tech is low cost

– 1T1C memory cell

– mbit is capable of holding binary information in the
form of stored charge in a capacitor
– mbit transistor operates as a switch interposed
between mbit capacitor and digitline
– Charge stored in a capacitor is Q = CV

DRAM mbit is simple, actual design and implementation is complex

Cost-effective DRAM designs require a tremendous amount of process technology

• Mbit comprise an
– active area rectangle (n+ active area),
– a pair of polysi wordlines,
– a single digitline contact,
– a metal or polysi digitline
– a pair of cell capacitors formed with an oxide-nitride-
oxide dielectric between two layers of polysi
 Fig. Layout to show array pitch
Mbit features are

Digitline pitch (width plus space) – active area pitch and capacitor pitch

Process engineers adjust active area width and fox width to maximize transistor drive and
Minimize transistor – to – transistor leakage.
• Wordline piitch tells space available for the
digitline contact, transistor length, active area,
field poly width, and capacitor length
– Optimization of these features by process engineers is
necessary to maximize capacitance, minimize leakage,
maximize yield

• Contact technology, subthreshold transistor

behavior, photolithography, etch and film tech
dictates overall design
F – minimum realizable process
Dimension

Folded array arch always produces 8F2 Mbit.

• Feature size is the minimum realizable process
dimension - how it relates to cell size
– In x-axis contains
• one-half digitline contact feature
• One wordline feature
• One capacitor feature
• One field poly feature
• One-half poly space feature - in total 4F

In y-axis contains
• Two one-half field oxide features
• One active area feature - in total 2F

• Area of mbit is therefore

– 4F . 2F = 8F2
 Folded digitline array schematic

• Optional digitline pair

twisting in one or more
positions reduces and
balances coupling to
adjacent digitline pairs
and improves overall
Signal to noise
characteristics.

Sense amplifier circuits placed at edge

of each array connect both true and
complement digitlines ( D and D*)
Coming from single array, increased
layout area, increase noise immunity
Digitline twisting scheme
 Open DRAM array

mbit tr. Gate terminal is connected to wordline

same poly si as gate

Wordline is orthogonal to digitline

Mbits along a given digitline don’t share
common wordline and vice versa

mbits are paired to share common contact to digitline, reduces array size
• As the integration density of DRAM has grown, new
types of memory array noise inherent in the scaled
memory cell array have emerged as inevitable
problems:

– inter-bitline coupling noise due to the bitline-bitline

coupling capacitance, increased as the bitline pitch
becomes smaller, and

– bitline wordline feedback noise due to mirror

capacitance of the transfer-gate transistors
• Twisting scheme equalizes the coupling terms
from each digitline to all other digitlines, both true
and complement

– Each digitline twisting consume silicon area

– Proper implementation cancel noise terms

– Coupling between adjacent metal lines is inversely

proportional to the line spacing, signal-noise problem
gets increasingly worse as DRAMs scale to smaller and
smaller dimensions
 SENSE AMP

• Sense amplifier refers to a collection of circuit

elements that pitch up to the digitlines of a DRAM
array
Includes
- isolation transistors, device for digitline equilibration and bias
– One or more Nsense, Psense amp
– Devices connecting selected digitlines to I/O signal lines
Requirement that the physical layout for these circuits is constrained by the digitline
and wordline pitches of an array of Mbits

For eg. SA for a specific digitline pair (column) are generally laid out within the space of 4
Digitlines - quarter pitch
 Equilibration and Bias circuits

Digit lines start at VCC/2 prior to cell access and sensing ,

• For sensing operation, both digitlines are at the same voltage before the wordline is driven HIGH
– Any offset voltage appearing between the pair reduces the signal produced during Access

• Equilibration of the digitlines is accomplished with one or more NMOS transistors connected
between the digitline conductors

• EQ is held at VCC whenever

external row address strobe
signal RAS* is High – precharge
state

After RAS* has fallen, EQ transitions

LOW , EQ tr off prior to a wordline
going HIGH – again RAS* High
Fig. Equilibration and bias layout circuit
• To perform sensing these devices operate to
ensure digitline pair remains at prescribed
voltage

• Digitline at VCC and gnd equilibrate to VCC/2

• VCC/2 precharge is used to reduce power

consumption, read-write times and improve
sensing operations
• Isolation devices
– NMOS transistors placed between array digitlines and
sense amplifiers
– If the sense amps are positioned between and
connected to two arrays – electrically isolate one of
the two arrays – reduce digitline capacitance-
speeding read-write times- reduce power
consumption – extending refresh for isolated arrary
• They electrically isolate one of the two arrays
• Provides resistance between sense amplifier and digitlines
• Stabilizes sense amplifiers and speeds up sensing operation
Fig. standard sense amplifier block
 • Input/Output Transistors
– I/O transistors allow data to be read from and
written to specific digitline pairs

Each CSEL
Outputs of can activate
Each I/O transistor 4 digitline pairs
are connected to peripheral
to I/O signal pairs Data path circuits

Two pairs of I/O signal

Lines permit
Four I/O transistors
to share
CSEL
 Nsense and Psense Amplifiers
• Fundamental Elements of any sense amplifier
• To access signal voltage and drive digitline to
Vcc and gnd

Fig. Basic sense amplifier block

• Nsense drives low-potential digitline to ground
• Psense drives HIGH potential digitline to Vcc

• SA are designed to detect and amplifies small

signal voltage (less than 200 mv)

• Matching of Vth, gm, Cj ensures reliable sense

amplifier operation

• Layout dictates overall balance and performance

•
• DRAM designs latch digitlines to Vcc and gnd
– Maintaining lower VDS and –ve VGS across non-
accessed mbit transistors , reduces Iss and longer
refresh times despite smaller stored charge
• Rate of Activation – rate at which SA are
activated
– Variety of designs multistage circuits to control the
rate at which NLAT* fires

– Two stage circuits reduce cell leakage

– negative VGS extends refresh by reducing Iss

– Trade off noise and speed
Standard sense amplifier block
• Commonly used double or triple-metal designs
– Two Psense amplifiers outside the isolation transistors,
– a pair of EQ/bias (EQb) devices,
– a single Nsense amplifier, and
– a single I/O transistor

Placement of Psense amp outside the isolation devices

is necessary because a full one level (Vcc) cannot pass
through unless the gate terminal of ISO transistors is
driven above Vcc
• Complex sense amplifier block
– Single Psense amplifier
– sets of Nsense amplifier
– Gurantees faster sensing and higher stability
• Reduced sense amplifier block
– One Nsense and Psense amp
– Both placed within isolation transistors
– EQ/bias circuits to maintain equilibration on
isolated array
Single-metal sense amplifier block

Single-metal sense amps are laid out at half pitch

One amplifier for every two array digitlines

• Difficult and places tight constraints on process
design margins

• Nsense and Psense are placed on separate ends

of the arrays

• Sharing sense amps between arrays is especially

beneficial for single-metal designs

• I/O device on only one end

 Array Architectures
For large scale DRAMs two types are most prevalent :

• Open digitline array architecture

• Folded digitline array architecture

217
• Multiple crosspoint array cores separated by
strips of sense amplifier blocks and row decode
blocks

• Each 128kbit array core is built using 6F2 Mbit

cell pairs
• Mbits arranged in 264 rows,
– 256 actual wordlines, 4 redundant wordlines, 4
dummy wordlines
– In 524 digitlines, 512 acutual digitlines, 8 redundant
digitlines, 4 dummy digitlines
• Photolithography problem occurs at the edge of
large repetitive structures, such as Mbit arrays
(malformed or non-uniform structures rendering edge
cells useless- including dummy ensures problem occur
On dummy cells- enlarge array str. – significantly
improve yield)
 0.25 um design parameters

32Mbit memory
Blocks

For use in 256-Mbit

DRAM
• Size of each array core have 2N row addresses and 2M
column addresses for a given part, there are 2 N+M
addressable Mbits, binary number

• Address decoding is greatly simplified within a DRAM if

array address boundaries are derived directly from
address bits
• Set of factors limiting array core size involves practical
limitations on digitline and WL length
– Ratio of cell to digitline capacitance to ensure reliable sensing
– Operating current and power for DRAM is determined by
current required for charge and discharge digitlines
during each active cycle
• The power dissipated during a Read or refresh operation
is proportional to digitline capacitance (CD), supply voltage
(Vcc), No. of active columns (N), Refresh period (P)

power dissipation is
PD = Vcc2 . N( CD + Cc)/2P watts

For a wordline connected to N( active columns) Mbits

RWL = (Rs. N.PDL)/ WLW

CWL = CW8. N farads

PDL – digitline pitch, WLW – wordline width CW8 – wordline

capacitance in an 8F2 Mbit cell
Active current and power versus digitline
256 Mbit length

Open digitline arch

Does not support
Digitline twisting
Because of true and
Complete digitlines
Wordline time constant versus wordline length
• 32 –Mbit array requires total of 256 – 128kbit
array cores

256 array cores in

16 X 16 arrangement

16 – 2 Mbit sections
are required to form
Complete 32Mbit block

Sense Amp is positioned

Vertically between
Each 2-Mbit section
Open digitline 32-Mbit array block
• Sense amplifier strips are positioned vertically
and row decode strips or wordline stitching strips
are positioned horizontally between each array
core

• Layout can be generated for various 32-Mbit is

necessary for pitch cell size
– Overall dimensions of memory block can be
calculated
• Overall height of 32Mbit

• TR – number of local decoders

• HLDEC – height of each decoder
• TDL – number of digitlines redundant and dummy
• PDL – digitline pitch

Over all height can be found by Summing the height of row decode blocks together
With the product digitline pitch and total no. of digitlines
• Width of 32-Mbit

• TSA – number of SA
• WAMP – width of SA
• TWL – total number of wordlines redundant
and dummy lines
• PWL6 – wordline pitch for 6F2 Mbit
• Overall size is the best measure of architectural
efficiency
– Array efficiency is determined by dividing the area
consumed by functionally addressable Mbits by total
die area – peripheral circuits area is ignored

Array efficiency for 32-Mbit block is

Efficiency = (100. 225. PDL. PWL6)/Area32 %

225 – number of addressable Mbits in each 32-Mbit

block
Open digitline – 32 Mbit size
 Folded Array Architecture
•
• Array Architecture objectives

• Open digitline achieve smaller array layouts

6F2 Mbit cells - Suffer from poor signal-to-
noise performance

• Sense amplifier layout – half pitch – one sense

amplifier for every two digitlines
• Superior signal-to-noise – larger array layouts

• Sense amplifier layout is simplified because

array configuration is quarter pitch – one
sense amplifier for every four digitlines.
• Wordline driver layout is more difficult because
the wordline pitch is effectively reduced in folded
architecture
• Main array arch. objectives
– Open digitline Mbit configuration
– Small 6F2 Mbit
– Small, efficient array layout
– Folded digitline sense amplifier configuration
– Adjacent true and complement digitlines
– Twisted digitline pairs
– Relaxed wordline pitch
– High signal-noise ratio