WIRELESS SENSOR NETWORKS

& IOT

Prof. R. Sivacoumar
TT601, MEMS Design Lab
9952840844
 What are sensor networks?
• Networks of devices that are able to sense the environment,
perform on-board computation, (and communicate)
• Why? Because we can: Technology
– Circuit integration.
• Ability to integrate more functions into chip with lower energy
– Wireless communication.
• Better communication theory
• Better devices
• Bit-rates are slowly increasing
• Transmission power is decreasing
– Sensor technology
 Result: sensing nodes

PC-104+
UCLA TAG
UCB Mote
 Embedded Networked Sensing
• Micro-sensors,
– on-board processing,
– wireless interfaces
– small scale and low cost => many
– monitor phenomena “up close”.
• Enables spatially and temporally dense monitoring.
– Nyquist Sampling – you must sample often enough (in time or space)
– Inverse problems are very difficult, e.g., by sensing the temperature at a
few places, determine the temperature everywhere (numerically
unstable). Instead, directly sense the temperature everywhere.
– Wireless interface allow little infrastructure – easy deployment
– Wireless interface allow cooperation and distributed computing
 Sensor networks applications…
Embed numerous
sensing nodes to
monitor and interact
with physical world

Network these devices

so that they can
execute more complex tasks.
Sensor networks applications…
 Vision: “Embed the World”
• Buildings self-detect and self-correct from structural faults (e.g., weld
cracks).
• Schools detect airborne toxins at low concentrations, trace contaminant
transport to source.
• Buoys alert swimmers to dangerous bacterial levels.
• Earthquake-rubbled building infiltrated with robots and sensors: locate
survivors, evaluate structural damage.
• Ecosystems infused with chemical, physical, acoustic, image sensors to
track global change parameters.
• More??
 Deployments
• Ecological Habitat Monitoring
– UCB/Intel Berkeley: Great Duck Island
– UCLA-CENS: James Reserve
– Princeton: ZebraNet in Kenya
• Structural Monitoring
– UCLA-CENS: Factor Building
– USC: Networked SHM
– UCB/Intel Berkeley: SF Golden Gate Bridge
– UD
• Biomedical Applications
– Artificial retina
– “Bio-monitors”
• Industrial and Commercial Apps
– Ember Corp: Thermal Process Control, Shipment Tracking
– CCM
 Environmental monitoring
• Petrel habitat on Great Duck Island in Maine.
• Questions to answer:
– Usage pattern of nesting burrows over the 24-72 hour cycle.
– Changes in the burrow and surface environmental parameters.
– Differences in the micro-environments with and without large
numbers of nesting petrels.
Hierarchical deployment
 Sensors
• Mica platform
– Atmel AVR w/ 512kB Flash
– 916MHz 40kbps RFM Radio
• Range: max 100 ft
• Affected by obstacles, RF propogation
– 2 AA Batteries, boost converter
• Mica weather board – “one size fits all”
– Digital Sensor Interface to Mica
• Onboard ADC sampling analog photo, humidity and passive IR sensors
• Digital temperature and pressure sensors
– Designed for Low Power Operation
• Individual digital switch for each sensor
– Designed to Coexist with Other Sensor Boards
• Hardware “enable” protocol to obtain exclusive access to connector
resources
• Packaging
– Conformal sealant + acrylic tube
– Placement
– Place above ground and in burrows (propagation?)
 Gateway
• Communicate with sensor and base station.
• Solar powered (sensors are just battery
powered).
• Directional antenna pointed toward base
station.
 Base station
• Laptops

• In lighthouse keepers house.

• Log all data and transmit via

satellite to D.C. and then on to
the Internet.
 Smart Dust
•Design goals
–Cubic millimeter.
–Very low energy.

•Result: sensor package containing:

–Sensors
–Transmitter (passive and active) and receiver
–Signal processing
–Solar power source
 Smart dust applications
• Environmental monitoring.
– Insects.
– Meteorological phenomena.
• Special operations.
 Protocols

 A protocol is a set of rules and formats that

govern the communication between
communicating peers
 set of valid messages
 meaning of each message

 Necessary for any function that requires

cooperation between peers
16
 Protocols
• A protocol provides a service
– For example: the post office protocol for reliable parcel
transfer service

• Peer entities use a protocol to provide a

service to a higher-level peer entity
– for example, truck drivers use a protocol to present post
offices with the abstraction of an unreliable parcel transfer
service

17
 Protocol Layers

• A network that provides many services needs many

protocols
• Some services are independent, But others depend on
each other
• A Protocol may use another protocol as a step in its
execution
– for example, ground transfer is one step in the execution of
the example reliable parcel transfer protocol
• This form of dependency is called layering
– Post office handling is layered above parcel ground transfer
protocol.
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 Open protocols and systems

• A set of protocols is open if

– protocol details are publicly available
– changes are managed by an organization whose
membership and transactions are open to the public
• A system that implements open protocols is called
an open system
• International Organization for Standards (ISO)
prescribes a standard to connect open systems
– open system interconnect (OSI)
• Has greatly influenced thinking on protocol stacks
19
 ISO OSI reference model

• Reference model
– formally defines what is meant by a layer, a service etc.
• Service architecture
– describes the services provided by each layer and the
service access point
• Protocol architecture
– set of protocols that implement the service architecture
– compliant service architectures may still use non-
compliant protocol architectures

20
 The seven Layers

Application Application

Presentation Presentation

Session Session

Transport Transport

Network Network Network

Data Link Data Link Data Link

Physical Physical Physical

End system Intermediate End system

system
21
 Serial Communication Overview
• Layering
– Break complexity of communication protocol into pieces easier to design and
understand
– Lower levels provide services to higher level
• Lower level might work with bits while higher level might work with packets of data
– Physical layer
• Lowest level in hierarchy
• Medium to carry data from one actor (device or node) to another
• Parallel communication
– Physical layer capable of transporting multiple bits of data
• Serial communication
– Physical layer transports one bit of data at a time
• Wireless communication
– No physical connection needed for transport at physical layer
 Transmission Illustration
Serial Parallel
Receiver Receiver
Serial
1 bit Transfers one bit at a time on
one data line

Parallel
N bits transmitted at a time
over N data lines
1 word
Synchronization among all N
bits

Note: each N bit is called a

word
Transmitter Transmitter
 Data Transmission
Serial Parallel
Cost Cheap Expensive

Speed Slow Fast

Transmission Single bit 8 bits (8 data lines)

Amount Transmitter & Receiver

TransmissionLin One line to transmit 8 lines for simultaneous

es one to receive transmission

TransmissionDis Long distance Short distance

tance (synchronization)

Example Modem Printer Connection

 Parallel communication
• Multiple data, control, and possibly power wires
– One bit per wire
• High data throughput with short distances
• Typically used when connecting devices on same IC or same
circuit board
– Bus must be kept short
• long parallel wires result in high capacitance values which requires more
time to charge/discharge
• Data misalignment between wires increases as length increases
• Higher cost, bulky

25
 Serial communication
• Single data wire, possibly also control and power wires
• Words transmitted one bit at a time
• Higher data throughput with long distances
– Less average capacitance, so more bits per unit of time
• Cheaper, less bulky
• More complex interfacing logic and communication protocol
– Sender needs to decompose word into bits
– Receiver needs to recompose bits into word
– Control signals often sent on same wire as data increasing protocol
complexity

26
 Serial Communications
• Synchronous • Asynchronous
– Synchronous Peripheral Interface (SPI) – Serial Communication Interface (SCI)
• Constant transmission of data • Transmission of data through “words”
• Clocks of Transmitter and Receiver must • Continuous transmission unnecessary
be synchronized • Built-in safeguards against noise and
• No safeguard against error or noise error
• Data rates depend on clock rates • Transmitter and Receiver operate
• Flexible to communication with peripheral independently
devices • Requires start and stop bit for each
– LCD drivers, A/D converter, other byte of data
microprocessors – Sends constant ‘1’ for idle
• Simultaneously transmits and receives – Sends a ‘0’ for start and “1” for stop bits
data • Very reliable data reception
– Transmission line, Receiving line, and
Ground
 Asynchronous Serial
• Transmission
With asynchronous communication, the transmitter and
receiver do not share a common clock
Add: Start, Stop, Parity Bits Remove: Start, Stop, Parity Bits

Transmitter + – Receiver
Data

1 byte-wide Data 1 byte-wide Data

The Transmitter The Receiver

¨ Shifts the parallel data onto ¨ Extracts the data using its own
the serial line using its own clock
clock
¨ Converts the serial data back to
¨ Also adds the start, stop and the parallel form after stripping
parity check bits off the start, stop and parity bits
 Asynchronous Serial
Transmission
• Start bit—indicates the beginning of the data word
• Stop bit—indicates the end of the data word
• Parity bit—added for error detection (optional)
• Data bits—the actual data to be transmitted
• Baud rate—the bit rate of the serial port
• Throughput—actual data transmitted per sec (total bits transmitted—
overhead)
– Example: 115200 baud = 115200 bits/sec
– If using 8-bit data, 1 start, 1 stop, and no parity bits, the effective
throughput is: 115200 * 8 / 10 = 92160 bits/sec
 Bit Types

Figure 1. Role of stop, start and parity bits.

• Start Bit –
• Signals the transmission of a word.
• Transition from “1” to “0”. (“Mark-to-space”)
• First bit to be transmitted.
 Data Format

• Idle 1
• Start bit 0
• Data bit 0 or 1
• Parity 0 or 1
• Stop bit 1
Data Data Data Parity
Idle
Bit 1 Bit 3 Bit 6 Bit
HIGH
Stop Bit

LOW
Start Data Data Data Data Data
Bit Bit 0 Bit 2 Bit 4 Bit 5 Bit 7
Ta Kim
 Bit Types (Cont)
• Stop Bits –
• Bit at the end of a data word.
• Bit set to high “1”.
• Indicates the end of a word.

• Data bits –
• Data bits to be transmitted.
• Sender and receiver have to agree in the number of data bits.
(Usually 8 or 9)
• Least significant bit is sent first.
• Can be low or high.
 Bit Types (Cont)
• Parity bit –
• Works as an error check.
• There are two types: odd and even
– Even: if number of 1’s in the data word is even.
– Odd: if number of 1’s in the data word is odd.
• Bit after the data bits and before the stop bit.
• Can prevent single noise signal, but does not recognize
when two bits are altered by noise.
• Used to prevent noise.
Bus types

• USART (Universal Sy/Asyn Rx/Tx)

• RS232
• RS485
• I2C (I2C) = Inter-Integrated Circuit
• SPI = Serial Peripheral Interface = Serial
Peripheral Interface One-wire (Dallas)
• CAN = Controller–Area Network
 RS232
• also called Universal Asynchronus Receiver/
Transmitter (UART)
• or the relevant standards:
– RS232 (-C) or EIA232
 What is RS-232?
• RS-232 is a standard by which two serial
devices communicate:
– The connection must be no longer than 50 feet.
– Transmission voltages are –15V and +15V.
– It is designed around transmission of characters
 RS-232 (cont.)
• One important aspect of RS-232 is that it is an
asynchronous form of communication.
• Asynchronous communication is important
because it is efficient; if no data needs to be
sent, the connection is “idle.” No additional
CPU overhead is required for an idle serial
line.
 Logical Voltages
• RS-232 is a little non-intunitave at first.
• Logical 1 is –15VDC.
• Logical 0 is +15VDC.
• When the connection is idle, the hardware ties
the connection to logical 1.
 How Can You Transmit Data?
• RS-232 communication is dependent on a set
timing speed at which both pieces of
hardware communicate. In other words, the
hardware knows how long a bit should be high
or low.
• RS-232 also specifies the use of “start” and
“stop” bits.
 Sending One Character
• Every time a character is sent, the same
communication occurs:
1. Start bit sent.
2. Seven data bits sent.
3. Stop bit sent.

• This communication is dependent on the fact that

both devices are sampling the bits at the same
rate! We’ll see what happens if this doesn’t
happen…
 Ok, So What’s the Start Bit?
• The start bit is a logical 0 sent on the line to
tell the other device to start sampling.
• Remember, the logical 0 is +15VDC.
 And the Stop Bit?
• The stop bit is a logical 1. –15VDC.
• A stop bit is always sent (per RS-232
standards).
 To Talk the Talk…
• We’ve mentioned that both devices must have the
same speeds to talk, but they must also know to
handle problems.
• The transmission rate of serial devices is called
baud. It is the number of changes in the signal per
second.
• Serial communications does not have to use 7 bits of
length. As a matter of fact, a whole variety of start
and stop bit patterns and bit lengths can be used.
A Sample Transmission
 Common Serial Settings
• Most settings are read in the following form:
– Bits per second
– Number of data bits
– Parity
– Number of Stop bits
 RS-232 Frame
• Every RS-232 consists
of: Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
– 1 start bit
– 8 data bits
– 1 stop bit
– (optional 1 parity bit)

UBC 104 Embedded Systems 46

 RS-232 Frame
• Every RS-232 consists
of:
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
– 1 start bit
– 8 data bits
– 1 stop bit
– (optional 1 parity bit)

• ‘a’= 0x61 = 0110 0001

UBC 104 Embedded Systems 47

 RS-232 Frame
• Every RS-232 consists
of:
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
– 1 start bit
1111
– 8 data bits 0
– 1 stop bit
1
– (optional 1 parity bit)

• ‘a’= 0x61 = 0110 0001

UBC 104 Embedded Systems 48

 RS-232 Frame
• Every RS-232 consists
of:
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
– 1 start bit
1111 0
– 8 data bits 0
– 1 stop bit
1
– (optional 1 parity bit)

• ‘a’= 0x61 = 0110 0001

UBC 104 Embedded Systems 49

 RS-232 Frame
• Every RS-232 consists
of:
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
– 1 start bit
1111 0 1 0 0 0 0 1 1 0
– 8 data bits 0
– 1 stop bit
1
– (optional 1 parity bit)

• ‘a’= 0x61 = 0110 0001

UBC 104 Embedded Systems 50

 RS-232 Frame
• Every RS-232 consists
of:
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
– 1 start bit
1111 0 1 0 0 0 0 1 1 0 0
– 8 data bits 0
– 1 stop bit
1
– (optional 1 parity bit)

• ‘a’= 0x61 = 0110 0001

UBC 104 Embedded Systems 51

 RS-232 Frame
• Every RS-232 consists
of:
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
– 1 start bit
1111 0 1 0 0 0 0 1 1 0 0 11
– 8 data bits 0
– 1 stop bit
1
– (optional 1 parity bit)

• ‘a’= 0x61 = 0110 0001

UBC 104 Embedded Systems 52

 Signal Timing
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop

1111 0 1 0 0 0 0 1 1 0 0 1111

UBC 104 Embedded Systems 53

Signal Timing (continued)
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop

1111 0 1 0 0 0 0 1 1 0 0 1111

?
bit period

UBC 104 Embedded Systems 54

 Full Duplex Transmission
• Full duplex transmission (FDX) occurs when data is
transmitted (or can be transmitted)
simultaneously by both devices. Special wiring is
needed for FDX.
• If only one endpoint may send data – half-duplex
communications or simplex
– Pin 2 - Receive (RxD)
– Pin 3 - Transmit (TxD)
– Pin 4 - Ready to send (RTS)
– Pin 5 - Clear to send (CTS)
– Pin 7 - Ground
 Wiring RS-232
• The RS-232 specification denotes usage of a 25 pin
cable, where each pin has a specific usage.
• However, most devices never need to use all of the
pins, so the cabling requirements for specific devices
may vary.
• Many common serial devices (modems for example),
use a 9 pin serial connection.
 RS-232 DB25 Pin Out

DB-25M Function Abbreviation

Pin #1 Chassis/Frame Ground GND
Pin #2 Transmitted Data TD
Pin #3 Receive Data RD
Pin #4 Request To Send RTS
Pin #5 Clear To Send CTS
Pin #6 Data Set Ready DSR
Pin #7 Signal Ground GND
Pin #8 Data Carrier Detect DCD or CD
Pin #9 Transmit + (Current Loop) TD+
Pin #11 Transmit - (Current Loop) TD-
Pin #18 Receive + (Current Loop) RD+
Pin #20 Data Terminal Ready DTR
Pin #22 Ring Indicator RI
Pin #25 Receive - (Current Loop) RD-
 RS-232 DB9 Pin Out

DB-9M Function Abbreviation

Pin #1 Data Carrier Detect CD
Pin #2 Receive Data RD or RX or RXD
Pin #3 Transmitted Data TD or TX or TXD
Pin #4 Data Terminal Ready DTR
Pin #5 Signal Ground GND
Pin #6 Data Set Ready DSR
Pin #7 Request To Send RTS
Pin #8 Clear To Send CTS
Pin #9 Ring Indicator RI
 Connector Types
• The two different connectors are associated
with two major types of hardware
• The Computer Terminal Equipment (CTE) and
the Data Terminal Equipment (DTE).
• For ease-of-use, a computer will transmit on pin
2 and receive on pin 3 (the CTE, remember).
• Vice versa: a modem will transmit on pin 3, and
receive on pin 2 (for the DTE).
 Speed Limitations
• For people familiar with modem communications,
there is a speed limitation associated with the
transmission.
• 56k (56 kilobit) analog modems are pretty much the
fastest analog modems that consumers are going to
see. This limitation is due to telephone systems, not
the computer systems.
 Speed Limitations (cont.)
• However, serial communications between devices
also has its own speed barrier.
• RS-232 was designed with the understanding that the
analog world is far from perfect.
• Digital is fast, analog is slow. RS-232 is analog,
therefore is it slow (in computing terms).
 Why Is It Slow?

• t exists. The change

is not instantaneous.
• Sampling does not
occur immediately, so
it must wait t+t0
• Cable length increases
delay.
• Etc.
 Noise
• Signal noise is bad. It is caused by a variety of
sources, all of which lead to lower speeds and
less reliable transmission.
• Shannon’s Theorem shows that the maximum
transmission rate of a voice call (analog) is
~30,000 bps (30kbps).
Limitations of RS-232
RS-232 has some serious shortcomings as an electrical interface. A signal on a
single line is impossible to screen effectively for noise. By screening the entire
cable one can reduce the influence of outside noise, but internally generated
noise remains a problem. As the baud rate and line length increase, the effect of
capacitance between the cables introduces serious crosstalk until a point is
reached where the data itself is unreadable. Using low capacitance cable can
reduce crosstalk.
There is a wire for each signal, together with the ground signal (reference for
voltage levels). This interface is useful for point-to-point communication at slow
speeds. For example, port COM1 in a PC can be used for a mouse, port COM2 for a
modem, etc. This is an example of point-to-point communication: one port, one
device. Due to the way the signals are connected, a common ground is required.
This implies limited cable length - about 30 to 60 meters maximum. (Main
problems are interference and resistance of the cable.) Shortly, RS 232 was
designed for communication of local devices, and supports one transmitter and
one receiver.
 RS422/485
The 422 and 485 standards, as they are known today, are
balanced data-transmission schemes that offer robust
solutions for transmitting data over long distances and noisy
environments.
These standards don’t specify a logical communication
protocol, and are used as the physical layer specification by
many protocols such as Modbus, Profibus, DIN-Measurement-
Bus and many others.
 RS422
• The TIA/EIA-422 standard, known as RS422, describes a
communication interface that uses balanced data transmission
over multiple pairs of wires to establish communication from
one transmitter to up to 10 receivers.
• At least two twisted pairs of wires are used, one for
communication from the transmitter (usually the master) to the
receivers (usually the slaves), and the other for transmission
from the slaves back to the master.
• Since multiple slaves share the same wires for transmission,
they must keep their line drivers turned off (in high impedance
state) most of the time. When data from a slave is requested, it
turns on its line driver, transmit data and turn it off again to
allow transmission from another slave.
• Use of two pairs of wires allows master and one slave to
transmit data at the same time, which is called full-duplex
operation.
 RS422
• The TIA/EIA-485 standard, known as RS485, describes a
communication interface that uses balanced data transmission
over one or two pairs of wires to establish communication
between 32 “load units”.
• Usually, each network device (transmitter and receiver)
corresponds to one “unit load”, thus resulting in a 32 devices
network. New devices can have fractional “unit loads”,
increasing the allowed number of networked devices.
• RS485 networks usually communicate using a twisted-pair of
wires, where data flows in both directions. Each device turns on
its line driver only when transmitting data, and keeps it off (in
high impedance state) for the remaining time to allow other
devices to transmit.
• Only one device can transmit at a time, which is called a half-
duplex operation. RS485 networks can also operate using 2 pairs
of wires, in full-duplex mode, as described for RS422.
 BALANCED DIFFERENTIAL
• Both RS485 and RS422LINES
use balanced differential lines for
communication, usually twisted pairs of wires.
• Line drivers and receivers for these interfaces use as data
information the voltage difference between the two lines of the
same pair.
• Binary data are identified by the polarity of this voltage
difference, defining that the data is a logical ‘1’ when the
polarity is positive (voltage level in “+” wire is higher than in “-“
wire) and ‘0’ when the polarity is negative (voltage level in “-”
wire is higher than in “+“ wire).
• A noise margin of ±0.2 V level is defined to enhance noise
immunity. The balanced data transmission cancels the induced
noise, since the same noise is induced in both conductors of the
pair, preserving the voltage difference that carries the
information. The radiated noise of a balanced communication
bus is also lower than the one of a non-differential bus.
IDEAL CONDITION
COMPARISON OF RS
232/422/485
 Synchronous Serial IO
• Send a separate clock line with data
– SPI (serial peripheral interface) protocol
– I2C (or I2C) protocol
• Encode a clock with data so that clock be
extracted or data has guaranteed transition
density with receiver clock via Phase-
Locked-Loop (PLL)
– IEEE Firewire (clock encoded in data)
– USB (data has guaranteed transition density)

V 0.3 74
 Serial Peripheral Interface
• What is it?

• Basic SPI

• Capabilities
Serial Peripheral Interface
http://upload.wikimedia.org/wikipedia/commons/thumb/e/ed/
SPI_single_slave.svg/350px-SPI_single_slave.svg.png

• Protocol

• Pros and Cons

• Uses
75
 What is SPI?
• Serial bus protocol
• Fast, easy to use, and simple
• Very widely used
• Not “standardized”

76
 SPI Basics
• A 4-wire communications bus
• Typically communicate across short distances
• Supports
– Single master
– Multiple slaves
• Synchronized
– Communications are “clocked”

77
 SPI Capabilities
• Always full-duplex
– Communicates in both directions simultaneously
– Transmitted (or received) data may not be
meaningful
• Multiple Mbps transmission speeds
– 0-50 MHz clock speeds not uncommon
• Transfer data in 4 to 16 bit characters
• Supports multiple slaves

78
 SPI bus wiring

• Bus wires
– Master-Out, Slave-In (MOSI)
– Master-In, Slave-Out (MISO)
– System Clock (SCLK)
– Slave Select/Chip Select (SS1#, …, SS#n or CS1, …, CSn)
• Master asserts slave/chip select line
• Master generates clock signal
• Shift registers shift data in and out
79
 SPI signal functions

• MOSI – carries data out of master to slave

• MISO – carries data out of slave to master
– Both MOSI and MISO are active during every
transmission
• SS# (or CS) – unique line to select each slave chip
• SCLK – produced by master to synchronize transfers

80
 SPI uses a “shift register” model of
communications

Master shifts out data to Slave, and shifts in data from Slave
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81
 Two bus configuration models

Some wires have been renamed

Master and multiple daisy-

chained slaves
Master and multiple independent http://www.maxim-ic.com/appnotes.cfm/an_pk/3947

slaves
http://upload.wikimedia.org/wikipedia/commons/thumb/f/fc/SPI_three_sla
ves.svg/350px-SPI_three_slaves.svg.png

82
SPI clocking: there is no “standard way”
• Four clocking “modes”
– Two phases
– Two polarities
• At CPOL=0 the base value of the clock is zero, i.e. the idle state is 0
and active state is 1.
– For CPHA=0, data are captured on the clock's rising edge (low→high
transition) and data is output on a falling edge (high→low clock
transition).
– For CPHA=1, data are captured on the clock's falling edge and data is
output on a rising edge.
• At CPOL=1 the base value of the clock is one (inversion of CPOL=0),
i.e. the idle state is 1 and active state is 0.
– For CPHA=0, data are captured on clock's falling edge and data is output
on a rising edge.
– For CPHA=1, data are captured on clock's rising edge and data is output on
a falling edge.
83
 SPI timing diagram
Master and selected slave must be in the same mode
During transfers with slaves A and B, Master must
Configure clock to Slave A’s clock mode
Select Slave A
Do transfer
Deselect Slave A
Configure clock to Slave B’s clock mode
Select Slave B
Do transfer
Deselect Slave B
Master reconfigures clock
mode on-the-fly!

Timing Diagram – Showing Clock polarities and phases 84

http://www.maxim-ic.com.cn/images/appnotes/3078/3078Fig02.gif
 SPI tradeoffs: the pros and cons
• Pros
– Fast for point-to-point connections
– Easily allows streaming/constant data inflow
– No addressing in protocol, so it’s simple to implement
– Broadly supported

• Cons
– Slave select/chip select makes multiple slaves more
complex
– No acknowledgement (can’t tell if clocking in garbage)
– No inherent arbitration
– No flow control (must know slave speed)
85
 The I C Bus
2

• What is the I2C Bus and what is it used for?

• Bus characteristics
• I2C Bus Protocol
• Data Format
• Typical I2C devices
• Example device

86 of 40
 What is I C 2

• The name stands for “Inter - Integrated Circuit Bus”

• A Small Area Network connecting ICs and other electronic
systems
• Originally intended for operation on one
single board / PCB
– Synchronous Serial Signal
– Two wires carry information between
a number of devices
– One wire use for the data
– One wire used for the clock
• Today, a variety of devices are available with I2C Interfaces
– Microcontroller, EEPROM, Real-Timer, interface chips, LCD driver, A/D
converter

87 of 40
 What is I C used for?
2

• Data transfer between ICs and systems at relatively low

rates
– “Classic” I2C is rated to 100K bits/second
– “Fast Mode” devices support up to 400K bits/second
– A “High Speed Mode” is defined for operation up to 3.4M
bits/second
• Reduces Board Space and Cost By:
– Allowing use of ICs with fewer pins and smaller packages
– Greatly reducing interconnect complexity
– Allowing digitally controlled components to be located close to
their point of use

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 I C Bus Characteristics
2

• Includes electrical and timing specifications,

and an associated bus protocol
• Two wire serial data & control bus implemented with the
serial data (SDA) and clock (SCL) lines
– For reliable operation, a third line is required:
Common ground
• Unique start and stop condition
• Slave selection protocol uses a 7-Bit slave address
– The bus specification allows an extension to 10 bits
• Bi-directional data transfer
• Acknowledgement after each transferred byte
• No fixed length of transfer

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 I C Bus Characteristics (cont’d)
2

• True multi-master capability

– Clock synchronization
– Arbitration procedure
• Transmission speeds up to 100Khz
(classic I2C)
• Max. line capacitance of 400pF,
approximately 4 meters (12 feet)
• Allows series resistor for IC protection
• Compatible with different IC technologies
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 I C Bus Definitions
2

• Master:
– Initiates a transfer by generating
start and stop conditions
– Generates the clock
– Transmits the slave address
– Determines data transfer direction
• Slave:
– Responds only when addressed
– Timing is controlled by the clock line
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I C Bus Configuration Example
2

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 I C Hardware Details
2

• Devices connected to the bus must have an open drain or

open collector output for serial clock and data signal
• The device must also be able to sense the logic level on
these pins
• All devices have a common ground reference
• The serial clock and data lines are connected to Vdd(typically
+5V) through pull up resistors
• At any given moment the I2C bus is:
– Quiescent (Idle), or
– in Master transmit mode or
– in Master receive mode.

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 I2C Electrical Aspects

• I2C devices are wire ANDed together.

• If any single node writes a zero, the entire line is zero
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 Bit Transfer on the I2C Bus
• In normal data transfer, the data line only changes state
when the clock is low

SDA

SCL
Data line stable; Change
Data valid of data
allowed

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 Start and Stop Conditions
A transition of the data line while the clock line is high is
defined as either a start or a stop condition.
Both start and stop conditions are generated by the bus
master
The bus is considered busy after a start condition, until a stop
condition occurs

SDA SDA

SCL SCL

Start Stop
Condition Condition
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 I C Addressing
2

• Each node has a unique 7 (or 10) bit address

• Peripherals often have fixed and programmable
address portions
• Addresses starting with 0000 or 1111 have special
functions:-
– 0000000 Is a General Call Address
– 0000001 Is a Null (CBUS) Address
– 1111XXX Address Extension
– 1111111 Address Extension – Next Bytes are the Actual
Address
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 Data Transfer on the I2C Bus

R/Wr 0 – Slave written to by Master

1 – Slave read by Master

ACK – Generated by the slave whose address has been output.

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 I C Bus Connections
2

• Masters can be
– Transmitter only
– Transmitter and receiver
• Slaves can be
– Receiver only
– Receiver and transmitter

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 Acknowledgements
• Master/slave receivers pull data line low for one clock pulse
after reception of a byte
• Master receiver leaves data line high after receipt of the last
byte requested
• Slave receiver leaves data line high on the byte following the
last byte it can accept

Transmitter releases SDA

line during 9th clock
pulse.

Acknowledgement
from receiver

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 Acknowledgements
• From Slave to Master Transmitter:
– After address received correctly
– After data byte received correctly
• From Slave to Master Receiver:
– Never (Master Receiver generates ACK)
• From Master Transmitter to Slave:
– Never (Slave generates ACK)
• From Master Receiver to Slave:
– After data byte received correctly
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 Negative Acknowledge
• Receiver leaves data line high for one clock
pulse after reception of a byte
Transmitter releases SDA
line during 9th clock
pulse.

Not acknowledgement
(NACK) from receiver

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 Negative Acknowledge (Cont’d.)
• From Slave to Master Transmitter:
– After address not received correctly
– After data byte not received correctly
– Slave Is not connected to the bus
• From Slave to Master Receiver:
– Never (Master Receiver generates ACK)
• From Master Transmitter to Slave:
– Never (Slave generates ACK)
• From Master Receiver to Slave:
– After last data byte received correctly

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 Data Transfer on the I2C Bus
• Start Condition
• Slave address + R/W
– Slave acknowledges with ACK
• All data bytes
– Each followed by ACK
• Stop Condition

SDA

ACK from Slave ACK from

Receiver

SCL
Remember : Clock is produced by Master
Start Stop

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 Data Formats
Master writing to a Slave

A A A

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 Data Formats Cont’d.
Master reading from a Slave :
Master is Receiver of data and Slave is Transmitter of data.

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 Data Formats Cont’d.
Combined Format

A repeated start avoids releasing the bus and therefore

prevents another master from taking over the bus
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 Multi-master I C Systems 2

• Multimaster situations require two additional features

of the I2C protocol
• Arbitration:
– Arbitration is the procedure by which competing masters
decide final control of the bus
– I2C arbitration does not corrupt the data transmitted by the
prevailing master
– Arbitration is performed bit by bit until it is uniquely resolved
– Arbitration is lost by a master when it attempts to assert a
high on the data line and fails

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 Arbitration Between Two Masters

• As the data line is like a wired AND, a ZERO address bit overwrites a ONE
• The node detecting that it has been overwritten stops transmitting and
waits for the Stop Condition before it retries to arbitrate the bus

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 Error Checking
• I2C defines the basic protocol and timing
– Protocol errors are typically flagged by the interface
– Timing errors may be flagged, or in some cases could be
interpreted as a different bus event
• Glitches (if not filtered out) could potentially cause:
– Apparent extra clocks
– Incorrect data
– “Locked” bus
• Microprocessors communicating with each other
can add a checksum or equivalent

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 Bus Recovery
• An I2C bus can be “locked” when:
– A Master and a Slave get out of synch
– A Stop is omitted or missed (possibly due to noise)
– Any device on the bus holds one of the lines low
improperly, for any reason
– A shorted bus line
• If SCL can be driven, the Master may send extra
clocks until SDA goes high, then send a Stop.
• If SCL is stuck low, only the device driving it can
correct the problem.
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 Type of I C Implementations
2

• Byte Oriented Interface

– Data is handled one byte at a a time
– Processor interprets a status byte when an event occurs
– For instance Philips 8xC554, 8xC591
• Bit Oriented Interface
– Processor is involved in every bus event when the interface is not Idle
• “Bit Banged”
– Implemented completely in software on 2 regular I/O pins of the
microcontroller
– Works for single master systems
– Not recommended for Slave devices or Multimaster systems

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 Available I C Devices
2

• Analog to Digital Converters (A/D, D/A): MMI functions,

battery & converters, temperature monitoring, control systems
• Bus Controller: Telecom, consumer electronics, automotive,
Hi-Fi systems, PCs, servers
• Bus Repeater, Hub & Expander: Telecom, consumer
electronics, automotive, Hi-Fi systems, PCs, servers
• Real Time Clock (RTC)/Calendar: Telecom, EDP, consumer
electronics, clocks, automotive, Hi-Fi systems, FAX, PCs,
terminals
• DIP Switch: Telecom, automotive, servers, battery &
converters, control systems
• LCD/LED Display Drivers: Telecom, automotive instrument
driver clusters, metering systems, POS terminals, portable
items, consumer electronics

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 Available I C Devices
2

• General Purpose Input/Output (GPIO) Expanders and LED

Display Control: Servers, keyboard interface, expanders, mouse
track balls, remote transducers, LED drive, interrupt output, drive
relays, switch input
• Multiplexer & Switch: Telecom, automotive instrument driver
clusters, metering systems, POS terminals, portable items,
consumer electronics
• Serial RAM/ EEPROM: Scratch pad/ parameter storage
• Temperature & Voltage Monitor: Telecom, metering systems,
portable items, PC, servers
• Voltage Level Translator: Telecom, servers, PC, portable items,
consumer electronics

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 End use
• Telecom: Mobile phones, Base stations,
Switching, Routers
• Data processing: Laptop, Desktop, Workstation,
Server
• Instrumentation: Portable instrumentation,
Metering systems
• Automotive: Dashboard, Infotainment
• Consumer: Audio/video systems, Consumer
electronics (DVD, TV etc.)
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 Applications
• There are some specific applications for
certain types of I2C devices such as TV or radio
tuners, but in most cases a general purpose I2C
device can be used in many different
applications because of its simple
construction.

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 I2C designer benefits
• Functional blocks on the block diagram
correspond with the actual ICs; designs proceed
rapidly from block diagram to final schematic
• No need to design bus interfaces because the
I2C-bus interface is already integrated on-chip
• Integrated addressing and data-transfer protocol
allow systems to be completely software-defined
• The same IC types can often be used in many
different applications
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 I2C designer benefits
• Design-time improves as designers quickly become familiar with
the frequently used functional blocks represented by I 2C-bus
compatible ICs
• ICs can be added to or removed from a system without affecting
any other circuits on the bus
• Fault diagnosis and debugging are simple; malfunctions can be
immediately traced
• Software development time can be reduced by assembling a
library of reusable software modules
• The simple 2-wire serial I2C-bus minimizes interconnections so ICs
have fewer pins and there are fewer PCB tracks; resulting in
smaller and less expensive PCBs

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 I C Manufacturers benefits
2

• The completely integrated I2C-bus protocol eliminates the

need for address decoders and other ‘glue logic’

• The multi-master capability of the I2C-bus allows rapid

testing/alignment of end-user equipment via external
connections to an assembly-line

• Increases system design flexibility by allowing simple

construction of equipment variants and easy upgrading to
keep design up-to-date

• The I2C-bus is a de facto world standard that is implemented

in over 1000 different ICs (Philips has > 400) and licensed to
more than 70 companies

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