Counters

Introduction: Counters
 Counters are circuits that cycle through a specified number of states.
 Two types of counters:
 synchronous (parallel) counters

 asynchronous (ripple) counters

 Ripple counters allow some flip-flop outputs to be used as a source of

clock for other flip-flops.
 Synchronous counters apply the same clock to all flip-flops.
Asynchronous (Ripple)
Counters
 Asynchronous counters: the flip-flops do not change
states at exactly the same time as they do not have a
common clock pulse.
 Also known as ripple counters, as the input clock pulse
“ripples” through the counter – cumulative delay is a
drawback.
 n flip-flops  a MOD (modulus) 2n counter. (Note: A
MOD-x counter cycles through x states.)
 Output of the last flip-flop (MSB) divides the input clock
frequency by the MOD number of the counter, hence a
counter is also a frequency divider.
Asynchronous (Ripple) Counters
 Example: 2-bit ripple binary counter.
 Output of one flip-flop is connected to the clock input of the next
more-significant flip-flop.

HIGH

J Q0 J Q1
CLK C C
Q0
K K

FF0 FF1

CLK 1 2 3 4

Q0 Timing diagram
00  01  10  11  00 ...
Q0 0 1 0 1 0

Q1 0 0 1 1 0
Asynchronous (Ripple) Counters
 Example: 3-bit ripple binary counter.
HIGH

J Q0 J Q1 J Q2
CLK C Q0 C Q1 C
K K K
FF0 FF1 FF2

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2 0 0 0 0 1 1 1 1 0

Recycles back to 0
Asynchronous (Ripple) Counters
 Propagation delays in an asynchronous (ripple-clocked) binary
counter.
 If the accumulated delay is greater than the clock pulse, some
counter states may be misrepresented!

CLK 1 2 3 4

Q0

Q1

Q2
tPHL (CLK to Q0) tPHL (CLK to Q0)
tPLH (Q0 to Q1) tPHL (Q0 to Q1)
tPLH
tPLH (Q1 to Q2)
(CLK to Q0)
Asynchronous (Ripple) Counters
 Example: 4-bit ripple binary counter (negative-edge triggered).

HIGH
Q0 Q1 Q2 Q3
J J J J
CLK C C C C
K K K K
FF0 FF1 FF2 FF3

CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Q0

Q1

Q2

Q3
 n
Asyn. Counters with MOD no. < 2
 States may be skipped resulting in a truncated sequence.
 Technique: force counter to recycle before going through all of the
states in the binary sequence.
 Example: Given the following circuit, determine the counting
sequence (and hence the modulus no.)

C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs Q K Q K Q K
CLR CLR CLR
are 1
(HIGH). B
C
 n
Asyn. Counters with MOD no. < 2
 Example (cont’d):
C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs Q K Q K Q K
CLR CLR CLR
are 1
(HIGH). B
C

1 2 3 4 5 6 7 8 9 10 11 12
Clock MOD-6 counter
A produced by
clearing (a MOD-8
B
binary counter)
C when count of six
NAND 1 (110) occurs.
Output 0
 n
Asyn. Counters with MOD no. < 2
 Example (cont’d): Counting sequence of circuit (in CBA order).

1 2 3 4 5 6 7 8 9 10 11 12
Clock
A 0 1 0 1 0 1 0 1
0 0 1 1 0 0 0 0
B
0 0 0 0 1 1 0 0
C
NAND 1
Output 0

11 00
Temporary 00
1 0
state 1 Counter is a MOD-6
11 01 counter.
0 0
10 01
1 10 1
0
 n
Asyn. Counters with MOD no. < 2
 Exercise: How to construct an asynchronous MOD-5 counter? MOD-7
counter? MOD-12 counter?
 Question: The following is a MOD-? counter?

F Q J
E Q J
D Q J
C Q J
B Q J
A Q J

Q K Q K Q K Q K Q K Q K
CLR CLR CLR CLR CLR CLR

C
D
E All J = K = 1.
F
 n
Asyn. Counters with MOD no. < 2
 Decade counters (or BCD counters) are counters with 10 states
(modulus-10) in their sequence. They are commonly used in daily
life (e.g.: utility meters, odometers, etc.).
 Design an asynchronous decade counter.

(A.C)'

HIGH
D C B A
J Q J Q J Q J Q

CLK C C C C
K K K K
CLR CLR CLR CLR
 n
Asyn. Counters with MOD no. < 2
 Asynchronous decade/BCD counter (cont’d).

HIGH D C B A
J Q J Q J Q J Q (A.C)'
CLK C C C C
K K K K
CLR CLR CLR CLR

1 2 3 4 5 6 7 8 9 10 11
Clock
D 0 1 0 1 0 1 0 1 0 1 0
C 0 0 1 1 0 0 1 1 0 0 0
B 0 0 0 0 1 1 1 1 0 0 0
A 0 0 0 0 0 0 0 0 1 1 0
NAND
output
 Asynchronous Down Counters
 So far we are dealing with up counters. Down counters, on the
other hand, count downward from a maximum value to zero, and
repeat.
 Example: A 3-bit binary (MOD-23) down counter.

1
Q0 Q1 Q2
J Q J Q J Q 3-bit binary
CLK C C C up counter
Q' K Q' K Q'
K

1
Q0 Q1 Q2
J Q J Q J Q 3-bit binary
CLK C C C down counter
K
Q' K Q' K Q'
 Asynchronous Down Counters
 Example: A 3-bit binary (MOD-8) down counter.

00
00 0 11
1
1 1
Q0 Q1 Q2
J Q J Q J Q 01 11
CLK C C C 0 0
K
Q' K Q' K Q'
01 10
1 10 1
0
CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 1 1 0 0 1 1 0 0

Q2 0 1 1 1 1 0 0 0 0
Synchronous (Parallel) Counters
 Synchronous (parallel) counters: the flip-flops are clocked at the
same time by a common clock pulse.
 We can design these counters using the sequential logic design
process (covered in Lecture #12).
 Example: 2-bit synchronous binary counter (using T flip-flops, or JK
flip-flops with identical J,K inputs).

Present Next Flip-flop

state state inputs
00 01 A1 A0 A1+ A0+ TA1 TA0
0 0 0 1 0 1
0 1 1 0 1 1
11 10
1 0 1 1 0 1
1 1 0 0 1 1
Synchronous (Parallel)
Counters
 Example: 2-bit synchronous binary counter (using T flip-flops, or JK
flip-flops with identical J,K inputs).

Present Next Flip-flop

state state inputs
A1 A0 A1+ A0+ TA1 TA0 TA1 = A0
0 0 0 1 0 1
TA0 = 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1

A0 J A1
J Q Q
C C
K
Q' K Q'

CLK
Synchronous (Parallel)
Counters
 Example: 3-bit synchronous binary counter (using T flip-flops, or JK
flip-flops with identical J, K inputs).

Present Next Flip-flop

state state inputs
A2 A1 A0 A2+ A1+ A0+ TA2 TA1 TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
A1 A1 A1

1 1 1 1 1 1 1
A2 1 A2 1 1 A2 1 1 1 1
A0 A0 A0

TA2 = A1.A0 TA1 = A0 TA0 = 1

Synchronous (Parallel)
Counters
 Example: 3-bit synchronous binary counter (cont’d).
TA = A .A
2 1 0 TA = A TA = 1
1 0 0

A2 A1 A0

Q Q Q
J K J K J K
CP
1
Synchronous (Parallel)
Counters
 Note that in a binary counter, the n
always complemented whenever
th bit (shown underlined) is

011…11  100…00
or 111…11  000…00
 Hence, Xn is complemented whenever Xn-1Xn-2 ... X1X0
= 11…11.
 As a result, if T flip-flops are used, then TXn = Xn-1 . Xn-
2 . ... . X1 . X0
Synchronous (Parallel)
Counters
 Example: 4-bit synchronous binary counter.
TA3 = A2 . A1 . A0
TA2 = A1 . A0
TA1 = A0
TA0 = 1

1 A1.A0 A2.A1.A0

A0 J A1 J A2 J A3
J Q Q Q Q
C C C C
K
Q' K Q' K Q' K Q'

CLK
Synchronous (Parallel)
Counters
 Example: Synchronous decade/BCD counter.

Clock pulse Q3 Q2 Q1 Q0
Initially 0 0 0 0
1 0 0 0 1 T0 = 1
2 0 0 1 0 T1 = Q3'.Q0
3 0 0 1 1
4 0 1 0 0 T2 = Q1.Q0
5 0 1 0 1 T3 = Q2.Q1.Q0 + Q3.Q0
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 (recycle) 0 0 0 0
Synchronous (Parallel)
Counters
 Example: Synchronous decade/BCD counter (cont’d).

T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q1.Q0 + Q3.Q0

Q0

1 T T Q1 T Q2 T Q3
Q Q Q Q
C C C C
Q' Q' Q' Q'

CLK
Up/Down Synchronous
Counters
 Up/down synchronous counter: a bidirectional counter that is
capable of counting either up or down.
 An input (control) line Up/Down (or simply Up) specifies the
direction of counting.
 Up/Down = 1  Count upward
 Up/Down = 0  Count downward
Up/Down Synchronous
Counters
 Example: A 3-bit up/down synchronous binary counter.

Clock pulse Up Q2 Q1 Q0 Down

0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

TQ0 = 1 Up counter Down counter

TQ1 = (Q0.Up) + (Q0'.Up' ) TQ0 = 1 TQ0 = 1
TQ1 = Q0 TQ1 = Q0’
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )
TQ2 = Q0.Q1 TQ2 = Q0’.Q1’
Up/Down Synchronous
Counters
 Example: A 3-bit up/down synchronous binary counter (cont’d).

TQ0 = 1
TQ1 = (Q0.Up) + (Q0'.Up' )
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )

Q0 Q1

1 T T T Q2
Q Q Q
Up C C C
Q' Q' Q'

CLK
Designing Synchronous
Counters
 Covered in Lecture #12. 00
00
 Example: A 3-bit Gray code counter 10 0
(using JK flip-flops). 0 1
10 01
1 1
11 01
1 11 0
Present Next Flip-flop 0
state state inputs
Q2 Q1 Q0 Q2+ Q1+ Q0 +
JQ2 KQ2 JQ1 KQ1 JQ0 KQ0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 1 0 X 1 X X 0
0 1 0 1 1 0 1 X X 0 0 X
0 1 1 0 1 0 0 X X 0 X 1
1 0 0 0 0 0 X 1 0 X 0 X
1 0 1 1 0 0 X 0 0 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 1 X 0 X 1 X 0
Designing Synchronous
Counters
 3-bit Gray code counter: flip-flop inputs.

Q1Q0 Q1Q0 Q1Q0

Q2 00 01 11 10 Q2 00 01 11 10 Q2 00 01 11 10

0 0 1 X X 0 1 X X
1
1 X X X X 1 X X 1 X X 1

JQ2 = Q1.Q0' JQ1 = Q2'.Q0 JQ0 = Q2.Q1 + Q2'.Q1'

= (Q2  Q1)'
Q1Q0 Q1Q0 Q1Q0
Q2 00 01 11 10 Q2 00 01 11 10 Q2 00 01 11 10

0 X X X X 0 X X 0 X 1 X
1 1 1 X X 1 1 X 1 X
KQ2 = Q1'.Q0' KQ1 = Q2.Q0 KQ0 = Q2.Q1' + Q2'.Q1
= Q 2  Q1
Designing Synchronous
Counters
 3-bit Gray code counter: logic diagram.
JQ2 = Q1.Q0' JQ1 = Q2'.Q0 JQ0 = (Q2  Q1)'
KQ2 = Q1'.Q0' KQ1 = Q2.Q0 KQ0 = Q2  Q1

Q0 Q1 Q2
J Q J Q J Q
C C C
Q1' Q2'
K Q' K Q' K Q'
Q0 '

CLK
Shift Register Counters

 Ring Counters
 A ring counter is basically a circulating shift register in which
the output of the most significant stage is fed back to the input
of the least significant stage.  The following is a 4-bit ring
counter constructed from D flip-flops.  The output of each stage
is shifted into the next stage on the positive edge of a clock
pulse.  If the CLEAR signal is high, all the flip-flops except the
first one FF0 are reset to 0.  FF0 is preset to 1 instead.
Shift Register Counters

 Since the count sequence

has 4 distinct states, the
counter can be considered as
a mod-4 counter.  Only 4 of
the maximum 16 states are
used, making ring counters
 
very inefficient in terms of
state usage.                                                                          
 But the major
advantage of a ring counter  
over a binary counter is that
it is self-decoding.  No extra
decoding circuit is needed to
determine what state the
counter is in.
 Shift Register Counters

 Johnson Counters


Johnson counters are a variation of standard ring counters, with the inverted
output of the last stage fed back to the input of the first stage.  They are also
known as twisted ring counters.  An n-stage Johnson counter yields a count
sequence of length 2n, so it may be considered to be a mod-2n counter.  The
circuit above shows a 4-bit Johnson counter.  The state sequence for the counter
is given in the table as well as the animation on the left.
Shift Register Counters

 Again, the apparent disadvantage of this

counter is that the maximum available
states are not fully utilized.  Only eight
of the sixteen states are being used.
 Beware that for both the Ring and the
Johnson counter must initially be forced
into a valid state in the count sequence
because they operate on a subset of the
available number of states.  Otherwise,
the ideal sequence will not be followed.