LECTURE 4

COB 2225
I/O ORGANIZATION
 I/0 ORGANIZATION

• In general, the rate of transfer from any input device to the processor, or from the
processor to any output device is likely to the slower than the speed of a processor.
– The difference in speed makes it necessary to create mechanisms to synchronize
the data transfer between them.
– Two mechanisms for synchronizing data transfers between the processor and
memory are the following:
Interrupts.
Direct Memory Access.
 INTERRUPTS

• In program-controlled I/O, when the processor continuously monitors the status of the
device, it does not perform any useful tasks.
• An alternate approach would be for the I/O device to alert the processor when it
becomes ready.
– Do so by sending a hardware signal called an interrupt to the processor.
– At least one of the bus control lines, called an interrupt-request line is dedicated
for this purpose.
• Processor can perform other useful tasks while it is waiting for the device to be ready.
 INTERRUPTS

Cont..

Interrupt
occurs i
here
i +1

M
 INTERRUPTS

• Processor is executing the instruction located at address i when an interrupt occurs.

• Routine executed in response to an interrupt request is called the interrupt-service
routine.
• When an interrupt occurs, control must be transferred to the interrupt service routine.
• But before transferring control, the current contents of the PC (i+1), must be saved in
a known location.
• This will enable the return-from-interrupt instruction to resume execution at i+1.
• Return address, or the contents of the PC are usually stored on the processor stack.
 INTERRUPTS

• Treatment of an interrupt-service routine is very similar to that of a subroutine.

• However there are significant differences:
– A subroutine performs a task that is required by the calling program.
– Interrupt-service routine may not have anything in common with the program it interrupts.
– Interrupt-service routine and the program that it interrupts may belong to different users.
– As a result, before branching to the interrupt-service routine, not only the PC, but other information
such as condition code flags, and processor registers used by both the interrupted program and the
interrupt service routine must be stored.
– This will enable the interrupted program to resume execution upon return from interrupt service
routine.
 INTERRUPTS

• Saving and restoring information can be done automatically by the processor or explicitly by program
instructions.
• Saving and restoring registers involves memory transfers:
– Increases the total execution time.
– Increases the delay between the time an interrupt request is received, and the start of execution of the
interrupt-service routine. This delay is called interrupt latency.
• In order to reduce the interrupt latency, most processors save only the minimal amount of information:
– This minimal amount of information includes Program Counter and processor status registers.
• Any additional information that must be saved, must be saved explicitly by the program instructions at the
beginning of the interrupt service routine.
 INTERRUPTS

• When a processor receives an interrupt-request, it must branch to the interrupt

service routine.
• It must also inform the device that it has recognized the interrupt request.
• This can be accomplished in two ways:
– Some processors have an explicit interrupt-acknowledge control signal for
this purpose.
– In other cases, the data transfer that takes place between the device and the
processor can be used to inform the device.
 INTERRUPTS

• Interrupt-requests interrupt the execution of a program, and may alter the intended
sequence of events:
– Sometimes such alterations may be undesirable, and must not be allowed.
– For example, the processor may not want to be interrupted by the same device while
executing its interrupt-service routine.
• Processors generally provide the ability to enable and disable such interruptions as desired.
• One simple way is to provide machine instructions such as Interrupt-enable and Interrupt-
disable for this purpose.
 INTERRUPTS

• To avoid interruption by the same device during the execution of an interrupt

service routine:
– First instruction of an interrupt service routine can be Interrupt-disable.
– Last instruction of an interrupt service routine can be Interrupt-enable.
• Multiple I/O devices may be connected to the processor and the memory via a
bus. Some or all of these devices may be capable of generating interrupt requests.
– Each device operates independently, and hence no definite order can be
imposed on how the devices generate interrupt requests.
 INTERRUPTS

• How does the processor know which device has generated an interrupt?
• How does the processor know which interrupt service routine needs to be
executed?
• When the processor is executing an interrupt service routine for one device, can
other device interrupt the processor?
• If two interrupt-requests are received simultaneously, then how to break the
tie?
 INTERRUPTS

• Consider a simple arrangement where all devices send their interrupt-requests

over a single control line in the bus.
• When the processor receives an interrupt request over this control line, how
does it know which device is requesting an interrupt?
• This information is available in the status register of the device requesting an
interrupt:
– The status register of each device has an IRQ bit which it sets to 1 when it
requests an interrupt.
 INTERRUPTS

• Interrupt service routine can poll the I/O devices connected to the bus. The first device
with IRQ equal to 1 is the one that is serviced.
• Polling mechanism is easy, but time consuming to query the status bits of all the I/O
devices connected to the bus.
• The device requesting an interrupt may identify itself directly to the processor.
– Device can do so by sending a special code (4 to 8 bits) the processor over the bus.
– Code supplied by the device may represent a part of the starting address of the
interrupt-service routine.
 INTERRUPTS

– The remainder of the starting address is obtained by the processor based on other
information such as the range of memory addresses where interrupt service routines
are located.
• Usually the location pointed to by the interrupting device is used to store the starting
address of the interrupt-service routine.
• Multiple I/O devices may be connected to the processor and the memory via a bus. Some
or all of these devices may be capable of generating interrupt requests.
– Each device operates independently, and hence no definite order can be imposed on
how the devices generate interrupt requests?
 INTERRUPTS

• How does the processor know which device has generated an interrupt?
• How does the processor know which interrupt service routine needs to be
executed?
• When the processor is executing an interrupt service routine for one device, can
other device interrupt the processor?
• If two interrupt-requests are received simultaneously, then how to break the
tie?
 INTERRUPTS

• Consider a simple arrangement where all devices send their interrupt-requests

over a single control line in the bus.
• When the processor receives an interrupt request over this control line, how
does it know which device is requesting an interrupt?
• This information is available in the status register of the device requesting an
interrupt:
– The status register of each device has an IRQ bit which it sets to 1 when it
requests an interrupt.
 INTERRUPTS

• Interrupt service routine can poll the I/O devices connected to the bus. The first device
with IRQ equal to 1 is the one that is serviced.
• Polling mechanism is easy, but time consuming to query the status bits of all the I/O
devices connected to the bus.
• The device requesting an interrupt may identify itself directly to the processor.
– Device can do so by sending a special code (4 to 8 bits) the processor over the bus.
– Code supplied by the device may represent a part of the starting address of the
interrupt-service routine.
 INTERRUPTS

– The remainder of the starting address is obtained by the processor based on

other information such as the range of memory addresses where interrupt
service routines are located.
• Usually the location pointed to by the interrupting device is used to store the
starting address of the interrupt-service routine.
• Previously, before the processor started executing the interrupt service routine
for a device, it disabled the interrupts from the device.
 INTERRUPTS

• In general, same arrangement is used when multiple devices can send interrupt requests to
the processor.
– During the execution of an interrupt service routine of device, the processor does not
accept interrupt requests from any other device.
– Since the interrupt service routines are usually short, the delay that this causes is
generally acceptable.
• However, for certain devices this delay may not be acceptable.
– Which devices can be allowed to interrupt a processor when it is executing an interrupt
service routine of another device?
 INTERRUPTS

• I/O devices are organized in a priority structure:

– An interrupt request from a high-priority device is accepted while the
processor is executing the interrupt service routine of a low priority device.
• A priority level is assigned to a processor that can be changed under program
control.
– Priority level of a processor is the priority of the program that is currently
being executed.
 INTERRUPTS

– When the processor starts executing the interrupt service routine of a device, its
priority is raised to that of the device.
– If the device sending an interrupt request has a higher priority than the processor, the
processor accepts the interrupt request.
• Processor’s priority is encoded in a few bits of the processor status register.
– Priority can be changed by instructions that write into the processor status register.
– Usually, these are privileged instructions, or instructions that can be executed only in
the supervisor mode.
 INTERRUPTS

– Privileged instructions cannot be executed in the user mode.

– Prevents a user program from accidentally or intentionally changing the
priority of the processor.
• If there is an attempt to execute a privileged instruction in the user mode, it
causes a special type of interrupt called as privilege exception.
 INTERRUPTS

INTR 1 I NTR p

Processor
Device 1 Device 2 Device p

INTA1 INTA p

• Each device has aPriority arbitration

separate interrupt-request and interrupt-acknowledge line.
• Each interrupt-request line is assigned a different priority level.
• Interrupt requests received over these lines are sent to a priority arbitration circuit in the processor.
• If the interrupt request has a higher priority level than the priority of the processor, then the
request is accepted.
 INTERRUPTS

• Which interrupt request does the processor accept if it receives interrupt requests from two or
more devices simultaneously?.
• If the I/O devices are organized in a priority structure, the processor accepts the interrupt
request from a device with higher priority.
– Each device has its own interrupt request and interrupt acknowledge line.
– A different priority level is assigned to the interrupt request line of each device.
• However, if the devices share an interrupt request line, then how does the processor decide
which interrupt request to accept?
 INTERRUPTS

Polling scheme:
• The processor uses a polling mechanism to poll the status registers of I/O
devices to determine which device is requesting an interrupt.
• In this case the priority is determined by the order in which the devices are
polled.
• The first device with status bit set to 1 is the device whose interrupt request is
accepted.
 INTERRUPTS

Daisy chain scheme:

Processor I NTR

Device 1 Device 2 Device n

INTA

• Devices are connected to form a daisy chain.

• Devices share the interrupt-request line, and interrupt-acknowledge line is
connected to form a daisy chain.
• When devices raise an interrupt request, the interrupt-request line is activated.
 INTERRUPTS

• The processor in response activates interrupt-acknowledge.

• Received by device 1, if device 1 does not need service, it passes the signal to device 2.
• Device that is electrically closest to the processor has the highest priority.
• When I/O devices were organized into a priority structure, each device had its own
interrupt-request and interrupt-acknowledge line.
• When I/O devices were organized in a daisy chain fashion, the devices shared an
interrupt-request line, and the interrupt-acknowledge propagated through the
devices.
• A combination of priority structure and daisy chain scheme can also used.
 INTERRUPTS
I NTR1

Device Device
INTA1

Processor
INTR p

Device Device
INTAp
Priority arbitration
circuit

• Devices are organized into groups.

• Each group is assigned a different priority level.
• All the devices within a single group share an interrupt-request line, and are
connected to form a daisy chain.
 INTERRUPTS

• Only those devices that are being used in a program should be allowed to generate interrupt
requests.
• To control which devices are allowed to generate interrupt requests, the interface circuit of each I/O
device has an interrupt-enable bit.
– If the interrupt-enable bit in the device interface is set to 1, then the device is allowed to generate
an interrupt-request.
• Interrupt-enable bit in the device’s interface circuit determines whether the device is allowed to
generate an interrupt request.
• Interrupt-enable bit in the processor status register or the priority structure of the interrupts
determines whether a given interrupt will be accepted.
 EXCEPTIONS

• Interrupts caused by interrupt-requests sent by I/O devices.

• Interrupts could be used in many other situations where the execution of one program needs to be
suspended and execution of another program needs to be started.
• In general, the term exception is used to refer to any event that causes an interruption.
– Interrupt-requests from I/O devices is one type of an exception.
• Other types of exceptions are:
– Recovery from errors
– Debugging
– Privilege exception
 EXCEPTIONS

• Many sources of errors in a processor. For example:

– Error in the data stored.
– Error during the execution of an instruction.
• When such errors are detected, exception processing is initiated.
– Processor takes the same steps as in the case of I/O interrupt-request.
– It suspends the execution of the current program, and starts executing an
exception-service routine.
 EXCEPTIONS

• Difference between handling I/O interrupt-request and handling exceptions due

to errors:
– In case of I/O interrupt-request, the processor usually completes the
execution of an instruction in progress before branching to the interrupt-
service routine.
– In case of exception processing however, the execution of an instruction in
progress usually cannot be completed.
 EXCEPTIONS

• Debugger uses exceptions to provide important features:

– Trace,
– Breakpoints.
• Trace mode:
– Exception occurs after the execution of every instruction.
– Debugging program is used as the exception-service routine.
• Breakpoints:
– Exception occurs only at specific points selected by the user.
– Debugging program is used as the exception-service routine.
 EXCEPTIONS

• Certain instructions can be executed only when the processor is in the

supervisor mode. These are called privileged instructions.
• If an attempt is made to execute a privileged instruction in the user mode, a
privilege exception occurs.
• Privilege exception causes:
– Processor to switch to the supervisor mode,
– Execution of an appropriate exception-servicing routine.