ECE 027

FUNDAMENTALS OF
ELECTRONIC CIRCUITS

Module 5 – Field Effect

Transistor

Engr. Raymart Aurora

Grading System and Scheme
Final Grade (FG)
The Final Grade (FG) will be computed as follows:

FG = {FCS (0.5) + FE (0.5)}2/3 + 1/3(MG)

FCS = Final Class standing
FE = Final Exam

Final Exam will be the third and last major Exam for this course.
This is usually a departmental exam and the coverage of Final E
will be Modules 1 - 6.
b. Final Class Standing will be based on the following:
Discussion - 5%
Homework -10%
Quizzes -25%
Simulation experiments and reports - 10%
Group Project - 50%
Week 5 Schedule
9/22/2020 – Introduction of Field Effect
Transistor (Part 1)
9/24/2020 – Introduction of Field Effect
Transistor (Part 2)
9/26/2020 – Operational Amplifiers and
Their Characteristics
Week 6 Schedule
9/29/2020 – Introduction of Digital
Electronics and Logic Circuits
10/1/2020 – Group Project submission and
presentation
10/3/2020 – Final Exam
Group Project
The objective of this group project is to apply
all the knowledge about basic electronics and
skills acquired from the simulation activities
in Multisim.
Group Project
1. Each group must be able to produce an
electronic project which utilizes diodes,
transistors, op-amps or IC’s. Example
projects are water level alarm, fire level
alarm, lie detector etc., as long as you are
able to utilize semiconductor devices.
Group Project
2. Due to the pandemic, this electronic
projects will be purely simulation. Each
group must be able to demonstrate that the
submitted circuit is operating via simulation.
3. The circuits must utilize actual part
numbers available in the Multisim Parts
Library.
Group Project
4. The class will be divided in 9 groups, each
group should have 5 members. You can
choose the members in your group.
Nominate also the group leader for each
group.
5. This will be due in the finals. In the project
demonstration, each group will be given 10
minutes for the presentation and simulation
demonstration.
Group Project
6. In addition, each group is expected to
submit the project documentation, project
powerpoint presentation and the simulation
file.
7. The level of difficulty and how interesting
it is affect your grade as well.
Group Project
9. In the project documentation, include the following :
a. Project Title and members
b. Table of contents
c. Introduction (discuss about the project, why choose
the project, objectives of the project)
d. Methodology (Design) - Include the circuitry.
e. Simulation results and interpretation - Include image
results and waveforms if applicable. 
f. Conclusion
g. Annexes (if applicable)
h. Reference
Group Project

Deadline for submission of the project

simulation file, presentation and
documentation will be on October 3, 2020
Introduction
The field effect transistor (FET) is a three-terminal device
similar to the bipolar junction transistor. Just as there are
NPN and PNP bipolar transistors, there are N-channel and P-
channel field effect transistors. However, it is important to
keep in mind that the BJT transistor is a bipolar device—the
prefix bi indicates that the conduction level is a function of
two charge carriers, electrons and holes. The FET is a
unipolar device depending solely on either electron (n -
channel) or hole (p -channel) conduction.

There are basically two types of FETs: the junction field

effect transistor, abbreviated JFET, and the metal-oxide-
semiconductor field effect transistor, abbreviated MOSFET.
Introduction
The term field effect in the name deserves some explanation.
Electric field is established by the charges present, which
controls the conduction path of the output circuit without the
need for direct contact between the controlling and
controlled quantities.
Introduction
Unlike bipolar transistors, which are current-controlled devices, FETs
are voltage-controlled devices, i.e., an input voltage controls an output
current. In other words, the current Ic is a direct function of the level of
Ib. For the FET the current Id will be a function of the voltage VGS
applied to the input circuit. In each case the current of the output circuit
is controlled by a parameter of the input circuit—in one case a current
level and in the other an applied voltage.
FET vs BJT
1. The input impedance is extremely high (of the order of
megohms) for FETs and therefore they require very little
power from the driving source. Their high input
impedance is one reason that FETs are sometimes
preferred over bipolar transistors.
2. Typical ac voltage gains for BJT amplifiers are a great
deal more than for FETs.
3. FETs are more temperature stable than BJTs, and FETs
are usually smaller than BJTs, making them particularly
useful in integrated-circuit (IC) chips.
Junction FET
The first FET that we will discuss is the Junction Field Effect
Transistor or JFET. There are two types of JFET : N – type and
P – type JFET. There schematic symbol are shown below.
JFETs and Their Characteristics
The construction of N - channel JFET or the Junction Field
Effect Transistor is shown below. Note that the major part of
the structure is the n -type material which forms the channel
between the embedded layers of p -type material. (That is why
it is called as N – Channel)
JFETs and Their Characteristics
There are three terminals for JFET; DRAIN (D), SOURCE (S)
and GATE (G). In essence, the drain and the source are
connected to the ends of the N -type channel and the gate to the
two layers of P -type material. The current flow is between the
drain and source terminals in a JFET. For the N -channel JFET
the majority current carriers in the channel are free electrons.
Conversely, for the P - channel JFET the majority current
carriers in the channel are holes.
JFETs and Their Characteristics
In the absence of any applied potentials the JFET has two p –
n junctions under no-bias conditions. The result is a depletion
region at each junction, that resembles the same region of a
diode under no-bias conditions. Recall also that a depletion
region is void of free carriers and is therefore unable to
support conduction.
JFET Operation (for N Channel)
VGS = 0 V, VDS Some Positive
Value
- n - channel JFET with both gates
shorted to the source.
- This results in zero gate current
- The drain supply voltage, VDD ,
reverse-biases both p-n junctions.
- It is important to note that the
depletion region is wider near the
top of both p –type materials.
JFET Operation (for N Channel)
VGS = 0 V, VDS Some Positive Value
- The instant the voltage VDD (=VDS) is
applied, the electrons are drawn to the
drain terminal, establishing the
conventional current Id with the defined
direction.
- The path of charge flow clearly reveals
that the drain and source currents are
equivalent (Id = Is).
- Under this conditions, the flow of charge is
relatively uninhibited and is limited solely
by the resistance of the n -channel between
drain and source.
JFET Operation (for N Channel)
Drain Curves/Output Characteristics Curve
- As the voltage Vds is increased from 0V to a few volts, the current will
increase as determined by Ohm’s law and the plot of Id versus Vds will
appear as shown. The relative straightness of the plot reveals that for the
region of low values of Vds, the resistance is essentially constant.
JFET Operation – (for N Channel)
Drain Curves/Output Characteristics Curve
- When Vds then reaches the level of Vp, the saturation level of drain
current will be achieved.
- Vp or Pinch off voltage is the minimum voltage required across drain to
source to achieve Idss or drain – source saturation current.
- Take note that Vp here is the Vp (when Vgs = 0V)
JFET Operation – (for N Channel)
Example
- What is the Vp (for Vgs = 0V)?
JFET Operation (for N Channel)
Pinch Off Voltage

- If Vds is increased to a level where it

appears that the two depletion regions
would “touch” or pinch-off will
result. The level of Vds that
establishes this condition is referred to
as the pinch-off voltage and is denoted
by Vp. In actuality, the term pinch-off
is a misnomer in that it suggests the
current Ip is pinched off and drops to
0A. However, this is hardly the case—
Id maintains a saturation level defined
as Idss.
JFET Operation (for N Channel)
Vgs < 0V

- The voltage from gate to source, denoted Vgs, is the controlling voltage
of the JFET. Just as various curves for Ic versus Vce were established for
different levels of Ib for the BJT transistor, curves of Id versus Vds for
various levels of Vgs can be developed for the JFET. For the n - channel
device the controlling voltage Vgs is made more and more negative from
its Vgs = 0 V level. In other words, the gate terminal will be set at lower
and lower potential levels as compared to the source.
JFET Operation (for N Channel)
Vgs < 0V

- A negative voltage of - 1V is
applied between the gate and
source terminals for a low level
of Vds. The effect of the
applied negative-bias Vgs is to
establish depletion regions
similar to those obtained with
Vgs = 0 V, but at lower levels
of Vds.
JFET Operation
Vgs < 0V
- Thus, result of applying a negative bias to the gate is to reach the
saturation level at a lower level of Vds, for VGS = - 1V. The resulting
saturation level for Id has been reduced and in fact will continue to decrease
as Vgs is made more and more negative. Also take note that for each Vgs
has corresponding pinch – off values as determine in the locus of points as
seen in the graph.
JFET Operation
Vgs < 0V
- Note also how the pinch-off voltage continues to drop in a parabolic
manner as VGS becomes more and more negative. Eventually, when
applied Vgs = -Vp (for Vgs = 0V) will be sufficiently negative to
establish a saturation level that is essentially 0 mA, and for all practical
purposes the device has been “turned off.” We call then this one as
Vgs(off).
Vgs(off) = -Vp (for Vgs = 0V)
JFET Operation
Vgs < 0V
Example
What is then our Vgs(off)?
JFET Operation
Vgs < 0V
In summary:
The level of Vgs that results in Id = 0 mA is defined as Vgs(off)= Vp (for
Vgs = 0V), with Vp being a negative voltage for n-channel devices and a
positive voltage for p-channel JFETs.
JFET Operation
Drain Curves
Notice that as Vgs becomes increasingly more negative, the drain current,
Id, is reduced.
JFET Operation
Drain Curves
There are two other important points to be brought out. The first
is that the slope of each separate drain curve in the ohmic region
decreases as Vgs becomes more negative. This occurs because the
channel resistance, rDS, increases as V GS becomes more negative. This
useful feature allows using JFETs as voltage variable resistances.
JFET Operation
Drain Curves
The second important feature is that the drain-source voltage Vds, at
which pinch-off occurs, decreases as Vgs becomes more negative.
Technically, the pinch-off value of Vds can be specified for any value of
Vgs. This is expressed in:

where Vp is the pinch-off voltage for Vgs = 0 V and Vds(p) is the pinch-
off voltage for any value of applied Vgs.

Thus, Vp here is constant. Vgs is the applied gate –source voltage. And
Vds(p) is the corresponding pinch – off voltage for the applied Vgs.

Note that Vgs here will be in absolute value.

JFET Operation
Drain Curves
Example.
If Vp = 4V, and Vgs applied is -2V, what is the Vds(p) for the applied
Vgs.

Vds (p) = 4V - | -2V |

Vds (p) = 2V
JFET TRANSFER CHARACTERISTICS

For the BJT transistor the output current Ic and the input controlling
current Ib are related by beta, which was considered constant for the
analysis to be performed. In equation form,
JFET TRANSFER CHARACTERISTICS

Unfortunately, this linear relationship does not exist between the output
and input quantities of a JFET. The relationship between Id and Vgs is
defined by Shockley’s equation. In general, The transfer characteristics
defined by Shockley’s equation are unaffected by the network in which
the device is employed.

OR

Thus Vp here is the the pinch off voltage for Vgs = 0V. And as we know
in the previous slides, Vgs(off) = Vp
JFET TRANSFER CHARACTERISTICS

In review:
JFET TRANSFER CHARACTERISTICS

In review:
JFET TRANSFER CHARACTERISTICS

In review:
JFET Transconductance Curve
This curve is called a transconductance curve. Notice that the graph is not
linear because equal changes in Vgs do not produce equal changes in Id.
JFET Biasing Techniques

Many techniques can be used to bias JFETs. In all cases, however, the
gate-source junction is reverse-biased. The most common biasing
techniques are covered in this section including gate bias, self-bias and
voltage divider bias.
JFET Biasing Techniques

Gate Bias

The negative gate voltage is applied

through a gate resistor, Rg. Rg can be
any value, but it is usually 100 kohms or
larger. Since there is zero current in the
gate lead of the JFET, the voltage drop
across Rg is zero. The main purpose of
Rg is to isolate the gate from ground for
ac signals.
JFET Biasing Techniques

Gate Bias

When Vgs is known, the value of the

drain current is calculated using
Shockley’s Equation. Then Vds is
calculated as
JFET Biasing Techniques

Gate Bias

Sample problem: For the range of JFET

parameters shown, calculate the
minimum and maximum values for Id
and Vds if Vgs = -1.5 V.
JFET Biasing Techniques
Gate Bias
Sample problem: For the range of JFET
parameters shown, calculate the
minimum and maximum values for Id
and Vds if Vgs = -1.5 V.

Sol.:
JFET Biasing Techniques
Self-Bias
One of the most common ways to bias a
JFET is with self-bias. Notice that only a
single power supply is used, the drain
supply voltage, Vdd. In this case, the
voltage across the source resistor, Rs,
provides the gate-to-source bias voltage.
JFET Biasing Techniques
Self-Bias
When power is first applied, drain
current flows and produces a voltage
drop across the source resistor, Rs. For
the direction of drain current shown, the
source is positive with respect to ground.
Because there is no gate current, Vg = 0
V. Therefore Vgs is calculated as
JFET Biasing Techniques
Self-Bias
When power is first applied, drain
current flows and produces a voltage
drop across the source resistor, Rs. For
the direction of drain current shown, the
source is positive with respect to ground.
Because there is no gate current, Vg = 0
V. Therefore Vgs is calculated as
JFET Biasing Techniques
Self-Bias Calculations
The source resistor, Rs, must be carefully
selected for any JFET circuit with self
bias. A convenient formula for
determining the source resistor, Rs:
JFET Biasing Techniques

Voltage Divider Bias

Since the gate-source junction has
extremely high resistance (several
hundred megohms), the R1 - R2
voltage divider is practically
unloaded. Therefore, the gate
voltage, Vg, is calculated as
JFET Biasing Techniques
Voltage Divider Bias
JFET Biasing Techniques
Voltage Divider Bias
JFET Biasing Techniques
Voltage Divider Bias
JFET Amplifier
JFETs are commonly used to amplify small ac signals. One reason for
using a JFET instead of a bipolar transistor is that a very high input
impedance, Zin , can be obtained. A big disadvantage, however, is that
the voltage gain, Av, obtainable with a JFET is much smaller.

Before examining the basic JFET amplifier configurations, let’s

analyze again the JFET’s transconductance curve.
JFET Amplifier
The transconductance curve reveals that equal changes in Vgs do not
produce equal changes in Id . On higher part of the transconductance
curve, notice that Id is more sensitive to changes in Vgs.
Mathematically, transconductance, gm, is defined as follows:

where ΔID = change in drain

current, and ΔVGS = change in
gate-source voltage.
JFET Amplifier
To prove that gm varies along the transconductance curve and the
sensitivity of Id as discussed in the previous slide:
JFET Amplifier
Notice how the transconductance, gm , increases with the height of the
transconductance curve. The value of gm can be calculated for any
value of VGS.
JFET Amplifier
Example: Calculate gm for Vgs = -1V, -2V, -3V and -4V
JFET Common-Source (CS) Amplifier
JFET Common-Source (CS) Amplifier
DC Analysis

The resistor, RS , provides self bias. Since VGS(off) = - 4V and IDSS = 10

mA, the RS value of 200 ohms. This sets the Q point so that the drain
current ID equals approximately one-half of IDSS.
JFET Common-Source (CS) Amplifier
DC Analysis
When Vs and Rs are known, the drain current, ID , can be calculated.
JFET Common-Source (CS) Amplifier
AC Analysis
JFET Common-Source (CS) Amplifier
AC Analysis
Notice that the drain circuit acts like a constant current source with a value
equal to gm * vgs , where vgs is the ac voltage across the gate-source junction.
Because VDD is at ac ground, RD and RL are in parallel for ac signals. The
voltage gain, AV, is calculated as follows:
JFET Common-Source (CS) Amplifier
Example:
calculate the voltage gain, AV , and the output voltage, Vout .
JFET Common-Source (CS) Amplifier
Example:
Metal-Oxide-Semiconductor FET
The second type of FET that we will discuss is Metal-Oxide-
Semiconductor Field effect transistor or MOSFET has a gate,
source, and drain just like the JFET. Like a JFET, the drain
current in a MOSFET is controlled by the gate source voltage
VGS . There are two basic types of MOSFETs: the enhancement-
type and the depletion-type. The enhancement-type MOSFET is
usually referred to as an E-MOSFET, and the depletion-type
MOSFET is referred to as a D-MOSFET.
Metal-Oxide-Semiconductor FET
The key difference between JFETs and MOSFETs is that the
gate terminal in a MOSFET is insulated from the channel.
Because of this, MOSFETs are sometimes referred to as
insulated gate FETs or IGFETs. Because of the insulated gate,
the input impedance of a MOSFET is many times higher than
that of a JFET.
Metal-Oxide-Semiconductor FET
Depletion - type MOSFET (D- MOSFET)

The schematic symbol of D – MOSFET is shown below.

There are also two types of D MOSFET, N- channel and P –
channel

N- channel, D - MOSFET P- channel, D - MOSFET

Metal-Oxide-Semiconductor FET
Depletion - type MOSFET (D- MOSFET)

Shown also below is the construction of the two types of D -

MOSFET

N- channel, D - MOSFET P- channel, D - MOSFET

Metal-Oxide-Semiconductor FET
Depletion - type MOSFET (D- MOSFET)
To understand more about the D – MOSFET, let’s use the N channel
D MOSFET. You can see in the figure shown below, the drain terminal
is at the top of the n -material and the source terminal is at the bottom.
The n -type material forms the Channel, thus it is called N Channel. The
block of p -type material forms the Substrate into
which the n -type material is
embedded. Along the n -channel, a
thin layer of silicon dioxide (SiO2)
is deposited to isolate the gate from
the channel. From gate to channel
are the metal, silicon dioxide,
and n -type semiconductor materials,
in that order, which give the MOSFET its name.N- channel, D - MOSFET
Metal-Oxide-Semiconductor FET
Depletion - type MOSFET (D- MOSFET)
Looking at the schematic symbol again, we can see that the substrate
is connected to the source. This results in a three-terminal device. The
solid line connecting the source and drain terminals indicates that
depletion-type MOSFETs are “normally on ” devices, which means that
drain current flows when the gate-source voltage is zero.

N- channel, D - MOSFET
Metal-Oxide-Semiconductor FET
Zero Gate Voltage operation of D-MOSFET
A depletion-type MOSFET can operate with either positive or
negative gate voltages. As shown in the image below, the depletion-type
MOSFET also conducts with the gate shorted to the source for VGS = 0 V.
You can notice that VDD is connected between the drain and source with
the drain positive relative to the source
Metal-Oxide-Semiconductor FET
Zero Gate Voltage operation of D-MOSFET
Notice also that the substrate is connected to the source. With the
gate shorted to the source, drain current, ID , will flow in the n -type
channel. Because the p -type substrate is grounded, the - n -channel and p
–type substrate are always reverse-biased; this results in zero current in
the substrate. Also note that zero gate current flows because
of the extremely high resistance
of the SiO 2 insulating layer.
The resistance between the gate
and channel is of the order of
several thousands of megohms.
Metal-Oxide-Semiconductor FET
Drain current curves of D-MOSFET
A depletion-type MOSFET is similar to a JFET in its operating
characteristics, as shown in the figure below. Notice that for each drain
curve, the drain current increases linearly until the pinch-off voltage, V P ,
is reached. When V GS is negative, pinch-off occurs sooner (lower values
of V DS ), and when V GS is made positive, pinch-off occurs later. Notice
also that the maximum drain current ID does not exist when VGS = 0 V.
Yet IDSS is still defined the
same way: it is the drain
current with the gate
shorted.
Metal-Oxide-Semiconductor FET
Positive Gate Voltage operation of D-MOSFET
(Enhancement Mode)
Figure shown illustrates a positive gate voltage applied to the N –
channel depletion-type MOSFET. The positive gate voltage attracts free
electrons into the channel from the substrate, thereby
enhancing its conductivity
. When the gate is made
Positive relative to the
source, the depletion-type
MOSFET is said to be
operating in the
enhancement mode.
Metal-Oxide-Semiconductor FET
Negative Gate Voltage operation of D-MOSFET (Depletion
Mode)
Now, what if a negative voltage applied to the gate. The
negative gate voltage sets up an electric field that repels free
electrons from the channel. When the gate is made negative
relative to the source, the
depletion-type MOSFET is
said to be operating in
the depletion mode.
Making the gate negative
enough will reduce the
drain current, ID , to zero.
Metal-Oxide-Semiconductor FET
Transconductance curve of an n -channel depletion-type
MOSFET.
The curve shown is called the transconductance curve for the n
-channel depletion-type MOSFET. IDSS is the drain current that
flows with the gate shorted to the source. It is important to note,
however, that I DSS is not the maximum drain current that is
obtainable.
Metal-Oxide-Semiconductor FET
Transconductance curve of an n -channel depletion-type
MOSFET.
When VGS is positive, the depletion-type MOSFET operates in
the enhancement mode, and the drain current increases beyond
the value of I DSS . With V GS negative, the MOSFET operates
in the depletion mode.
Metal-Oxide-Semiconductor FET
Transconductance curve of an n -channel depletion-type
MOSFET.
If VGS is made negative enough, the drain current, I D , will be
reduced to zero. As with JFETs, the value of the gate-source
voltage that reduces the drain current to zero is called the gate
source cutoff voltage, designated V GS(off) .
Metal-Oxide-Semiconductor FET
D MOSFET as “NORMALLY ON”
One more point: because there is drain current with zero gate-
source voltage, the device is referred to as a “normally on”
MOSFET.
Because D-MOSFETS are normally on devices, the drain
current, I D , can be calculated using the formula :
Metal-Oxide-Semiconductor FET
Sample calculation for D - MOSFET
Metal-Oxide-Semiconductor FET
p -Channel Depletion-Type MOSFET
As shown in the previous slides, the channel is made up of p
-type semiconductor material for p -Channel Depletion-Type
MOSFET and the substrate is made of n -type semiconductor
material. Because of this, p -channel depletion-type MOSFET’s
require a negative drain voltage.
Metal-Oxide-Semiconductor FET
p -Channel Depletion-Type MOSFET
And now if we compare the transconductance curves of P –
Channel and N – channel (shown below is for P – Channel) we
can see that they are opposite. The p -channel depletion-type
MOSFET operates in the enhancement mode when V GS is
negative and in the depletion mode when V GS is positive. Note
that holes are the majority current carriers in the p -channel.
Metal-Oxide-Semiconductor FET
Enhancement-Type MOSFET
Shown below the construction of an n -channel enhancement-
type MOSFET. Notice that the p -type substrate makes contact
with the SiO2 insulator. Because of this, there is no channel for
conduction between the drain and source terminals.
Metal-Oxide-Semiconductor FET
Enhancement-Type MOSFET
Notice the polarities of the supply voltages. The drain and gate
are made positive with respect to the source. With V GS = 0 V,
there is no channel between the source and drain and so the
drain current, I D , is zero.
Metal-Oxide-Semiconductor FET
Enhancement-Type MOSFET
To produce drain current, the positive gate voltage must be
increased. This attracts electrons along the right edge of the
SiO2 insulator, The minimum gate-source voltage that makes
drain current flow is called the threshold voltage , designated V
GS(th) . When the gate voltage is less than V GS(th) , the drain
current, I D , is zero. The value of V GS(th) varies from one E-
MOSFET to the next.
Metal-Oxide-Semiconductor FET
Enhancement-Type MOSFET (E – MOSFET)
The schematic symbol of E – MOSFET is shown below. There are
also two types of E MOSFET, N- channel and P – channel. The
broken line represents the “off” condition that exists with zero gate
voltage. Because of this characteristic, enhancement-type MOSFETs
are called “normally off ” devices.

N- channel, E - MOSFET P- channel, E - MOSFET

Metal-Oxide-Semiconductor FET
Drain Curves of E - MOSFET
The curves shown is a typical set of drain curves for the n –
channel enhancement-type MOSFET. The lowest curve is the VGS(th)
curve. For more positive gate voltages, the drain current, ID ,
increases.
Metal-Oxide-Semiconductor FET
Transconductance Curve of E - MOSFET
The transconductance curve is shown below. Notice that ID is zero
when the gate-source voltage is less than VGS(th) .
Metal-Oxide-Semiconductor FET
P –channel E - MOSFET
As shown earlier, p -channel enhancement-type MOSFET.
Notice the arrow pointing outward away from the p -type channel.
Also, notice the negative gate and drain voltages. These are the
required polarities for biasing the p –channel enhancement-type
MOSFET.
Metal-Oxide-Semiconductor FET
MOSFET Biasing Techniques
There are many ways to bias
MOSFET’s . As an example, shown
below is a popular biasing technique
fo E – MOSFET. This form of bias is
called drain-feedback bias.
Metal-Oxide-Semiconductor FET
MOSFET Biasing Techniques
The manufacturer’s data sheet for enhancement-type MOSFETs
usually specifies the value of VGS(th) and the coordinates of one
point on the transconductance curve. The quantities I D(on) , V GS(on) ,
and V GS(th) are the parameters that are important when biasing E-
MOSFETs.
Metal-Oxide-Semiconductor FET
MOSFET Biasing Techniques
The transconductance curve, as an example a Motorola 3N169
enhancement-type MOSFET. The values shown for I D(on) , V GS(on) ,
and V GS(th) are “ typical” values.
Metal-Oxide-Semiconductor FET
MOSFET Biasing Techniques
The drain resistor, RD , must be
properly selected to provide the
required bias. RD can be calculated
using the formula :

Note : Since the gate current is zero,

no voltage is dropped across the gate
resistor, RG .
Therefore, V GS = V DS .
Metal-Oxide-Semiconductor FET
MOSFET Biasing Techniques
Example for biasing E MOSFET
Calculate the value of RD to provide an ID(on) of 10 mA.

Solution :
Metal-Oxide-Semiconductor FET
Handling MOSFETs

One disadvantage of MOSFET devices is their extreme

sensitivity to electrostatic discharge (ESD) due to their insulated
gate-source regions. The SiO2 insulating layer is extremely thin and
can be easily punctured by an electrostatic discharge.
Metal-Oxide-Semiconductor FET
Handling MOSFETs
Because MOSFETs can be easily damaged from electrostatic discharge,
extreme caution is recommended when handling them. The following is
a list of precautions:
1. Never insert or remove MOSFETs from a circuit with the power on .
2. Never apply input signals when the dc power supply is off .
3. Wear a grounding strap on your wrist when handling MOSFET
devices. This keeps the body at ground potential by bleeding off any
buildup of static electric charge.
4. When storing MOSFETs, keep the device leads in contact with
conductive foam, or connect a shorting ring around the leads.

Note: It is extremely important to observe these precautions to avoid

possible damage to the MOSFET device.
Metal-Oxide-Semiconductor FET
Handling MOSFETs
Many manufacturers put protective zener diodes across the gate-source region to
protect against ESD. The diodes are arranged so that they will conduct for either
polarity of gate-source voltage, V GS . The breakdown voltage of the diodes is
much higher than any voltage normally applied between the
gate source region but less
than the breakdown voltage of
the insulating material.
One drawback of using the
protective diodes is that the
input impedance of the device
is lowered considerably.
References:
Boylestad, Robert L., and Louis Nashelsky. 1978. Electronic devices and
circuit theory. Englewood Cliffs, N.J.: Prentice-Hall.
http://hyperphysics.phy-astr.gsu.edu/hbase/Solids/pnjun.html

Schultz, M. 1978. 2011. GROB’S BASIC ELECTRONICS.

END

ECE 027 FUNDAMENTALS OF ELECTRONIC CIRCUITS –

Module 5 Field Effect Transistors