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Interconnection Networks in Computer Architecture

The document discusses interconnection networks in computer architecture. It defines an interconnection network as a programmable system that transports data between terminals over shared physical channels. The key goals of interconnection network design are high throughput and low latency to avoid bottlenecking the system. Interconnection networks are classified into four domains based on the type and proximity of connected devices: on-chip networks (OCNs), system/storage area networks (SANs), local area networks (LANs), and wide area networks (WANs). On-chip networks connect devices on multicore/MPSoC chips and are the most tightly coupled with the shortest link delays.

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188 views19 pages

Interconnection Networks in Computer Architecture

The document discusses interconnection networks in computer architecture. It defines an interconnection network as a programmable system that transports data between terminals over shared physical channels. The key goals of interconnection network design are high throughput and low latency to avoid bottlenecking the system. Interconnection networks are classified into four domains based on the type and proximity of connected devices: on-chip networks (OCNs), system/storage area networks (SANs), local area networks (LANs), and wide area networks (WANs). On-chip networks connect devices on multicore/MPSoC chips and are the most tightly coupled with the shortest link delays.

Uploaded by

nishant rana
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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INTERCONNECTION NETWORKS

IN COMPUTER ARCHITECTURE

INTRODUCTION
What is an Interconnection Network?

 Network within a system


 Not the Internet: network between systems
Why Interconnection Networks Matter ?
What is an Interconnection Network?

 Interconnection Networks connect processors and


memory elements within and across computers
What is an Interconnection Network?

 Application: Ideally wants low-latency, high bandwidth,


dedicated channels between processors and memory
 Technology: Dedicated channels too expensive in terms
of area and power
What is an Interconnection Network?

 Interconnection Network: A programmable system


that transports data between terminals over a set of
shared physical channels
Interconnection Networks
 Key Design Principles
 Transfer maximum amount of information (high
throughput) within the least amount of time (low
latency) so as to not bottleneck the system

 Efficiently utilize shared but scarce resources


(buffers, links, logic) to reduce area and power
Types of Interconnection Networks (INs)

 Interconnection Networks can be grouped into four


domains:
 Depending on the type and proximity of devices to be
connected
1. On-Chip Networks (OCNs or NoCs)
2. System/Storage Area Networks (SANs)
3. Local Area Networks (LANs)
4. Wide Area Networks (WANs)
Local Area Network (LAN)

 Networks between autonomous computer systems


 Example: Machine room or throughout a building or campus
 “Clusters”
 Hundreds of devices
 thousands with bridging
 Loosely coupled with raw interconnects (e.g., Ethernet)
 Proximity: few kilometers
 Delay: micro seconds
Wide Area Network (WAN)

 Networks between LANs and autonomous computer


systems distributed across the world
 Millions of devices
 Loosely coupled with electrical and optical
Interconnects
 Proximity: many thousands of kilometers
 Delay: milli seconds
 Largest WAN is the Internet
System/Storage area Network (SAN)

 Multi-processor and multi-computer Networks


 Inter-processor and processor-memory interactions
 Server and Datacenter Networks
 Storage and I/O components
 Hundreds to thousands of devices interconnected
 IBM Blue Gene/L Supercomputer (64K nodes, each with 2 processors)
 Tightly-coupled with proprietary interconnects
 Proximity: tens of meters (typical) to a few hundred meters
 Link Delay: nano seconds
 Examples: Infiniiband, Myrinet, Quadrics, Advanced Switching Interconnect
On-Chip Network (OCN or NoC)

 Networks on multicore/MPSoC chips


 Devices include micro architectural functional units, register files,
processor/IP cores, caches, directories, memory controllers
 Current/Future Systems: tens to hundreds of devices
 Intel Single-Chip Cloud Computer – 48 Cores
 Tilera TILE64 – 64 Cores
 Tightly coupled with on-chip links
 Proximity: milli-meters
 Delay: pico seconds
Interconnection Network Domains
Why study NoCs now?
NoCs are Critical for Performance
Off-chip(SANs) vs. On-Chip
 Off-Chip Networks
 Bandwidth limited by chip pin-bandwidth
 Latency limited by long off-chip cables
 On-Chip Networks
 Very high on-chip bandwidth
 Abundant metal layers and wiring
 Much lower latency due to short wires
Off-chip vs. On-Chip
 The key concepts remain the same across SANs and
NoCs
 The constraints are different -> the design decisions are
different
 E.g., an off-chip topology may not be feasible on-chip due to
on-chip layout constraints
 Or an on-chip link circuit may not be feasible off-chip due to
technology constraints
 We will mostly focus on on-chip networks when
discussing concepts, but will periodically look at
implications in the off-chip (SAN/datacenter) space
Topology
 It refers to the arrangement
of the nodes and channels
 A good topology exploits
the characteristics of the
available packaging
technology to meet the
Throughput and Latency
requirements of the
application at minimum cost
Topology
 Our Next Topic

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