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CH 10

The division algorithm uses signed magnitude representation. It repeatedly shifts and subtracts the divisor from the dividend to obtain the quotient and remainder. The sign of the quotient is the XOR of the dividend and divisor signs. The algorithm shifts the remainder left at each step, adds the divisor's complement if needed, and sets the quotient bit if there is a borrow out of the most significant bit. It repeats until the remainder is smaller than the divisor.

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0% found this document useful (0 votes)
61 views37 pages

CH 10

The division algorithm uses signed magnitude representation. It repeatedly shifts and subtracts the divisor from the dividend to obtain the quotient and remainder. The sign of the quotient is the XOR of the dividend and divisor signs. The algorithm shifts the remainder left at each step, adds the divisor's complement if needed, and sets the quotient bit if there is a borrow out of the most significant bit. It repeats until the remainder is smaller than the divisor.

Uploaded by

Ayush Uprety
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Computer Arithmetic

Chapter 10
Contents
• Introduction
• Addition and Subtraction
• Multiplication Algorithm
• Division Algorithm
Introduction
• Arithmetic Instruction :
– Manipulate data to produce results necessary for the
solution of computational problems
– Perform arithmetic calculations and involved in
processing data in computers
– Primitive operations : Addition, subtraction,
Multiplication and division
– Other operations are derived from primitive
operations using numerical analysis
– Arithmetic processor :
• Executes arithmetic operations and are part of processor
unit
Contd…
• Data types are assumed to be reside in processor
registers during the execution of an arithmetic
instruction is specified in the definition of
instruction.
• Fixed and floating point representation
• Fixed point numbers may represent integer or
fractional part
• Negative number may be signed-magnitude or
signed-complement representation
Signed Magnitude Number
• A sign-magnitude number Z Signed-
Number
can be represented as (As, Magnitude
A) where As is the sign of Z +3 0 11
and A is the magnitude of
Z. +2 0 10
• The leftmost position, As, is +1 0 01
the sign bit. +0 0 00
• The sign bit is either
positive = 0 or negative = 1 -0 1 00
-1 1 01
-2 1 10
-3 1 11
Algorithm: Signed Magnitude Addition and
subtraction
Eight Conditions for Signed-Magnitude Addition/Subtraction

SUBTRACT Magnitudes
ADD
Operation Magnitu
des A>B A<B A=B

(+A) + (+B) + (A + B)
(+A) + (-B) + (A – B ) - (B – A ) + (A – B )
(-A) + (+B) - (A – B ) + (B – A ) + (A – B )
(-A) + (-B) - ( A + B)
(+A) - (+B) + (A – B ) - (B – A ) + (A – B )
(+A) - (-B) + (A + B)
(-A) - (+B) - ( A + B)
(-A) - (-B) - (A – B ) + (B – A ) + (A – B )
Example
Example of adding two
magnitudes when the +3 0 011
result is the sign of both
operands:
+ +2 0 010
+5 0 101

-3 1 011
Example
Example ofof adding
adding two
two
magnitudes
magnitudes when
when the
the result
result is
is
+ +2 0 010
the
the sign
sign of
of the
the larger
larger -( +3
magnitude:
magnitude:
011
- +2) 010

- 1 1 001
Flowchart of Addition and Subtraction with Signed-Magnitude Data
Summary of Addition and Subtraction with Signed-Magnitude Data

• The signs use an exclusive OR gate where if the output


is 0, then the signs are the same.
• Hence, add the magnitudes of the same signed
numbers. If the sum is an overflow, then a carry is
stored in E where E = 1 and transferred to the flip-flop
AVF, add-overflow.
• Otherwise, the signs are opposite and subtraction is
initiated and stored in A.
• No overflow can occur with subtraction so the AVF is
cleared.
• If E = 1, then A > B.
• However, if A = 0, then A = B and the sign is made
positive.
• If E = 0, then A < B and sign for A is complemented.
Addition and Subtraction with Signed-Magnitude Data Hardware
Design

Bs B register
Mode
Control
AVF Complementer M

E Parallel Adder
Input
Output Carry
S
Carry
As A register Load
Sum
Addition and Subtraction : 2’s Complement
Addition and Subtraction Signed-2’s
Compement Data Hardware Design
Multiplication Algorithm
1. Multiplication Algorithm : Array
Multiplier
Example#1 : 2 * 2 Multiplier

Multiplicand
Multiplier
Example # 2: 2 * 3 Multiplier
What will be the final
b1 b0 value ?
Draw equivalent
a2a1 a0
circuit of this type ?
-----------------
4 bit by 3 bit array multiplier
Multiplication Algorithm: For signed magnitude Data
Hardware for multiply operation: SM
Example # 1

• Multiply (-20)10 by (-5)10 using Signed Magnitude


Representation.

sign of 20 : 1 (Qs ) weight of 20 : 10100 [ Multiplicand] B


sign to 5 : 1 (Bs ) weight of 5 : 101 [Multiplier] Q

Sign of As = QS  BS = 0
Sign of Qs = QS  BS = 0
SC = n -1 = 3
A = 00000 [ 5 0’s : Just look at B]
E=0
Example : contd…
Multiplicand B E A Q SC
=10100
Multiplier in Q 0 00000 101 11 (3)
Qn = 1; add B 10100
First Partial Product 10100
Shift Right EAQ 0 01010 010 10 (2)
Qn = 0, Shr EAQ 0 00101 001 01 (1)
Qn = 1 , add B 10100
Second Partial Product 11001

Shift Right EAQ 01100 100 00 (0)

Final Product in AQ = (100 )10


Example#2
• Multiply (-5)10 by (-20)10 using Signed Magnitude
Representation.
sign to 5 : 1 (Bs ) weight of 5 : 101 [Multiplicand] B
sign of 20 : 1 (Qs ) weight of 20 : 10100 [ Multiplier] Q

Sign of As = QS  BS = 0
Sign of Qs = QS  BS = 0
SC = n -1 = 5
A = 000 [ 3 0’s : Just look at B]
E=0
Multiplicand B =101 E A Q SC
Multiplier in Q 0 000 10100 101 (5)
Qn = 0; Shr EAQ 000 01010 100 (4)
Qn = 0; Shr EAQ 0 000 00101 011 (3)
Qn = 1; add B 101
0 101
Shr EAQ 010 10010 010 (2)
Qn = 0; Shr EAQ 0 001 01001 001 (1)
Qn=1 ; Add B 101
110
Shr EAQ 011 00100 000 (0)

Final Product in AQ = (100 )10


Booth’s Algorithm
For 2’s Complement Numbers
Example #1
• Multiply (-5)10 by (-20)10 using Booth’s
Algorithm
-5 : 1011 (BR)
-20: 101100 (QR)

SC = n = 6
A = 0000 [ 4 0’s : Just look at BR]
Qn Qn+1 BR = 1011 AC QR Qn+1 SC
BR’+1 = 0101
Initially 0000 101100 0 6
00 ASHR 0000 010110 0 5
00 ASHR 0000 001011 0 4
10 SUB BR 0101
0101
ASHR 0010 100101 1 3
11 ASHR 0001 010010 1 2
01 ADD BR 1011
1100
ASHR 1110 001001 0 1
10 SUB BR 0101
0011
ASHR 0001 100100 1 0

+100
Example # 2
• Multiply (-15) * (+12)
- 15 : 10001 (BR)
+ 12 : 01100 (QR)

SC = n = 5
A = 00000 [ 5 0’s : Just look at BR]
Qn Qn+1 BR = 10001 AC QR Qn+1 SC
BR’+1 = 01111
Initially 00000 01100 0 5
00 ASHR 00000 00110 0 4
00 ASHR 00000 00011 0 3
10 SUB BR 01111
01111
ASHR 00111 10001 1 2
11 ASHR 00011 11000 1 1
01 ADD BR 10001
10100
ASHR 11010 01100 0 0

-180
Hardware for Booth Algorithm
Division Algorithm
For Signed Magnitude Data
Example
• Divide (+448) by (+17)
• Dividend in AQ = 0111000000
• Divisor in B = 10001
B’+1 = 01111
• Sign of Quotient = As XOR Bs = 0
• Sign of Remainder = same as sign of dividend
• (+17) * (+26) + (+6) = (+448)
• (Divisor) * (Quotient) + (remainder) = Dividend
Divisor B=10001 B’+1 = 01111
Operation E A Q SC
Dividend 01110 00000 5
SHL EAQ 0 11100 00000
ADD B’+1 01111
1 01011
E=1
Set Qn=1 1 01011 00001 4
SHL EAQ 0 10110 00010
ADD B’+1 01111
E=1 1 00101
Set Qn=1 1 00101 00011 3
SHL EAQ 0 01010 00110
ADD B’+1 01111
E=0,Leave Qn=0 0 11001 00110
Operation E A Q SC
ADD B 10001
Restore Remainder 1 01010 2
SHL EAQ 0 10100 01100
ADD B’+1 01111
E=1 1 00011
Set Qn=1 1 00011 01101 1
SHL EAQ 0 00110 11010
ADD B’+1 01111
E=0, Leave Qn=0 0 10101 11010
ADD B 10001
Restore Remainder 1 00110 11010 0
Neglect E
Remainder in A 00110
Quotient in Q 11010
Example#2
• Divide (-90) by (+8)
• Dividend in AQ = 1011010
• Divisor in B = 1010
B’+1 = 1010
• Sign of Quotient = As XOR Bs = 1 (negative)
• Sign of Remainder = same as sign of dividend =
negative
• (+8) * (-11) + (-2) = (-90)
• (Divisor) * (Quotient) + (remainder) = Dividend
Divisor B=1000 B’+1 = 1000
Operation E A Q SC
Dividend 0101 1010 4
SHL EAQ 0 1011 0100
ADD B’+1 1000
1 0011
E=1, Set Qn=1 0101 3
SHL EAQ 0 0110 1010
ADD B’+1 1000
1110
E=0,Qn=0 1010
Restore 1000
1 0110 2
SHL EAQ 0 1101 0100
ADD B’+1 1000
Operation E A Q SC
1 0101
E=1, Set Qn=1 0101 1
SHL EAQ 0 1010 1010
ADD B’+1 1000
1 0010
E=1, Set Qn=1 1011 0
Remainder in A 0010
Quotient in Q 1011

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