Advanced RISC Machines

(ARM)

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 Contents

•ARM Introduction
• Registers
•ARM Instructions

•ARM Operating Modes

•Instruction Pipelining
•Exception and Interrupt Handling

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 ARM Introduction

Introduction :

• Founded 1990, owned by Acorn, Apple and VLSI

• First RISC microprocessor for commercial use

• Market-leader for low-power and cost-sensitive embedded

applications

• Problems with CISC:

•Sometimes Slower then memory parts
•Uneven Clock cycles per instruction

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 ARM Introduction
• The naming convention for ARM Revision Example core
processors are: ARMv1, v2 … v6.v7 implementation
ARMv1 ARM1
• Core implementation:
ARMv2 ARM2
– ARM1, ARM2, ARM7,
StrongARM, ARM926EJ, ARMv2a ARM3
ARM11, Cortex
ARMv3 ARM6 and ARM7DI

• ARM7 is based on ARMv4 ARMv3M ARM7M

ARMv4 StrongARM
• ARM11 is based on ARMv6 ARMv4T ARM7TDMI and ARM9T
ARMv5TE ARM9E and ARM10E
ARMv5TEJ ARM7EJ and ARM926EJ
ARMv6 ARM11

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 ARM Introduction
• Major Difference between Cores
– Processor Modes,
– Pipeline,
– Architecture ,
– Memory Protection Unit,
– Memory Management Unit,
– Cache,
– Hardware Accelerated Java
• Examples:
– ARM7TDMI
• MMU, MPU, cache, Java ( Not Supported)
• Thumb mode ( Supported)
– ARM922T
• MMU, No MPU, 8K+8K data and instruction cache, No Java,
Thumb mode

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 ARM Introduction
• Naming Conventions
• ARM [X][Y][Z][T][D][M][I][E][J][F][S] (e.g: ARM7TDMI)
– X-Family
– Y-Memory Management
– Z- Cache
– T- Thumb mode
– D- JTAG debugging
– M- Fast multiplier
– I- Embedded ICE Macrocell
– E- Enhanced instructions (implies TDMI)
– J- Jazelle, hardware acclerated Java
– F- Floating point
– S- Synthesizable version

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 ARM Introduction

• ARM core uses RISC architecture

– Reduced instruction set
– Load store architecture
– Large number of general purpose registers
– Parallel execution with pipelines

• But some differences from RISC

– Thumb mode
– DSP instructions
– Conditional execution instruction
– 32 bit barrel shifter

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 ARM Registers

Main Features of ARM Register

– Load and store architecture
– General purpose registers can hold data or
address
– Total of 32 registers each 32 bit wide
– There are 18 active registers
• 16 data registers
• 2 status registers

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ARM7TDMI Core Diagram

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 ARM Registers
User Mode
R0
• Registers R0 thru R15 are General Purpose R1
Registers R2
R3
R4
• R13 is used for Stack pointer (sp) R5
R6
R7
• R14 is used as the Link Register (lr) R8
R9
R10
• R15 is used as Program Counter (pc) R11
R12
R13 (sp)
• CPSR – Current program status register R14 (lr)
R15 (PC)

• SPSR – Stored program status register CPSR

SPSR

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 ARM Registers
• Program status registers
– CPSR is used to control and store CPU states
– CPSR is divided in four 8 bit fields
• Flags
• Status
• Extension
• Control

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 ARM Registers
• Program status register flags
– N:1 – Negative result
– Z:1 – Result is zero
– C:1 – Carry in addition operation
– C:0 – Borrow in subtraction operation
– V:1 – Overflow or underflow

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 ARM Registers

• Program status register flags

– I:1 – IRQ interrupts disabled
– F:1 – FIQ interrupts disabled
– T:0 – ARM mode
– T:1 – Thumb mode

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 ARM Registers
• Program status register control modes
– 0b10000 – User mode
– 0b10001 – FIQ mode
– 0b10010 – IRQ mode
– 0b10011 – Supervisor mode
– 0b10111 – Abort mode
– 0b11011 – Undefined mode
– 0b11111 – System mode

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 ARM Instructions
• When the processor is executing in
• ARM state:
– All instructions are 32 bits wide
– All instructions must be word aligned
– Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as
instruction cannot be halfword or byte aligned).
• Thumb state:
– All instructions are 16 bits wide
– All instructions must be halfword aligned
– Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as
instruction cannot be byte aligned).
Jazelle state:
– All instructions are 8 bits wide
– Processor performs a word access to read 4 instructions at once

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 ARM Thumb Instructions
• Compressed form of ARM
– Instructions stored as 16-bit,
– Decompressed into ARM instructions and
– Executed
• More traditional:
– No condition codes
– Two-address data processing instructions
• Access to R0 – R8 restricted to
– MOV, ADD, CMP
• Lower performance (ARM 40% faster)
• Higher density (THUMB saves 30% space)

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 ARM Thumb Instructions
• Thumb set register is a subset of ARM-state set.

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 ARM Operating Modes
• Processor modes are execution modes which determines active registers and
priveleges
• List of modes
– User mode
– Abort mode
– Fast interrupt mode
– Interrupt mode
– Supervisor mode exception modes
– System mode
– Undefined mode
• All except user mode are privileged modes
– Used mode is used for normal execution of programs and application
– Privileged mode allow full read/write to CPSR

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 ARM Operating Modes
• Of total 37 registers only 18 are active in a given register mode

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 Instruction Pipelining
• 3-stage pipeline: Fetch – Decode - Execute
• Three-cycle latency,
one instruction per cycle throughput
i
n
s
t i Fetch Decode Execute
r
u
i+1 Fetch Decode Execute
c
t
i i+2 Fetch Decode Execute
o cycle
n
t t+1 t+2 t+3 t+4

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 Instruction Pipelining
• Increases speed –
most instructions executed in single cycle
• Versions:
– 3-stage (ARM7TDMI and earlier)
– 5-stage (ARMS, ARM9TDMI)
– 6-stage (ARM10TDMI)

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 Exception and Interrupt Handling

• ARM Supports 7 Exception modes

• Developers can write custom exception handlers to deal with exceptions

conditions

• For example:
– Consider a system that crashes if PC is corrupted. This will cause
an exception. In corresponding exception handler, programmer can
save state of all registers to file system for debugging and reset.

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 Exception and Interrupt Handling

• ARM exceptions order of priority

– Reset
– Data abort
– FIQ
– IRQ
– Prefetch abort
– Undefined instruction
– Software interrupt

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 Exception and Interrupt Handling
Reset Exception :
• Highest priority exception
– The reset handler runs in a supervisor mode
– Handler is generally located at 0x00000000
– In Reset Handler, FIQ and IRQ are disabled
– Actions performed:
• R14_svc is set to unpredictable value
• SPSR_svc is set to unpredictable value
• CPSR [4:0] is 0b10011 – supervisor mode
• CPSR [5] is 0 – execute in ARM mode
• CPSR [6] is 1 – disable fast interrupts
• CPSR [7] is 1 – disable normal interrupts
• PC = 0x0000000

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 Exception and Interrupt Handling
Data Abort Exception:
Data abort exceptions mean software trying to read/write an illegal
memory location
• Abort handler is located at 0x00000010.
– Actions performed
• R14_abt =address of abort instruction + 8
• SPSR_svc = CPSR
• CPSR [4:0] is 0b10111 – abort mode
• CPSR [5] is 0 – execute in ARM mode
• CPSR [6] is 1 – unchanged
• CPSR [7] is 1 – disable normal interrupts
• PC = 0x0000010

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 Exception and Interrupt Handling
FIQ Interrupts:
FIQ mode exists if developer wants to handle certain interrupts faster
• Additional banked registers in FIQ mode makes execution faster
• Default ARM core do not handle nested interrupts
• FIQ handler is generally located at 0x0000001C
– Actions performed
• R14_fiq =address of next instruction to execute + 4
• SPSR_fiq = CPSR
• CPSR [4:0] is 0b10111 – FIQ mode
• CPSR [5] is 0 – execute in ARM mode
• CPSR [6] is 1 – disable fast interrupts
• CPSR [7] is 1 – disable normal interrupts
• PC = 0x0000001C

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 Exception and Interrupt Handling
Normal Interrupts (IRQ) :
• Normal interrupt is lower priority than fast interrupts
• Default ARM core do not handle nested interrupts
• IRQ handler is generally located at 0x00000018
– Actions performed
• R14_irq =address of next instruction to execute + 4
• SPSR_irq = CPSR
• CPSR [4:0] is 0b10010 – IRQ mode
• CPSR [5] is 0 – execute in ARM mode
• CPSR [6] is 1 – Unchanged
• CPSR [7] is 1 – disable normal interrupts
• PC = 0x00000018

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 Exception and Interrupt Handling
Prefetch Abort Exception:
• If processor reads instruction from undefined memory, it causes a
prefetch abort exception.
• Prefetch abort occurs when instruction reaches execution stage of
pipeline.
• Normal interrupts disabled.
• Prefetch handler is generally located at 0x0000000C
– Actions performed
• R14_abt =address of next instruction to execute + 4
• SPSR_irq = CPSR
• CPSR [4:0] is 0b10111 – Prefetch mode
• CPSR [5] is 0 – execute in ARM mode
• CPSR [6] is Unchanged
• CPSR [7] is 1 – disable normal interrupts
• PC = 0x0000000C
•

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 Exception and Interrupt Handling
Undefined Exception:
• When executing co processor instructions, ARM waits for
coprocessor to acknowledge that it can execute the instruction.
• If no coprocessor can handle given instruction, undefined instruction
expection is raised.
• Undefined instruction handler can parse instructions and process
them in a software saimulator
• Undefined instruction handler is generally located at 0x00000004
– Actions performed
• R14_und =address of next instruction to execute
• SPSR_irq = CPSR
• CPSR [4:0interrupts
• ] is 0b11011 – Undefined mode
• CPSR [5] is 0 – execute in ARM mode
• CPSR [6] is Unchanged
• CPSR [7] is 1 – disable normal PC = 0x00000004

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 Exception and Interrupt Handling
Software Interrupt :
• Software interrupt expection is used to enter supervisor mode to
execute a privileged OS function.
• Execution of any system call will cause SWI interrupt to change mode to
supervisor mode
• Software interrupt handler is generally located at 0x00000008.
– Actions performed
• R14_svc =address of next instruction to execute after SWI
• SPSR_irq = CPSR
• CPSR [4:0] is 0b10011 – Supervisor mode
• CPSR [5] is 0 – execute in ARM mode
• CPSR [6] is Unchanged
• CPSR [7] is 1 – disable normal interrupts
• PC = 0x00000008

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 Exception and Interrupt Handling
Examples:
1. Exception is raised
2. Lookup to exception table to find exception handler
3. Exception handler is executed
4. Return from the exception handler.

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LPC 2138 Block Diagram

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