Reduced Instruction

Set Computer &

Complex Instruction
Set Computer.
RISC and CISC

By: Sania Shahzad &

Farheen Masood

LOGO
LOGO Contents
a nd RISC
of CI S C
Histo r y
1
r ac t e r is tics
I SC & Cha
R
2
c t e r is t i cs
C & Ch ar a
CIS
3
m pari son
Co
4
d va n ta ges
Disa
5
ry
6 Summa
LOGO History of RISC/CISC

1974
1974 1978
1978 1980s
1980s 1982
1982 to
to 1983
1983

RISC
RISCchip
chipwas AA16-bit CISC
CISCwas
wasused
usedby
was 16-bitCISC
CISCchip
chip by RISC-I
developed RISC-Iprocessor
processor
developed atIBM
at IBMby
by was
wasused
usedby
byIntel's
Intel's
Motorola's 68040
Motorola's 68040 and
John andthe
theRISC-II
RISC-II
JohnCocke
Cocke. .  8086 processor.
8086 processor.
computer
computerprocessor
processor were
and weredeveloped
developed
and Intel's80486
Intel's 80486
LOGO What is RISC?
2
Elements that define a
1 following:
RISC processor are
 Single-cycle oper
ation aids in fast
execution of simple func
RISC is a  Load/Store archite
tions
ssor cture implemented
microproce due to the desired single
-cycle
oa c h
design appr operation
 Hardwired contro
e
using simpl
l provides for the
fastest possible single-c
s. ycle operation
instruction  Relatively few inst
ructions and
addressing modes makes
it easy for the
control unit to interpre
t instructions
 Fixed instruction
format makes
decoding of instructions
fast and easy
 More compile-tim
e effort offers
opportunity to explicitl
y move static
run-time complexity in
to compiler.
 Pipelining
LOGO RISC Characteristics

w i n s t ru ctions
ely fe
• Relativ f e w a d d ressing
ely
• Relativ
modes lim it ed to load
e m or y access
• M i n s t ructions
and st o re
r e d o n e within
o p e rations a
• Al l
t e rs o f t he CPU
the regis a n d e asily-
eng t h
• Fixed-l nstruction format.
i
decoded i n s t ruction
cy c le
• Single
execution nd micro
ired a
• Hardw e d control
progr a m m
LOGO

RISC Processor
LOGO
LOGO What exactly is CISC?
3
1
2
ss o r s h a v e the following
Uses complex
c e
Instructions
ro
CISC microp
s: e to variable
characteristic
instructions o n d u
are made up
o p e r a ti
 Multi-cycle f in s t ructions
intended for
ti m e o
execution
direct of smaller,  N o t a lo a d /s tore machine
icro -c o d e d co n tr ol engine
 Relies on m
implementat
ion simpler  More instru
cti o n s a n d a ddressing
high-level
instructions.
f a
of high-level k e t h a t o
modes li
g language
programmin at
language  Variable - le n g th in st ruction form
e number of
operations. depe n d e n t o n th
d r e ss in g modes used
a d
operands and
ic u lt ta r g e ts for optimizing
 Diff s e o f complex
r s b ec a u
compile
instructions
LOGO CISC Characteristics

1 2 4
Some • Variable-
A large instruc
tions 3 length
f
number o that pe
rform instruction
ns
instructio special
iz e A l ar ge formats
- typically tasks a d variety o
f
• Instructions
to nd are
from 100 used a dd r e s sing
that
250
ns.
infrequ
ently. modes - m a nipulate
tr uc ti o l l y 5 to
i ns ty pi c a op erands in
en t
20 differ memory.
modes.
LOGO

CISC Processor
LOGO Comparison
Factor RISC CISC
Complex architecture make it
Implementatio Simple architecture makes RISC difficult to implement on a
n Feasibility being realizable at earlier date single chip with the design
rules at that time
Lengthened design time may
Design that can be easier to lead to problems such as
design and debug can use much having a machine with an old
Design Time superior technology than design technology, or trying to predict
that takes a long time to future technology and have a
implement go at attempting to build that
technology
Gains in speed from better use
of chip area and from simple
More instructions and
design – with less instructions
Speed addressing modes result to
and addressing modes, these
complicated control structure
would lead to a less complicated
control structure
Area left on chip due to
Use of Chip simple design may be used to Complex design leaves no room
Area make RISC improve on chip for enhancements
performance even more
LOGO Comparison
LOGO Cisc Disadvantages
1 3

Instruction set & e

Setting th es take
chip hardware it io n c o d 4
cond
become more 2
ch time
complex with ea Programme
generation of Different to remembe
r s ha v e
computers. r to
instructions wil examine th
l e
take different condition co
de bits
amounts of clo before a sub
ck sequent
time to execute instruction
, changes
slowing down th them.
e
overall
performance o
f the
machine.
LOGO Risc Disadvantages
Code
Code Quality:
Quality:
•• The
The performance
performance ofof aa RISC
RISC processor
processor depends
depends greatly
greatly on
on the
the code
code that
that itit isis executing.
executing.
•• Developers
Developers have
have to
to choose
choose their
their compiler
compiler carefully
carefully based
based on
on the
the quality
quality ofof the the generated
generated code.
code.

Code
Code expansion:
expansion:
-Code
-Code expansion
expansion refers
refers toto the
the increase
increase inin size
size
System
System Design
Design of
of aa program
program that
that isis compiled
compiled for for aa CISC
CISC
-Require
-Require more
more memory.
memory. machine
machine andand re-compile
re-compile itit for
for aa RISC
RISC machine
machin
-They
-They require
require very
very fast
fast memory
memory systems
systems to
to
feed
feed them
them instructions.
instructions.
LOGO Instruction example
Cisc: Jump if Above
JA Ju
Risc:  There are
onl
instruction y two Jump
ump if Above or
s
JAE JJu processor in the ARM
Equal ( Branch
and Bran
ump if Below
JB JJu Link.)
.) ch with
 The
... "if equal,
if carry se
JPO Jump if Parity zero" type
of selectio t, if
handled b n
Odd y conditio is
n
JS Jump if Sign
options. F
or example:
ump if Zero
JZ JJu BLNV Br
NeVer anch wit
h Link
re 32 jump
re are
 There
e BLEQ B
instructions in th EQual
ranch w h
it Link if
8086(e.g. of Cisc
micro ocessorr)),
roprro • BL part is
and the 80386 the follow
the instruc
tion, and
re. ing part is
adds more conditio the
n.
LOGO
LOGO Summary

The long
RISC ve
CISC ha rsus
d es i gn h ave both arc s caused
RIS C to a hitecture
t h a t res u lt develop s to
advantages excellent processo and
machine’s e.
rs today
have
performanc a little b
something it of
from eac
architect h
ure.
 LOGO
RISC and CISC:
The Best Of Both Worlds

(AltiVec unit adds 162

new instructions to the
existing RISC
architecture)

Hybrid of the two design philosophies

known as a complex/reduced instruction
set computer-combine characteristics
such as variable-length instructions, few
general-purpose registers, pipelining,
and floating-point units.
LOGO