Module-6 Thumb Instruction Set

MODULE-6
Thumb Instruction
Set
Thumb Instruction Set
Thumb Instruction
Thumb Registers
ARM Thumb interworking
Branch instruction
Data processing instruction
Single/multiple load store instruction
Stack instruction
SWI instruction
THUMB INSTRUCTION
Thumb encodes a subset of the 32-bit ARM instructions
into a 16-bit instruction set space.
Thumb has higher performance than ARM on a

processor with a 16-bit data bus.
Lower performance than ARM on a 32-bit data bus.
 Thumb is preferredfor memory-constrained systems.

THUMB INSTRUCTION
Thumb has higher code density—the space taken up in
memory by an executable program—than ARM.
For memory-constrained embedded systems, for

example, mobile phones and PDAs, code density is
very important.
On average, a Thumb implementation of the same code

takes up around 30% less memory than the equivalent
ARM implementation.
THUMB INSTRUCTION
THUMB INSTRUCTION
THUMB INSTRUCTION
THUMB INSTRUCTION
THUMB INSTRUCTION
THUMB INSTRUCTION
Only the branch relative instruction can be conditionally
executed.
The limited space available in 16 bits causes the barrel shift
operations ASR, LSL, LSR, and ROR to be separate
instructions in the Thumb ISA.
Thumb Register Usage
In Thumb state, you do not have direct access to all
registers.
Only the low registers r0 to r7 are fully accessible.
The higher registers r8 to r12 are only accessible with

MOV, ADD, or CMP instructions.
CMP and all the data processing instructions that

operate on low registers update the condition flags in
the cpsr.
There are no MSR- and MRS-equivalent Thumb instructions. To
alter the cpsr or spsr, you must switch into ARM state to use
MSR and MRS.
Similarly, thereareno coprocessor instructions

in Thumb state. You need to be in ARM state to access
the coprocessor for configuring cache and memory
management.
Only the branch relative instruction can be conditionally

executed.
The limited space available in 16 bits causes the barrel shift

operations ASR, LSL, LSR, and ROR to be separate instructions
ARM-Thumb Interworking
ARM-Thumb interworking is the name given to the
method of linking ARM and Thumb code together for
both assembly and C/C++.
It handles the transition between the two states.
Extra code, called a veneer, is sometimes needed

to carry out the transition.
 ATPCS defines the ARM and Thumb procedure call

standards.
To call a Thumb routine from an ARM routine, the core
has to change state.
This state change is shown in the T bit of the cpsr.
The BX and BLX branch instructions cause a switch

between ARM and Thumb state while branching to a
routine.
The BLX instruction was introduced in ARMv5T.
On ARMv4T cores the linker uses a veneer to switch state

on a subroutine call.
Instead of calling the routine directly, the linker calls

the veneer, which switches to Thumb state using the BX
instruction.
There are two versions of the BX or BLX instructions: an
ARM instruction and a Thumb equivalent.
The ARM BX instruction enters Thumb state only if bit 0

of the address in Rn is set to binary 1; otherwise it
enters ARM state.
The Thumb BX instruction does the same.
Unlike the ARM version, the Thumb BX instruction

cannot be conditionally executed.
Branch Instructions
 There are two variations of the standard branch
instruction, or B.
1. The first is similar to the ARM version and is

conditionally executed
 The branch range is limited to a signed 8-bit
immediate, or−256 to +254 bytes.
2. The second version removes the conditional part

of the instruction
 Expands the effective branch range to a signed 11-
bit
immediate, or −2048 to +2046 bytes.
Branch Instructions
 The BL instruction is not conditionally

executed
Data Processing Instructions
The data processing instructions manipulate data within
registers.
They include move instructions, arithmetic instructions,

shifts, logical instructions, comparison instructions, and
multiply instructions.
The Thumb data processing instructions are a subset

of the ARM data processing instructions.
These instructions follow the same style as the
equivalent ARM instructions.
Most Thumb data processing instructions operate on

low registers and update the cpsr. The exceptions
are,
 The can operate on the higher registersr8–r14and the

pc.
Single-Register Load-Store Instructions
The Thumb instruction set supports load and
storing registers, or LDR and STR.
These instructions use two pre - indexed addressing

modes: offset by register and offset by immediate.
The offset by register uses a base register Rn plus the
register offset Rm.
The seconduses the same base registerRn plus a 5-

bit immediate or a value dependent on the data size.
Single-Register Load-Store
Instructions
This example shows two Thumb instructions that use a pre-
index addressing mode. Both use the same pre-
condition.
Multiple -Register Load-Store
Instructions
 They only support the increment after (IA) addressing
mode.
Here N is the number of registers in the list of registers. You

can see that these instructions always update the base register
Rn after execution.
The base register and list of registers are limited to

the low registers r0 to r7.
Multiple -Register Load-Store
Instructions
This example saves registers r1 to r3 to memory addresses
0x9000 to 0x900c. It also updates base register r4.
STACK INSTRUCTIONS
 The Thumb stack operations are different from the
equivalent ARM instructions because they use the more
traditional POP and PUSH concept.
STACK INSTRUCTIONS
 The interesting point to note is that there is no stack pointer
in the instruction.
 This is because the stack pointer is fixed as register r13 in

Thumb operations and sp is automatically updated.
 The list of registers is limited to the low registers r0 to

r7.
 The PUSH register list also can include the link register
lr; similarly the POP register list can include the pc.
 The stack instructions only support

STACK INSTRUCTIONS
 The link register lr is pushed onto the stack with register

r1.
 Upon return, register r1 is popped off the stack, as well as

the return address being loaded into the pc. This returns
SOFTWARE INTERRUPT
INSTRUCTION
 Similar to the ARM equivalent, the Thumb software
interrupt (SWI) instruction causes a software interrupt
exception.
 If any interrupt or exception flag is raised in Thumb

state, the processor automatically reverts back to ARM
state to handle the exception.
SOFTWARE INTERRUPT
INSTRUCTION
 The Thumb SWI instruction has the same effect and
nearly the same syntax as the ARM equivalent.
 It differs in that the SWI number is limited to the range

0 to 255 and it is not conditionally executed.
SOFTWARE INTERRUPT
INSTRUCTION
Programs
x = (a + b) - c;
ADR r4,a
LDR r0,[r4]
ADR r4,b
LDR r1,[r4]
ADD r3,r0,r1
ADR r4,c
LDR r2,[r4]
SUB r3,r3,r2
ADR r4,x
STR r3,[r4]
y = a*(b+c);
ADR r4,b
LDR r0,[r4]
ADR r4,c
LDR r1,[r4]
ADD r2,r0,r1
ADR r4,a
LDR r0,[r4]
MUL r2,r2,r0
ADR r4,y
STR r2,[r4]
Programs
To evaluate (A + 8B + 7C - 27)/4, where A = 25, B = 19,

and C = 99.
MOV r0,#25
MOV r1,#19
ADD r0,r0,r1,LSL #3
MOV r1,#99
MOV r2,#7
MLA r0,r1,r2,r0
SUB r0,r0,#27
MOV r0,r0,ASR #2
Programs
if (i == 0)
{
i = i +10;
}
SUBS R1, R1, #0
ADDEQ R1, R1, #10
CMP R1,#0
ADDEQ R1, R1, #10
Programs
for ( i = 0 ; i < 15 ; i++)

{
j = j + j;
}
SUB R0, R0, R0
Start CMP R0, #15
ADDLT R1, R1, R1
ADDLT R0, R0, #1
BLT start

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MODULE-6

ARM Thumb interworking

Data processing instruction

Single/multiple load store instruction

Thumb has higher performance than ARM on a

Lower performance than ARM on a 32-bit data bus.

 Thumb is preferredfor memory-constrained systems.

For memory-constrained embedded systems, for

On average, a Thumb implementation of the same code

Only the low registers r0 to r7 are fully accessible.

The higher registers r8 to r12 are only accessible with

CMP and all the data processing instructions that

Similarly, thereareno coprocessor instructions

Only the branch relative instruction can be conditionally

The limited space available in 16 bits causes the barrel shift

It handles the transition between the two states.

Extra code, called a veneer, is sometimes needed

 ATPCS defines the ARM and Thumb procedure call

This state change is shown in the T bit of the cpsr.

The BX and BLX branch instructions cause a switch

On ARMv4T cores the linker uses a veneer to switch state

Instead of calling the routine directly, the linker calls

The ARM BX instruction enters Thumb state only if bit 0

The Thumb BX instruction does the same.

Unlike the ARM version, the Thumb BX instruction

1. The first is similar to the ARM version and is

2. The second version removes the conditional part

 The BL instruction is not conditionally

They include move instructions, arithmetic instructions,

The Thumb data processing instructions are a subset

Most Thumb data processing instructions operate on

 The can operate on the higher registersr8–r14and the

These instructions use two pre - indexed addressing

The seconduses the same base registerRn plus a 5-

Here N is the number of registers in the list of registers. You

The base register and list of registers are limited to

 This is because the stack pointer is fixed as register r13 in

 The list of registers is limited to the low registers r0 to

 The stack instructions only support

 The link register lr is pushed onto the stack with register

 Upon return, register r1 is popped off the stack, as well as

 If any interrupt or exception flag is raised in Thumb

 It differs in that the SWI number is limited to the range

To evaluate (A + 8B + 7C - 27)/4, where A = 25, B = 19,

for ( i = 0 ; i < 15 ; i++)

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