Compiled by :- Er.

Praveen Kumar Karn Lalitpur Engineering College

Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College
BSR Mode (Bit Set/Reset): BSR mode is concerned only with
eight bits of port C, which can be set or reset by writing an
appropriate control word in the control register.
• A control word with bit D7=0 is recognized as a control word and
it does not alter any previously transmitted control word with bit
D7=1.
• Thus the I/O operations of ports A and B are not affected by a BSR
control word. In the BSR mode individual bits of port C can be
used for applications such as On/Off switch.
BSR Control Word:This control word, when written in control
register, sets or resets one bit at a time, as specified in figure.

Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College

Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College
BSR Control Word Examples:
Q.Determine the BSR Control word for the following Port C
configurations.

Operating modes of Intel 8255A:

Mode 0 (Basic I/O):- The functional configuration provides simple input
and output operation.No“handshaking”is required.
• Data is simply written to or read from a specified port.
• All ports can be used in this mode.
• Any ports can be I/O.
• Outputs are latched.
• Inputs are not latched. Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College
• 16 different I/O configurations are possible in this mode.
• Two 8-bit ports and two 4-bit ports.
Examples:
I. I/O Mapped I/O:
a) Identify the port addresses in given figure.
b) Identify the Mode 0 control word to configure port A as an input
port and port B as an output port.
c) Write a program to read the Dip switches and display the reading
from port A at port B.

Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College

 This is I/O mapped I/O; when A15 A14 A13 is 011, then chip select of
8255 is enabled. We also know that during the execution of IN and OUT
instruction, A15-A8 and AD7-AD0 carry the same signals. Keeping this in
mind, port addresses will be derived. Firstly, port A’s port address will be
calculated as under:
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 1 X X X X X = X X X X X X 0 0

To have equality, 0’s and 1’s on one side of the equation must appear on
other sides. This means that AD7 AD6 AD5 must equal 011 and A9 and A8
must equal 00 (port A) to get
0 1 1 X X X 00 = 0 1 1 X X X 00
Since the remaining don’t cares can be 0’s and 1’s, there are many solutions.
For instance, if all the don’t cares are equal to zero; address of port A
becomes 1110 0000 (60H). The port addresses of the given figure are
determined as under:
Port A = 60H
Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College
Port B = 61H
Port C = 62H
Control Register = 63H
b) The Mode 0 control word to configure port A input and port B
output is calculated as under:
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 X 0 0 X
=90H
c) Program subroutine to read DIP switches and display the reading
from port A at port B is as under:
MVI A, 90H; Load ACC with the control word
OUT 63H; Write the control word in control register and initialize
the ports
IN 60H; Reads switches at port A
OUT 61H; Display the reading at port B
RET
Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College
II. Memory mapped I/O
Write a program to read the DIP switches and display the reading
from port B at port A and from port C (lower) to port C(upper).
(Gaonkar, 2010) .
1.Port Addresses :- This is memory mapped I/O ; when the
address line A15 is high, the chip select line is enabled. Assuming
all don’t care lines are at logic 0,the port addresses are as follows
Port A =8000H(A1=0,A0=0)
Port B =8001H(A1=0,A0=1)
Port C=8002H(A1=1,A0=0)
Control Register=8003H(A1=1,A0=1)

Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College

Gjj

Figure :- Interfacing 8255 I/O Ports in Mode 0

Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College
Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College
Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College
Programming on BSR Mode
Any of the eight bits of port C can be set or reset using a single
output instruction. This feature reduces software requirements in
control-based applications.
• When Port C is being used as Status / Control for Port A or B, these
bits can be set or reset by using Bit Set/Reset. Word in the control
register when D7=0 is recognized as BSR control word and does
not affect the I/O operations of Port A and B.

Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College

Q. Write a BSR word subroutine to set bits PC7 and PC3 and reset them after 10ms.Use the
schematic in figure 15.3 and assume that a delay subroutine is available.
BSR Control Words
D7 D6 D5 D4 D3 D2 D1 D0
To set bit PC7 = 0 0 0 0 1 1 1 1 =0FH
To reset bit PC7= 0 0 0 0 1 1 1 0 = 0EH
To set bit PC3 = 0 0 0 0 0 1 1 1 =07H
To reset bit PC3 = 0 0 0 0 0 1 1 0 =06H
Port Address :- Control register address =83H
Subroutine :-
BSR : MVI A,0FH ;Load byte in accumulator to set PC7
OUT 83H ;set PC7=1
MVI A,07H ; Load byte in accumulator to set PC3
OUT 83H ;set PC3=1
CALL DELAY ; This is 10 ms delay
MVI A,06H ;Load byte in accumulator to reset PC3
OUT 83H ;reset PC3
MVI A,0EH ; Load byte in accumulator to reset PC7
OUT 83H ;reset PC7
RET
Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College
From an analysis of the above routine ,the following points can be noted :-
1.To set/reset bits in port C, a control word is written in the control register
and not in port C.
2. A BSR control word affects only one bit in port C.
3. The BSR control word does not affect the I/O mode.
(Q)Write a BSR control word to set PC7, PC6, PC5, PC4, PC3, PC2, PC1, and
PC0 and reset each after 1 second.
Mode 1(Strobe Input/output):- This mode is applicable for Port A and Port
B.
• There is two data port with 3 bit handshaking signal for each port.
• It provides a means for transferring I/O data to or from a specified port in
conjunction with strobes or handshaking signals.
Programming in Mode 1 (Strobe I/O Mode): In Mode 1, handshake signals
are exchanged between the MPU and peripherals prior to data transfer.
Two ports (A and B) function as 8-bit I/O ports.
They can be configured either as input or output ports. Each port uses three
lines from port C as handshake signals. The remaining two lines of port C
can beCompiled
used byfor
:- Er.simple I/OKarnfunctions.
Praveen Kumar Lalitpur Engineering College
• When Port A is to be programmed as an input port, PC3, PC4, and
PC5 are used for control, PC6 and PC7 can be Input or Output, as
programmed by bit D3 (Cupper) of the control word.
• When Port A is programmed as an output port, PC3, PC6, PC7 are
used for control and PC4 and PC5 can be Input or Output, as
programmed by bit D3 (Cupper) of the control word.
• When Port B is to be programmed as an input or output port,
PC0, PC1 and PC2 are all used for control.
Mode 1 Input :- Below figure shows Port A as input port (when it
operates in Mode 1) along with the control word and control
signals (for handshaking with a peripheral).
When the control word is loaded into control register, Group A is
configured in Mode 1 with Port A as an input port, Port A can
accept parallel data from a peripheral (like a keyboard) and this
data can be read by the CPU.

Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College

• The peripheral first loads data into Port A by making the STBA
input low. This latches the data placed by the peripheral on the
common data bus into Port A. Port A acknowledges reception of
data by making IBFA (Input Buffer Full) high. IBFA is set when the
STBA input is made low.
• INTRA is an active output signal which can be used to interrupt
the CPU so that the CPU can suspend its current operation and
read the data written into Port A by the peripheral.
• INTRA can be enabled or disabled by the INTEA flip-flop which is
controlled by BIT Set-Reset operation of PC4. INTRA is set (if
enabled by setting the INTEA flip-flop) after the STBA has gone
high again, and if IBFA is high.
• On receipt of the interrupt, the CPU can be made to read Port A.
The falling edge of the RD input resets IBFA and it goes low. This
can be used to indicate to the peripheral that the input buffer is
empty and that data can again be loaded into it.
Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College
Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College
Compiled by :- Er. Praveen Kumar Karn
Lalitpur Engineering College
• Above figure shows Port B as an input port (when in Mode 1). The
timing diagram and operation of Port B is similar to that of Port A
except that it uses different bits of Port C for control. INTEB is
controlled by Bit Set/Reset of PC2.
• If the CPU is busy with other system operations, it can read data
from the input port when it is interrupted. This is often called
Interrupt Controlled I/O.
• If the CPU is busy with other system operations, it can read data
from the input port when it is interrupted. This is often called
Interrupt Controlled I/O.
• The status word is accessed by reading Port C (A1 A0 must be 10,
RD and CS must be low). The status word format as assumed by
the bits of Port C when Ports A and B are input ports in Mode 1, is
shown in above figure.

Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College

Mode 1 Output
• Figure below shows Port A configured as an output port (when in Mode 1)
along with the control word and control signals (for handshaking with a
peripheral). When the control word is loaded into the control register, Group A
is configured in Mode 1 with Port A as an output port. The CPU can send out
data to a peripheral (like a display device) through Port A of the 8255.
• The OBFA’ output (Output Buffer Full) goes low on the rising edge of the WR
signal (when the CPU writes data into the 8255). The OBFA output from 8255
can be used as a strobe input to the peripheral to latch the contents of Port
A.
• The peripheral responds to the receipt of data by making the ACKA’ input
of the 8255 low, thus acknowledging that it has received the data sent out by
the CPU through Port A.
• The ACKA’ low resets the OBFA signal, which can be polled by the CPU
through OBFA of the status word to load the next data when it is high again.
• INTRA is an active high output of the 8255 which is made high (if the associated
INTE flip-flop is set) when ACKA is made high again by the peripheral, and
when OBFA goes high again (see timing diagram in Figure below).

Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College

• It can be used to interrupt the CPU whenever the output buffer is
empty. It is reset by the falling edge of WR when the CPU writes
data onto Port A. It can be enabled or disabled by writing a '1' or a
'0' respectively to PC6 in the BSR mode.
• Figure below shows Port B as an output port when in Mode 1. The
operation of Port B is similar to that of Port A. INTEB is controlled
by writing a '1' or '0' to PC2 in the BSR mode.
• The status word is accessed by issuing a Read to Port C. The
format of the status word as assumed by the bits of Port C
when Ports A and B are Output ports in Mode 1 is shown in Figure
below.

Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College

Compiled by :- Er. Praveen Kumar Karn
Lalitpur Engineering College
Mode 1 Output Control Signals:
OBF’ (Output Buffer Full): The OBF’ will go low to indicate that the
CPU has written data out to the specified port. The OBF’ will be
set with the rising edge of the WR’ input and reset by ACK’ input
being low.
Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College
ACK’(Acknowledgement Input): A low on this input informs the
8255A that the data from port A or port B has been accepted. In
essence, a response from the peripheral device indicating that it
has received the data output by the CPU.
INTR(Interrupt Request): A high on this output can be used to
interrupt the CPU when an output device has accepted data
transmitted by the CPU. INTR is set when OBF’, ACK’ and INTE are
all 1 and reset by falling edge of WR’.
INTE: This is an internal flip-flop to a port and needs to be set to
generate the INTR signal. The two flip-flops INTEA and INTEB are
set/reset using the BSR mode through PC6 and PC2.

Compiled by :- Er. Praveen Kumar Karn Lalitpur Engineering College

 References
• Microprocessor Architecture, Programming, and
Applications with 8085 by Ramesh S.Gaonkar
• Insights on Instrumentation II by Er.Hari Prasad
Aryal,Er.Shyam Dahal.
• Notes by Er.Saban kumar KC notes.

Compiled by :- Er. Praveen Kumar Karn

Lalitpur Engineering College