8086 Memory Banks

Dept. of Computer Science and Engineering

BRAC University
CSE 341 Team
Lecture References:

 Book:

 Microprocessors and Interfacing: Programming and Hardware,

Author: Douglas V. Hall

 The 8086/8088 Family: Design, Programming, And Interfacing,

Author: John Uffenbeck.

CSE – 341: Microprocessors

BRAC University
8086 Memory Organisation
  
RECAP:
 The 8086 has 20-bit address bus, so
it can address or 1,048,576
addresses.
 Each address can store a byte.
Hence, 8086 can store upto 1MB.
 Each read/write operation takes 1
bus cycle
CSE – 341: Microprocessors
BRAC University
8086 Memory Organisation

  
Each read/write operation takes 1 bus cycle
for 1 byte data
 To read/write 1 word or 2 bytes of data, the
µp would need 2 cycles
 To solve this problem by saving processing
time, memory is organized into memory
banks
 Odd and even banks
 With the use of and pins
CSE – 341: Microprocessors
BRAC University
8086 Memory Organisation

 Addresses are consecutively numbered

 All even numbers end with a 0 and all
odd numbers end with a 1

Even Odd
6= 110 5= 101
14 = 1110 13 = 1101
20 = 10100 27 = 11011
42 = 101010 35 = 100011

even odd
CSE – 341: Microprocessors
BRAC University
8086 Memory Organisation
 Even addresses are considered as the even/low bank, which
holds the content of the low byte while
 Odd addresses are considered as the odd/high bank, which
holds the content of the high byte

CSE – 341: Microprocessors

BRAC University
 8086 Memory Banks
  Pin Recap:
8086

 pins for carrying 20-bit address

 pins for carrying low data byte and for high byte
 when 0 indicates data bus carries high byte of data

 The memory for an 8086 is set

up in to 2 banks of up to
524,288 bytes or 512kB each
 This makes it possible to

𝑫 𝑫
  𝟕 − 𝑫𝟎
read/write a word with one
  𝟏𝟓 − 𝑫 𝟖
 𝑨𝟏𝟗 − 𝑨𝟏   ´
𝑩𝑯𝑬  𝑨𝟎 machine cycle
CSE – 341: Microprocessors
BRAC University
 8086 Memory Addressing
Data can be accessed from the memory in 4 different ways:
8 - bit data from Even Bank e.g. from address 00002
8 - bit data from Odd Bank e.g. from address 00003
16 - bit data starting from Even Address e.g. from 00002 and 00003
16 - bit data starting from Odd Address. e.g. from 00003 and 00004
Type of Transfer Data Lines

0 0 Word i.e.
a byte from each bank
0 1 Byte from odd bank
11 00 Byte from
Byte from even
even bank
bank
11 11 None -- 𝑫 𝑫
  𝟕 − 𝑫𝟎
None   𝟏𝟓 − 𝑫 𝟖
𝑨
  𝟏𝟗 − 𝑨𝟏  𝑨𝟎
  ´
𝑩𝑯𝑬
CSE – 341: Microprocessors
BRAC University
 A byte from Low/Even bank

  Requires one bus-cycle to read/write a data-byte.
 Valid address is provided via with = 0 & =1
 Byte of data fetched on
 Low bank enabled, High bank disabled

Type of Transfer Data Lines

1 0 Byte from even bank

𝑫
  𝟏𝟓 − 𝑫 𝟖 𝑫
  𝟕 − 𝑫𝟎
 𝑨𝟏𝟗 − 𝑨𝟏  = 1  =0
CSE – 341: Microprocessors
BRAC University
 A byte from High/Odd bank
 
 Requires one bus-cycle to read/write a data-byte.
 Valid address is provided via with = 1 & =0
 Byte of data fetched on
 Low bank disabled, High bank enabled

Type of Transfer Data Lines

0 1 Byte from odd bank

𝑫
  𝟏𝟓 − 𝑫 𝟖 𝑫
  𝟕 − 𝑫𝟎
 𝑨𝟏𝟗 − 𝑨𝟏 =0
    =1

CSE – 341: Microprocessors

BRAC University
 An aligned word
starting from an even address
 
 Requires one bus-cycle to read/write a data-word.
 Valid address is provided via with = 0 & =0
 Word of data fetched on
 Low bank and High bank enabled

Type of Transfer Data Lines

0 0 Word i.e.
a byte from each bank

𝑫
  𝟏𝟓 − 𝑫 𝟖 𝑫
  𝟕 − 𝑫𝟎
 𝑨𝟏𝟗 − 𝑨𝟏   ´ = 0
𝑩𝑯𝑬   =0

CSE – 341: Microprocessors

BRAC University
 An unaligned word
starting from an odd address
 
Requires two bus-cycles to read/write a data-word
 During the 1st bus-cycle, odd addressed LSB of the word is accessed from the
high memory bank via of data bus; = 1 & = 0
 During 2nd bus-cycle, physical address is auto-incremented to access the even
address MSB of the word from the Low bank via

1 2

𝑫 𝑫
  𝟕 − 𝑫𝟎
𝑫
  𝟏𝟓 − 𝑫 𝟖 𝑫
  𝟕 − 𝑫𝟎   𝟏𝟓 − 𝑫 𝟖
𝑨
  𝟏𝟗 − 𝑨𝟏
 𝑨𝟏𝟗 − 𝑨𝟏 =
 0   =1
 = 1  =0
CSE – 341: Microprocessors
BRAC University
 An unaligned word
starting from an odd address
2 bus-cycles required

  2nd bus-cycle:
physical add auto-incremented
1st bus-cycle:
  even addressed MSB via
odd addressed LSB via
𝑫
  𝟏𝟓 − 𝑫 𝟖 𝑫
  𝟕 − 𝑫𝟎
=1& =0
 𝑨𝟏𝟗 − 𝑨𝟏    

𝑫 𝑫
  𝟕 − 𝑫𝟎
𝑫
  𝟏𝟓 − 𝑫 𝟖 𝑫
  𝟕 − 𝑫𝟎   𝟏𝟓 − 𝑫 𝟖
𝑨
  𝟏𝟗 − 𝑨𝟏
 𝑨𝟏𝟗 − 𝑨𝟏 =
 0   =1
 = 1  =0
CSE – 341: Microprocessors
BRAC University
Thank You
Questions are welcome in the discussion class

CSE – 341: Microprocessors

BRAC University