Interfacing to the Real World

 Peripheral Chip Interfacing – Memory vs. IO Mapped

 Software Interaction with IO Chips
 Polled IO vs. Interrupt Driven IO
 Advantages and Disadvantages
 Operation, Rom and Ram based Vector tables - Example 6811
 Vectored and Auto Vectored IRQ – example using 68000

 Exceptions
 User and Supervisor Mode Processing
 Memory Management Unit (MMU) Interfacing
 Software Interrupts - Trap instructions

1
 IO Interfaces to the Real World
 Most microcomputer systems are designed for use in small embedded applications
where they typically interface to and control data from the real world.
 CPU manufacturers provide their own family of peripheral interface chips to make the
more common interfacing functions fairly straight forward and these chips are
interfaced to the CPU in more or less the same way as memory by hooking them up
to the Address and Data Buses and using R/W and Chip Selects off Address and IO
decoders.

Address and
RS-232
Serial Data Bus
Comms
CPU
(M6850) CPU
CPU
(68000)
PB1
Digital Parallel
Push PB2
IO
CPU
Button PB3 (M6821)
Inputs PB4

Events Timer/ ADC/ Analog In

Counter
CPU DAC
Clock (M6840)
CPU
(ADC8100) Analog Out
2
 Peripheral Chip Interfacing
 Manufacturers differ slightly in their interfacing Logic 0 (Write Operation)
between peripheral chips and CPU: Two
R/W
methods supported
 IO Mapped (supported mainly by Intel) IO
 Memory mapped (supported by most other Mapped
Data Bus Intel CPU
manufacturers) CPU
Peripheral
IO Mapped Peripherals Chip Address Bus
Reg AX
 Occupy a separate address space to memory. 55
Chip
 Primitive attempt to segregate Memory and IO. Select
 CPU issues a Signal (M/IO) to distinguish a IO Port
M/IO
Memory access from an IO access. CPU
Decoder
 IO/Memory decoders are enabled off M/IO
 Special IO instructions are needed to access Logic 0 - IO Access
address in the IO Space, i.e. ones that drive the Logic 1 – Memory Access
M/IO signal low. void func1() Memory Space
 For example Intel CPUs have the following 2 { FFFFFF
instructions.
#asm
IN Port #, Register
OUT 82, ax 8FFFFF
OUT Port #, Register IN 83, ax
#endasm
 Port # is presented as an 8 bit address. }
 Data transfer between register/IO over data bus. RAM
 Separate IO space approach fallen out of favour
as it means IO devices cannot be accessed
using ‘C/C++’ pointers, (which generate M signal
not IO) meaning that you have to embed IO Space
100000
assembly language into your C++ source code. 0000FF 007FFF 3
000000
IO Ports ROM
000000
 Peripheral Chip Interfacing
Memory Mapped Peripherals
 Share the same address space as main Logic 0 (Write Operation)

memory (i.e. they behave like memory). R/W

 System designer partitions an area of the
system memory space for use by memory Memory Data Bus
mapped peripherals simply by extending the Mapped
address decoder concept used by memory. CPU
Peripheral Motorola
 No need for separate IO space. Chip Address Bus
 No special instructions needed to access IO.
CPU
 Programs can use a pointer in C/C++ to access Chip
Select
IO adding versatility. Address
 IO devices vulnerable to programs accidentally CPU
Decoder AS
overwriting them.

Memory Space Memory Access used for IO

FFFFFF

C07FFF
IO Ports
C00000 void func1()
main()
8FFFFF {{
char
char *IOports
*ports = = 0xC00000;
0xC00000;
Example
Memory char
char cx;;
RAM
Map
*IOports
*ports = = 0x55
0x55 ; ;
100000 cx==*(IOports
*(ports + +1)1); ;
007FFF
}}
ROM 4
000000
 Peripheral Registers
 All peripheral chips regardless of how they are mapped, contain a number of
internal registers that control the configuration of the chip and supply the CPU
with important status information about the device. In addition, read and write
registers facilitate communication between CPU and outside world.

Address and
RS-232 Serial Data Bus
Comms
Chip
Control
CPU CPU
CPU
Status
Read Data
Write Data

Parallel
IO
Chip
PB1 Control
Digital
PB2 CPU Status
Push
Button
PB3 Read Data
inputs
PB4 Write Data 5
 Peripheral Registers
Example 6850 Serial Comms Chip Control Register
 Bits in this register control important functions in the chip.

 By writing to this register we can control the behaviour of our chip.

Control Reg 6850 B7 B6 B5 B4 B3 B2 B1 B0

Receiver Transmitter Clock Division

Word Select
Interrupt and Reset
Enable Control

Bit 7 : Receiver Control

Controls generation of an interrupt when a
character has been received.

Bits 5-6: Transmitter Control

Controls the state of the RTS line used with a
modem. Controls generation of interrupt when
transmitter empty.

Bits2-4: Frame Format

Data width (7 or 8 bits), Parity (odd, even,
none), Number of stop bits (1 or 2).

Bits 0-1: Reset and Clock divisor

Provides a software master reset for the device.
Clock division ratio (1, 16 or 64) i.e. effective
baud rate for transmitter and receiver sections.
6
 Peripheral Registers
Example 6850 Serial Comms Chip Status Register
 Individual bits in this register indicate the state of play within the chip.

 By reading this register we can determine the operating status of the chip.

Status Reg 6850

Bit 7: Device is generating an interrupt

Bit 6: Parity Error

Bit 5: Receiver Overrun

Bit 4 : Framing Error

Bit 3: Clear to Send (From a Modem)

Bit 2: Data Carrier Detect (From a Modem)

Bit 1: Transmit Data Register Empty

7
Bit 0: Receive Data Register Full
 6811’s On-Chip Memory Mapped IO
 A 64 byte area of the 6811 address space between locations [1000-103F] has been
set aside for the large number of IO ports, (digital, serial, analog, time, watchdog etc.)
that exist ‘on-chip’.
 Some of the memory mapped registers are shown below for the parallel IO ports.

Port A: 8 Bit port. In or Out

Port C: 8 Bit Bidirectional port.

Port B: 8 Bit Output port.

Port C Data Direction Register

0 = Input, 1 = Output

Port D: 6 Bit Bidirectional port.

Port E: 8 Bit Input port.

8
 Polled IO
Communicating with an IO Chip?
 Once initial configuration of the chip has been performed in software, the
question of how to communicate with the outside world arises.
 One simple approach is to poll each device in turn as part of a program loop.
 That is, we read the status of the device by interrogating its status register.
 When we determine that a device has something to say, we deal with it.
 A system with 3 peripheral IO chips might contain a polling loop like this one.

while(1)
{
if( serial IO port status register indicates character received)
// Get Character from device and buffer it somewhere.

if( parallel IO device status register indicates a push button pressed)

// get robot to back-up and change direction.

if( timer status register indicates time has elapsed)

// measure a critical temperature/pressure/speed or whatever.
}

9
 Polled IO
Advantages of Using Polling

 Software is pretty easy to write, involving nothing more than a simple loop
and a few ‘if’ tests to interrogate each device status in turn.

 Polling has the advantage that we make recognition of the asynchronous

inputs of the real world, synchronous to the execution of our program, i.e.
we get to chose when we recognise and respond to a real world input,
which makes testing and debugging of software much easier.

10
 Polled IO
Disadvantages of Using a Polling Loop

 Adding more IO devices to the system, degrades the response time to any
one of them since it takes longer to poll more devices in software.

 An input (such as a push button being momentarily pressed) could be

missed, if the signal is too brief to be recognised within the polling loop time
period or if the CPU is busy dealing with something else at the time.

 It is not very efficient. The execution time for one iteration of a polling loop
could take longer than the time required to generate the response.

 No Slack - A polling approach consumes 100% of CPU time leaving no

spare capacity for other activities that the system might need to perform. OK
if the system isn’t doing anything else then fine, but not so good if it is.

 Lack of prioritisation. If the CPU is busy dealing with less important

inputs/events, there is no way for a more important input to pre-empt it.

 In real-time systems, polling leads to non-deterministic response times and

inefficient utilisation of the CPU.
11
 Interrupt Driven IO
 A better solution to overcome the problems of polling would be to use interrupts.
 Here, instead of our CPU ‘asking’ each I/O device in turn if they have anything
important to report (i.e. polling), the I/O device itself can be programmed to
attract the attention of the CPU by asserting an Interrupt request signal (IRQ )
when it requires the attention of the CPU.
 CPU’s have varying numbers of interrupt request pins that are generally
prioritised, the 6811/8051 has 2, the 68000 has 7.

Address and Data Bus

RS-232 Serial
Comms
CPU
Chip
IRQ
CPU
CPU
Data Received IRQ1
PB1 Button Pressed
Digital Parallel IRQ2
PB2 Time-Out IRQ3
Push
Button IO
CPU
PB3
inputs Chip
PB4
IRQ

IRQ Control Register programs

chips IRQ capability Timer
CPU
12
IRQ
 Advantages of Interrupt Based Systems
 The response time to each IO device interrupt is independent of the number
of IO devices in the system (provided the system is not overloaded with
interrupt requests). This makes response times more predictable and leads
to a more deterministic system.

 IO devices can be prioritised in hardware thus a high priority IO device can

override (i.e. interrupt) a lower priority one.

 Inputs from the real world should never be missed even if the system is
busy. The interrupt signal will stay asserted until the CPU deals with it.

 Creates Spare Processing Capacity: The system is able to perform other

more mundane tasks at a lower priority level, or even sit idle, while waiting
for an IO device to inform it of the need to respond and thus CPU utilisation
is reduced enabling the CPU to do other things.

 This last point is particularly important in a multi-tasking operating system

environments where many programs may be scheduled simultaneously and
are time-sliced.

 In summary the use of interrupts leads to better response time and

improved CPU utilisation.
13
 Disadvantages to Interrupt Driven Systems
 Usually require more complex/expensive hardware and software architectures.
For example the system may require

 The use of IO devices capable of generating an interrupt (not all of them can
or may not be able to generate them under the conditions you want).

 More complex (multi-threaded) code to deal with the interrupt and route the
request for service to a users program where the data is then made
available to the main code (i.e. there are possibly problems of mutual
exclusion and thread synchronisation associated with the use of interrupts).

 More difficult to debug.

 Interrupts are asynchronous to the operation of the rest of the system and
can occur with unpredictable frequency and timing relative to the execution
of the program, making it very difficult to debug.

 Recreating the set of circumstances that led to the bug in your code is
virtually impossible since the real world cannot be single stepped and it may
be difficult to recreate the combination of asynchronous inputs that lead to14
the failure/bug being identified in the first place.
 Interrupts: the Basics
 An interrupt then is an asynchronous signal generated by an IO chip to
request service from a CPU.

 In response to an interrupt request (IRQ), the CPU:-

 Finishes the current instruction (which cannot be interrupted).

 Saves the value of the Program counter (PC) onto the hardware
stack – this is to enable the CPU to “remember” where it was in your
program so that it can resume after the interrupt has been dealt with.
 Saves the internal state of the processor onto the stack including
 The Condition Code Register (CCR)
 Other registers depending upon the particular CPU.

15
 Interrupts: the Basics
 Identifies and prioritises which external IRQ pin(s) are being
asserted. If two different IRQ pins are active at the same instant the
highest priority IRQ is dealt with first.

 Executes an Interrupt Service Routine (ISR) – which must as a

minimum

 Save additional CPU registers that might be overwritten by code within the ISR.
 Identify the chip asserting the IRQ by interrogating it’s status register.
 Deal with the reason for the interrupt (e.g. data has been received)
 Clear the interrupt within the device requesting service.
 Restore the additional registers saved above.
 Execute a return from Interrupt (RTI) instruction at the end of the ISR which
restores the CCR and PC registers stacked earlier.

 This last instruction (RTI) returns control of the CPU back to the
program immediately following the instruction where the interrupt
occurred. This action is summarised in the next diagram.
16
 Interrupt Action (the basics)

Normal Processing

Interrupt(s)
Complete
Current
Instruction [Stack P
C, CCR,
jump to
ISR]
Interrupt Service Routine (ISR)

Save Additional CPU Registers

Service Highest Priority Requesting Device
Main Program
(+ Clear it’s IRQ)
Suspended for
Duration of Restore Additional Registers
ISR
RTI
turn]
CCR , PC and re
[Restore

Ideally Keep ISR

Resume
With
Short and Fast
Rest
Of
Program

Interrupt Latency is a measure of the time taken to

service the IRQ. This is important in real-time systems as
all other processing is suspended during this time.
17
 Interrupt Action (the basics)
 Question: How does the CPU find its way to the Interrupt Service Routine (ISR)?
That is, how do we get it to execute the code that deals with the interrupt?

 At a purely hardware level, the CPU has been designed to fetch the address of the
Interrupt Service Routine from a special Vector Table located in Rom (so that it is
always there when power is applied.) when the interrupt occurs.

 The Vector Table also deals with Resets and other Exceptions in the same way.

 The Vector Table contains one entry for each IRQ that the CPU has been designed
to deal with (2 for the 6811 external interrupts, 7 for the 68000).

 Each entry in the vector table contains an address. It is to this address that the
CPU jumps and expects to find your ISR code to deal with the interrupt.

 If you are designing your own embedded microcontroller application, you must
place the address of your ISR into the Vector Table before you blow the ROM.

 Note: If you are running under an Operating system (Windows/Linux) or a debug

monitor (such as buffalo) these programs build an additional jump table (in RAM)
which allows you to install your ISR with a suitable system call after the system has
18
booted and after your main program begins execution.
 6811 Interrupt Vector Table
 The table opposite is the interrupt
“Vector” table for the 6811 which resides
at the top of the 64k memory map.
 Each vector table entry is 2 bytes in size
and contains a 16 bit address
corresponding to an ISR for that IRQ.
 The 6811 has a lot of built in IO
capability and many of these are able to
generate their own IRQ thus there are a
lot of entries in the vector table one for
each source of internal interrupt.
 Two external sources of interrupt are
triggered by the IRQ and XIRQ pins.
 When an XIRQ interrupt request is
received the 6811 fetches a 16 bit entry
from the vector table corresponding to
the XIRQ, i.e. the 16 bit address stored
at [FFF4,FFF5]
 It then jumps to the address specified by
that table entry and expects to find your
ISR to deal with devices connected to
the XIRQ pin.
 Note reset vector (FFFE,FFFF) works in
the same way as do all other kinds of
interrupt, each with its own vector except
that reset never returns
Vector for XIRQ found at $FFF4/FFF5 19
Each vector comprises a two byte entry
 Normal Processing 6811 XIRQ Interrupt Action (Detail)

XIRQ
Hardware Processing
Complete
Current Stack PC, CCR
Instruction
ROM Vector Table Store address of your XIRQ
Index into
Vector Table for FFC0 ISR in locations $FFF4-
XIRQ Entry $FFF5, i.e. ISR can be found
at $C000 in this example

Main Program
PC = $C000 Contents = $C000 XIRQ=[FFF4,FFF5]
Suspended for
Duration of ISR
FFFF

XIRQ Interrupt S. Routine $C000

Stack Additional CPU Registers

Service Requesting Device
Clear it’s IRQ
Restore Additional Registers
RTI
Resume
Rest
Of
Program

20
 Maskable Interrupts
 All interrupt capable peripherals have the ability to control whether the chip should
generate an interrupt or not via interrupt mask bits in the chips control register.

 In addition, all CPU’s have the ability to postpone recognition of some or all of their
interrupts until later, by “masking” the recognition of the interrupt within the CPU
status or condition code register

 In the case of the 6811, the IRQ and XIRQ external interrupts are controlled by the ‘I’
and ‘X’ bits in the 6811’s condition code register.

 These interrupts are initially masked after a reset to prevent spurious interrupts being
recognised while the system is being initialised.
 In the 6811 all internal memory mapped peripherals with interrupt generating
capability can be masked (disabled) by setting the ‘I’ bit in the 6811’s condition code
register

 There are two assembly language instructions in the 6811 instruction set to change
the value of the ‘I’ bit
 CLI - Clear Interrupt bit (allowing recognition of interrupts)
 SEI - Set Interrupt bit (postpone recognition until ‘I’ cleared)

 To enable the ‘X’ input, use the ‘TAP’ instruction – transfer accumulator A to condition
code register to clear the ‘X’ bit.
21
 Interrupts/Exceptions on other Processors
 The 68000, MIPS and ARM processor are typical of more modern 16/32/64 bit CPUs in that they offer a
wider range of prioritised interrupt levels.
 Support for Vectored interrupt handling, (the Peripheral chip directly points the CPU to its ISR).
 Interrupts are part of a more general ‘exception
handling’ policy which (for the 68000) is closely linked
to User and Supervisor states within the CPU (see later)

The 68000 Interrupt Interface

 7 prioritised IRQ levels encoded via IPL0 – IPL2
 Level 7 is non-maskable (cannot be ignored).
 Status register controls IRQ masking via bits I2 – I0
 Function code pins FC0-FC2 indicate type of bus
cycle and state. (Note interrupt acknowledge cycle).
 Note Supervisor and User modes and ‘S’ bit (see later)
Status Register

s I2 I1 I0

FC2 FC1 FC0 Memory access type

0 0 0 Undefined --reserved
0 0 1 User data access
0 1 0 User program access
0 1 1 Undefined --reserved
1 0 0 Undefined --reserved
1 0 1 Supervisor data access
1 1 0 Supervisor program access
1 1 1 Interrupt Acknowledge
22
 The 68000 Exception Table and Operation
Vector Vector Exception
 The table opposite shows the vector table for the Number Address Type/Description
68000. Each entry is 4 bytes in size. 0 000 Reset – Initial Stack Pointer
1 004 Reset – Initial Program Counter
2 008 Bus Error
Auto-Vectored Interrupts : Vectors 25 - 31 3 00C Address Error
4 010 Illegal Instruction
 Intended for use by dumb peripherals 5 014 Divide by Zero
 For IRQ levels 1-7, the CPU uses one of the auto 6 018 CHK Instruction
7 01C TRAPV Instruction
vectors 25-31 based on the level of the interrupt. 8 020 Privilege Violation
 Thus a dumb peripheral asserting a level 3 IRQ will 9 024 Trace Exception
10 028 Line 1010 Emulation
eventually be serviced by the ISR whose address 11 02C Line 1111 Emulation
can be found at location [00 006C-00 006F] 12 030 (Unassigned – Reserved)
13 034 (Unassigned – Reserved)
14 038 (Unassigned – Reserved)
User Programmable Vectored Interrupts: Vectors 15 03C Uninitialised Interrupt Exception
64 - 255 16 040 (Unassigned Reserved)
 Intended for modern 16-bit peripherals to provide a … … …
23 05C (Unassigned Reserved)
faster, more direct response to the IRQ. 24 060 Spurious Interrupt Exception
25 064 Level 1 Interrupt Auto Vector
Such devices are able to supply an 8 bit vector 26 068 Level 2 Interrupt Auto Vector
number (programmed into them as part of their 27 06C Level 3 Interrupt Auto Vector
28 070 Level 4 Interrupt Auto Vector
initialisation) during an interrupt acknowledge 29 074 Level 5 Interrupt Auto Vector
(IACK) cycle (i.e. pins FC2-FC0 = {1,1,1}). 30 078 Level 6 Interrupt Auto Vector
31 07C Level 7 Interrupt Auto Vector
32 080 TRAP #0 Instruction Vector
 This vector number is multiplied by 4 (i.e. shifted 33 084 TRAP #1 Instruction Vector
left 2 bit positions) to generate the address of the … … …
47 0BC TRAP #15 Instruction Vector
corresponding vector table entry. 48 0C0 (Unassigned - Reserved)
… … …
For example, an interrupting peripheral chip that 63 0FC (Unassigned – Reserved)
supplies vector #64 during an Interrupt 64 100 User Programmable Vectored Interrupt
… … …
Acknowledge cycle will eventually be serviced by 255 3FC User Programmable Vectored Interrupt
an ISR whose address can be found at location 23
[00 0100 – 00 0103]
 68000 Vectored Interrupts
 The 68000 supports seven levels of Prioritised Interrupts 1-7 via the
3 external CPU pins [IPL2 - IPL0]

 Level 0 indicates that no interrupt is present.

 Levels 1-7 are prioritised with 7 being the highest.
 The 68000’s status register bits (I2, I1, I0) indicate the current level of
interrupt request being serviced.
 Interrupt requests with a priority less than or equal to the current value
of I2, I1, I0 will be postponed until later.
 Level 7 interrupts are non-maskable and thus can never be ignored.

 The sequence of operations required to generate an interrupt

request is

 A peripheral requests attention by asserting its (IRQ*) output

 The IRQ* is connected to a priority encoder which generates a 3-bit
code indicating the highest level of Interrupt request currently being
generated.
 The 3 bit output from this encoder is connected to pins IPL0-IPL2

24
 68000 Vectored Interrupts
Upon receipt of an Interrupt Request
 The 68000 compares the level of the interrupt request with the value of its interrupt
mask flags (I2, I1, I0) in the Status register.

 If the requested interrupt level is greater than (I2, I1, I0), the interrupt is serviced,
otherwise it is postponed.

 In servicing the interrupt:

 The interrupt mask flags (I2, I1, I0) in the status register are set to the level of the
interrupt being serviced and the supervisor ‘S’ bit is also set to 1.

 The function code pins (FC2,FC1, FC0) are set to {111} to inform the system that an
interrupt acknowledge (IACK) is in progress

 The level of the interrupt being acknowledged is placed on (A3, A2, A1).

 A read of the data bus is performed (during which an intelligent peripheral has the
option to supply a vector number to the CPU during this IACK cycle).
 An external interrupt acknowledge decoder, decodes the address lines
(A3, A2, A1) in conjunction with the function code pins (FC2,FC1, FC0) and asserts one
of seven IACK* lines that connect back to the peripheral.

 The asserted IACK* line informs the interrupting device that it is about to be serviced.
25
 68000 Vectored Interrupts
 After the appropriate IACK* line is asserted by the 68000, the following
operations are performed.
 The peripheral supplies it’s Vector number onto the data bus lines (D0-D7).

 The peripheral drives DTACK*.

 The 68000 reads the vector number on (D0-D7), shifts this left 2 places (x4),
and accesses the interrupt service routine using the vector number as an
index into the vector table.
 Only one “vector capable” device should be wired directly to each IACK* line
to prevent multiple devices responding with their own vector number during
an interrupt acknowledge cycle.

 Note: There are two variations to this procedure

 If DTACK* is not asserted, BERR* (Bus Error) must be asserted by an
external timer to force a spurious interrupt exception. Vector 24 is then called
(see vector table). This would occur if no peripheral owned up to generating
the interrupt.
 If a peripherals vector register has not been initialized with an appropriate
vector number in software, it will generate $0F as the vector to force an
26
uninitialized interrupt vector exception. Vector 15 is called (see vector table).
 Level 2 IRQ at CPU
68000 IRQ1*
Encoded
0 IRQ2* 7
IPL0 IRQ3*
Interrupt 1 Priority Levels
IPL1 IRQ4* of IRQ
Request 0 Encoder
Inputs IPL2 IRQ5*
IRQ6*
IRQ7*

FC0
1
Function Code IACK1*
[1,1,1] = IACK FC1
1 IACK2* 7
Cycle
FC2
1 Interrupt IACK3* Levels
A01 0 Acknowledge IACK4* of
IACK Level on 1 Decoder IACK5* IACK
Address Bus A02
0 IACK6*
A03 IACK7*

CPU acknowledges level 2 IRQ

IRQ on
Status Reg ROM Vector Table Level 2
1
0 0 0 0
1
Stack Pointer IRQ* IACK* IRQ* IACK*
IACK
S bit Reset Vector
Received
Interrupt
Mask bits set
to level of IRQ Get Vector Register Vector Register Peripheral
being
ISR Vector 120 supplies
recognised 120 130 Vector #
Vector 130
Peripheral 1 Peripheral 2 onto Data
Bus
130
Address Bus
Peripheral
Data Bus Drives
27
DTACK* DTACK*
 Normal Processing
(User Mode)

Level 1 IRQ Hardware Processing

(Supervisor Mode)
Complete
Current Save PC, SR, S=1
Instruction
IACK Cycle Peripheral
Peripheral
Supplies
Supplies
Address = Vector << 2 Vector e.g.
Vector
64

ROM Vector Table

Main
00000000
Program
Suspended
for Duration
of ISR Address $100 Contents = $0000D000 Vector 64 - $000100 - $000103

Level 1 ISR at $0000D000

Stack Additional CPU Registers

Service Requesting Device
Clear it’s IRQ
S=0 Restore Additional Registers
RTE
Resume
Rest
Of
Program

Normal 68000 Vectored Interrupt Operation 28

 IRQ Sharing in a Vectored Environment: IRQ1*
Leads to faster Response than Polling IRQ2* 7
IRQ3* Levels
IRQ4* of IRQ
IRQ5*
IRQ6*
IRQ7*

IACK1*
IACK2* 7
IACK3* Levels
IACK4* of
IACK5* IACK
IACK6*
IACK7*
IACK* IACK* IACK* IACK*
Propagator Propagator Propagator Propagator

IRQ* IACK* IRQ* IACK* IRQ* IACK* IRQ* IACK*

If IACK* received
and CHIP is not
asserting IRQ,
Vector Register
propagator passes
Vector Register Vector Register Vector Register
on IACK* to next
120 121 122 123 in line. Furthest
away has lowest
Peripheral 1 Peripheral 2 Peripheral 3 Peripheral 4 priority

Address Bus Vector # 123 supplied

Data Bus

29

DTACK*
 Auto-Vectored Interrupts
 Auto-vectored interrupts are intended for ‘dumber’ peripherals that cannot
supply a vector during an Interrupt acknowledge cycle like the 6850, 6821 etc.
 The process is similar to Vectored interrupts except that after the appropriate
IACK* line is asserted during an interrupt acknowledge cycle by the 68000:

 The interrupting device will assert the 68000’s VPA* line (Valid Peripheral
Address)
 Upon receiving an asserted VPA* line, the 68000 knows that the peripheral
is a dumb device incapable of supplying a vector. The 68000 then:

 Generates its own interrupt vector number internally based upon the priority
level of the IRQ* line that is being asserted.
 The 68000 reserves vector numbers 25-31 for auto vectored interrupts on
IRQ1*-IRQ7*
 Several peripherals can be assigned to the same IRQ* level, in which case
the appropriate auto-vectored interrupt handler routine will have to resort to
POLLING each of the possible peripheral by reading their interrupt status
registers to determine which of them is generating the interrupt.
30
 Level 2 IRQ at CPU
68000 IRQ1*
Encoded
0 IRQ2*
IPL0* IRQ3*
Interrupt 1 Priority 7
IPL1* IRQ4* Levels
Request 0 Encoder of IRQ
Inputs IPL2* IRQ5*
IRQ6*
IRQ7*

FC0
1
Function Code IACK1*
[1,1,1] = IACK FC1
1 IACK2*
Cycle
FC2
1 Interrupt IACK3*
7
Levels
A01 0 Acknowledge IACK4* of
IACK Level on
A02 1 Decoder IACK5* IACK
Address Bus IACK6*
A03 0
IACK7*
IACK on level 2
IRQ on
Status Reg Vector Table Level 2
0
1 0 0
1 0
Stack Pointer IRQ*
S bit Reset Vector IACK
Interrupt Received
Mask bits set
to level of IRQ Get
being Vector 25
ISR
recognised Dumb
Vector 26
Peripheral
VPA
Generated

Address Bus

Data Bus
31
VPA*
 Normal Processing
(User Mode)

Level 3 IRQ Hardware Processing

(Supervisor Mode)
Complete
Current Save PC, SR, S=1
Instruction
ROM IRQ Auto Vector Table
Index into Vector
Table for Level 3 00000000
IRQ

$0000D000 Level 1 IRQ (Auto Vector) $000064 - $000067

$0000E000 Level 2 IRQ (Auto Vector) $000068 - $00006B
Main PC = $0000F000 $0000F000 Level 3 IRQ (Auto Vector) $00006C - $00006F
Program $00010000 Level 4 IRQ (Auto Vector) $000070 - $000073
Suspended $00011000 Level 5 IRQ (Auto Vector) $000074 - $000077
for Duration
of ISR $00012000 Level 6 IRQ (Auto Vector) $000078 - $00007B
$00012000 Level 7 IRQ (Auto Vector) $00007C - $00007F

Level 3 ISR at $0000F000

Stack Additional CPU Registers

S=0 Service Requesting Device
Clear it’s IRQ
Resume Restore Additional Registers
Rest RTE
Of
Program

68000 Auto Vectored Interrupt Operation 32

 68000 Processing and Privilege States
 To fully appreciate how the 68000 and other advanced processors deal with exceptions one
has to appreciate that the 68000 is always operating in one of two states.
 The state information is used by memory management units (MMUs) which are used to
enforce protection between Kernel and Process code
 Supervisor mode (S-bit in 68000’s Status register is 1) is reserved for executing
operating system code and is associated with a higher level of privilege that user mode.
 User mode (S-bit in 68000’s status register is 0) is reserved for executing user
programs, and is associated with a lower level of privilege than supervisor mode.
 Certain instructions and access to memory and memory mapped peripherals may be
limited in user mode to constrain the process to accessing only the resources allocated
to it by an operating system.

 From the state transition diagram below, we see that once the CPU enters user mode, the
only way to move to the Supervisor mode is via an exception, such as a reset, interrupt, etc.
 An RTE instruction is used to restore the state of the CPU to that which it was in prior to the
exception occurring, for example to change state back to user mode.
 The RTE instruction itself is privileged: You can only execute it in the supervisor mode
Exception: IRQ, Reset etc

User Supervisor
Mode Mode

33
 Typical 68000 MMU Interface
MMU validates each access to memory made by the
code. If the code is running in supervisor mode, access
MMU is always allowed, if in user mode, address is validated
MMU against a set of look up tables and a Page
Address
Address fault/exception may be generated by the 68000’s
Decoder
Decoder BERR* signal to signal an invalid access

Logical
68000 Address Physical
CS
Address Memory/IO
Memory
Address Bus System
System
A1 – A23 Address
AS Memory ((Decoder
Decoder plus
plus
AS
Management Memory
Memory))
BERR Unit
Page Fault exception

Type of memory access

and Privilege Translation
Look aside
FC0 – FC2 Buffer

D0 – D15 ‘16’ bit wide Data Bus

34
 Software Interrupts and System Calls
Vector Vector Exception
Trap Exceptions Number Address Type/Description
0 000 Reset – Initial Stack Pointer
 These 15 instructions provide a means to 1 004 Reset – Initial Program Counter
execute an OS Kernel call via an exception. 2 008 Bus Error
 Sometimes known as a ‘software interrupt’ since 3 00C Address Error
4 010 Illegal Instruction
the behaviour is similar to hardware but initiated 5 014 Divide by Zero
via an instruction rather than a physical signal 6 018 CHK Instruction
 Imagine an OS kernel that contains 1000’s of 7 01C TRAPV Instruction
8 020 Privilege Violation
system level calls. 9 024 Trace Exception
 The user program needs to make these calls, but 10 028 Line 1010 Emulation
their execution requires the CPU be in supervisor 11 02C Line 1111 Emulation
12 030 (Unassigned – Reserved)
mode as the call often involves accessing 13 034 (Unassigned – Reserved)
resources that are not normally accessible by the 14 038 (Unassigned – Reserved)
program e.g. Kernel Code/IO devices etc. so 15 03C Uninitialised Interrupt Exception
they cannot be called like a conventional 16 040 (Unassigned Reserved)
… … …
subroutine because that would lead to an access 23 05C (Unassigned Reserved)
made in user mode (and the MMU would not 24 060 Spurious Interrupt Exception
permit it). 25 064 Level 1 Interrupt Auto Vector
26 068 Level 2 Interrupt Auto Vector
 Instead the OS call is allocated a number, e.g. 27 06C Level 3 Interrupt Auto Vector
open file might be 250, the kernel call is made by 28 070 Level 4 Interrupt Auto Vector
loading 250 into CPU register D0 and then 29 074 Level 5 Interrupt Auto Vector
executing one of the trap instructions associated 30 078 Level 6 Interrupt Auto Vector
31 07C Level 7 Interrupt Auto Vector
with calling the Kernel. 32 080 TRAP #0 Instruction Vector
 The exception handler for the Trap instruction is 33 084 TRAP #1 Instruction Vector
… … …
called and it interprets the number in D0 and 47 0BC TRAP #15 Instruction Vector
calls the correct kernel function (with the CPU 48 0C0 (Unassigned - Reserved)
now in supervisor mode so that the MMU will … … …
permit it). 63 0FC (Unassigned – Reserved)
64 100 User Programmable Vectored Interrupt
 At the end of the Kernel call, an RTE instruction … … …
return the CPU back to the calling program in 255 3FC User Programmable Vectored Interrupt
User Mode. 35
 Entry to Supervisor mode triggered by an exception

Device1
Device1 Device2
Device1 Device3
Device1 Device4
Device1

Interrupt Interrupt Interrupt Interrupt

Reset Interrupt
Push Button Operating
Operating System
System RTC
Device1 Device1
(Supervisor
(Supervisor Mode)
Mode)

SS == 11 Full
Full Privileges
Privileges

SS == 00 Limited
Limited Privileges
Privileges

System Call System Call System Call

(Trap Exception) (Trap Exception) (Trap Exception)
Exit() CreateThread() OpenFile()

User
User Program
Program 11 User
User Program
Program 21 User
User Program
Program 31
(User
(User Mode)
Mode) (User
(User Mode)
Mode) (User
(User Mode)
Mode)

36