Digital Circuit Design Lab

Part- B
Part B: To design and simulate using
CAD tools

1. 8:3 priority encoder.

2. Ring counter.
3. Asynchronous counter.
4. Simple Data path
5. ALU Design
6. Open Ended Experiment

Software - Xilinx
Language - Verilog
What is Verilog HDL?
 Why using Hardware Description Language?
 Design abstraction: HDL ←→ layout by human
 Hardware modeling
 Reduce cost and time to design hardware
 Two Popular HDLs
 VHDL
 Verilog
What is Verilog HDL?
 Key features of Verilog
 Supports various levels of abstraction
 Behavior level
 Register transfer level or dataflow
 Gate level or structural level
 Switch level or transistor level
 Simulate design functions
Basic Limitation of Verilog

Description of digital systems only

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Verilog Value Set
 0 represents low logic level or false condition

 1 represents high logic level or true condition

 x represents unknown logic level

 z represents high impedance logic level

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Numbers in Verilog (i)

<size>’<radix> <value>

No
Noofof Binary
Binary 
bbororBB Consecutive
bits Consecutivechars
chars
bits Octal
Octal 
ooor
orOO 0-f,
0-f,x,x,zz
Decimal
Decimal 
ddor
orDD
Hexadecimal
Hexadecimal hhororHH

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Numbers in Verilog (ii)

 You can insert “_” for readability

 12’b 000_111_010_100
 12’b 000111010100 Represent the same number

 12’o 07_24

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Number Representation

 Examples:
 6’b010_111gives 010111
 8’b0110 gives 00000110
 4’bx01 gives xx01
 16’H3AB gives 0000001110101011
 24 gives 0…0011000
 5’O36 gives 11110
 16’Hx gives xxxxxxxxxxxxxxxx
 8’hz gives zzzzzzzz
Data Type: Register
 Register
 Keyword: reg, integer, time, real
 Storage element (modeling sequential circuit)
 Assignment in “always” block (LHS of expressions)
Data Type: Net
 Net
 Keyword: wire, wand, wor, tri, triand, trior, supply0, supply1
 Doesn’t store value, just a connection
 Input, output and inout ports are default “wire”
Vectors
 Represent buses
wire [3:0] busA;
reg [1:4] busB;
reg [1:0] busC;
 Left number is MS bit
 Slice management
busC[1]
busC = busA[2:1];  = busA[2];
busC[0] = busA[1];

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Bitwise Operators (i)
 &  bitwise AND
 |  bitwise OR
 ~  bitwise NOT
 ^  bitwise XOR
 ~^ or ^~  bitwise XNOR

 Operation on bit by bit basis

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Bitwise Operators (ii)

c = ~a; c = a & b;

 a = 4’b1010;
b = 4’b1100;

c = a ^ b;

 a = 4’b1010;
b = 2’b11;

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Shift Operators
 >>  shift right
 <<  shift left

 Result is same size as first operand, always zero filled

a = 4’b1010;
...
d = a >> 2; // d = 0010
c = a << 1; // c = 0100

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 Concatenation Operator
 {op1, op2, ..}  concatenates op1, op2, .. to single number
 Operands must be sized !!
reg a;
reg [2:0] b, c;
..
a = 1’b 1;
b = 3’b 010;
c = 3’b 101;
catx = {a, b, c}; // catx = 1_010_101
caty = {b, 2’b11, a}; // caty = 010_11_1
catz = {b, 1}; // WRONG !!
 Replication ..
catr = {4{a}, b, 2{c}}; // catr = 1111_010_101101
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Relational Operators

 >  greater than

 <  less than
 >=  greater or equal than
 <=  less or equal than

 Result is one bit value: 0, 1 or x

1 > 0 1
’b1x1 <= 0  x
10 < z x

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Equality Operators

 ==  logical equality
Return 0, 1 or x
 !=  logical inequality
 ===  case equality
Return 0 or 1
 !==  case inequality

 4’b 1z0x == 4’b 1z0x x

 4’b 1z0x != 4’b 1z0x  x
 4’b 1z0x === 4’b 1z0x  1
 4’b 1z0x !== 4’b 1z0x  0

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Conditional Operator
 cond_expr ? true_expr : false_expr

 Like a 2-to-1 mux ..

A
1
Y
B Y = (sel)? A : B;
0
sel

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 Hierarchical Design

Top
TopLevel
Level E.g.
Module
Module

Full
FullAdder
Adder
Sub-Module
Sub-Module Sub-Module
Sub-Module
11 22

Half
HalfAdder
Adder Half
HalfAdder
Adder
Basic
BasicModule
Module Basic
BasicModule
Module Basic
BasicModule
Module
11 22 33

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Module

module my_module(out1, .., inN);

in1 my_module out1 output out1, .., outM;
in2 out2 input in1, .., inN;

f .. // declarations
inN outM .. // description of f (maybe
.. // sequential)

endmodule

Everything you write in Verilog must be inside a module

exception: compiler directives

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Example: Half Adder

A module half_adder(S, C, A, B);

S
output S, C;
B input A, B;
C
wire S, C, A, B;

A S assign S = A ^ B;
Half assign C = A & B;
Half
B Adder
Adder C
endmodule

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 Example: Full Adder
in1 A S I1 A S sum
Half
Half Half
Half
Adder
Adder11 Adder
in2 B C I2 B Adder C I3
ha1
ha1 ha2
ha2 cout

cin
module full_adder(sum, cout, in1, in2, cin);
output sum, cout;
input in1, in2, cin;

wire sum, cout, in1, in2, cin;

Module wire I1, I2, I3; Instance
name name
half_adder ha1(I1, I2, in1, in2);
half_adder ha2(sum, I3, I1, cin);

assign cout = I2 || I3;

endmodule
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Hierarchical Names

ha2.A

in1 A Half S I1 A Half S sum

Half Half
Adder
Adder11 Adder
in2 B C I2 B Adder C I3
ha1
ha1 ha2
ha2 cout

cin

Remember to use instance names,

not module names

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Structural Model (Gate Level)
 Built-in gate primitives:
and, nand, nor, or, xor, xnor, buf, not, bufif0,
bufif1, notif0, notif1

 Usage:
nand (out, in1, in2); 2-input NAND without delay
and #2 (out, in1, in2, in3); 3-input AND with 2 t.u. delay
not #1 N1(out, in); NOT with 1 t.u. delay and instance name
xor X1(out, in1, in2); 2-input XOR with instance name
 Write them inside module, outside procedures

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Example: Half Adder,
2nd Implementation

A module half_adder(S, C, A, B);

S
output S, C;
B input A, B;
C
wire S, C, A, B;

xor (S, A, B);

and (C, A, B);

endmodule

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Behavioral Model - Procedures (i)
 Procedures = sections of code that we know they
execute sequentially
 Procedural statements = statements inside a procedure
(they execute sequentially)
 e.g. another 2-to-1 mux implem:
begin
if (sel == 0)
Execution Y = B;
Flow else Procedural
Proceduralassignments:
assignments:
Y = A; YYmust
mustbe
bereg
reg!!!!
end

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Behavioral Model - Procedures (ii)

 Modules can contain any number of procedures

 Procedures execute in parallel (in respect to each other)
and ..
 .. can be expressed in two types of blocks:
 initial  they execute only once
 always  they execute for ever (until simulation finishes)

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“Initial” Blocks
 Start execution at sim time zero and finish when their
last statement executes
module nothing;

initial
$display(“I’m first”); Will
Willbe bedisplayed
displayed
atatsim
simtime
time00
initial begin
#50;
$display(“Really?”); Will
Willbe bedisplayed
displayed
atatsim
simtime
time5050
end

endmodule

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“Always” Blocks
 Start execution at sim time zero and continue until sim
finishes

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Events (i)
 @
always @(signal1 or signal2 or ..) begin
..
end execution triggers
execution triggersevery
every
time
timeany
anysignal
signalchanges
changes
always @(posedge clk) begin
.. execution
executiontriggers
triggersevery
every
end time
timeclk
clkchanges
changes
from
from00to
to11
always @(negedge clk) begin
.. execution
executiontriggers
triggersevery
every
end time
timeclk
clkchanges
changes
from
from11to
to00

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 Examples
 3rd half adder implem
module half_adder(S, C, A, B);
output S, C;
input A, B;

reg S,C;
wire A, B;

always @(A or B) begin

S = A ^ B;
C = A && B;
end

endmodule
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Procedural Statements: if
E.g. 4-to-1 mux:
module mux4_1(out, in, sel);
output out;
if (expr1) input [3:0] in;
true_stmt1; input [1:0] sel;

reg out;
else if (expr2) wire [3:0] in;
wire [1:0] sel;
true_stmt2;
.. always @(in or sel)
if (sel == 0)
else out = in[0];
def_stmt; else if (sel == 1)
out = in[1];
else if (sel == 2)
out = in[2];
else
out = in[3];
endmodule

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 Procedural Statements: case

E.g. 4-to-1 mux:

module mux4_1(out, in, sel);
case (expr) output out;
input [3:0] in;
input [1:0] sel;
item_1, .., item_n: stmt1;
reg out;
item_n+1, .., item_m: stmt2; wire [3:0] in;
.. wire [1:0] sel;

default: def_stmt; always @(in or sel)

case (sel)
0: out = in[0];
endcase 1: out = in[1];
2: out = in[2];
3: out = in[3];
endcase
endmodule

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 Test Methodology

Stimulus

Hardware Design
Testbench
(Design Under Test)

Response

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