Introduction to the

Next Generation High-Performance

200 MHz PIC32MZ
Stu Chandler, Principal TTE
Microchip Technology, Inc.
 Objectives
● When you complete this class you
should be able to:
● Describe the differences between the MIPS®
M4K™ and MIPS® microAptiv™ cores
● Describe PIC32MZ Oscillators and Clocks
● Describe PIC32MZ External Memory Interfaces
● Describe PIC32MZ High-Speed USB Features
● Understand and utilize PIC32MZ Low-Speed
Peripherals, Timers and I/Os
● Explain the role and use of the new MPLAB
HARMONY eco-system

2
 Agenda
● Why PIC32MZ?
● Introduction to PIC32MZ
● CPU
● Clocks
● Memory Management
● I/O
● Peripherals
● Development Tools
● HW Tools
● Introduction to MPLAB HARMONY
● Resources and Summary

3
Why PIC32MZ?

4
 A Successful Platform
Auto Diagnostics HVAC Air Handler Photo ID Management
Engine
Optical Stabilization Control

Home Lighting Security System Docking Station

Control Panel Power
Server Diagnostic GPS Tracking
Meter
Monitoring

White Goods Graphics GPS Control

Audio Head Bar code
Phones Scanner
Robotic Vacuum
Remote
Cleaner
Control

5
 Worldwide 32-bit Microcontroller
Market Share (USD)
8-bit MCU Supplier Ranking

16-bit MCU Supplier Ranking

Based on dollar shipment volume 2010-2012, Source: Gartner and Microchip

6
 "Which of the following 32-bit chip families would you
consider for your next embedded project?"

EE Times 2013 Annual Survey

Microchip PIC 32-bit (MIPS) 33% Other 4%

STMicro STM32 (ARM) 28% Freescale PowerPC 7xx, 8xx 4%
TI Stellaris (ARM) 26% Qualcomm (any) 3%
NXP LPC (ARM) 21% Xilinx Virtex-5 (with PowerPC 405) 3%
Atmel (AVR32) 19% Microsemi SmartFusion SoC FPGA (Cortex-M3) 3%
Atmel SAMxx (ARM) 17%
FreescaleKinetis (Cortex-M4/M0) 15% AMD Fusion, Athlon, Sempron, Turion, Opteron, Geode 3%
Arduino 13% Freescale Vybrid (ARM) 3%
TI OMAP 12% NVIDIA Tegra 3%
Atmel AT91xx 11% Microsemi FPGA (Cortex-M1, soft) 3%
TI C2000 MCUs 10% Xilinx Virtex-4 (with PowerPC 405) 3%
TI Sitara (ARM) 10% Freescale PowerQUICC 2%
Freescale i.MX (ARM) 9% Infineon XMC4000 (ARM) 2%
Cypress PSOC 5 (ARM) 9%
Altera Nios II (soft core) 8% Broadcom 2%
RenesasSuperH, H8SX, M32C, M32R 8% NEC V850 2%
Freescale 68K, ColdFire 8% Cirrus Logic EP73xx, EP93xx (ARM) 2%
Xilinx Zynq (with dual ARM Cortex-A9) 8% Marvell 2%
Xilinx MicroBlaze (soft-core) 8% Intel Itanium 2%
Intel Atom, Pentium, Celeron, Core 2, Core iX 7% Fujitsu FM3 (ARM) 2%
Altera SoC-FPGA (with dual ARM Cortex-A9) 7% AMD Alchemy (MIPS) 1%
TI Hercules (ARM) 7%
Energy Micro EFM32 6% IBM PowerPC 4xx, 7xx 1%
SiLABS Precision32 (ARM) 5% Infineon Tricore 1%
Freescale PowerPC55xx 4% Those clock rate are under 100 MHz SPARC (any) 1%
Microsemi SmartFusion2 SoC FPGA (Cortex-M3) 4% Fujitsu FR Series 1%
Freescale PowerPC 5xx, 6xx 4% AMCC PowerPC 4xx 1%
IDT 32xxx 0%
Atmel AT91xx/ATSAMxx (ARM) 0%

7
 PIC32 in Production
250

214

200

150
130

100

66 70

50 46
34
18

0
1 CY08 2
CY09 3
CY10 4
CY11 5
CY12 6
CY13 CY14 7

8
 Competitive Arena
The Perception
● Code can easily be ported between two
Cortex-M MCUs from different vendors
● If both offer Standard Peripheral libraries
that are CMSIS* compatible
● Standardizing on an ARM core
architecture future proofs your design
● MCUs are a commodity if they are ARM
core based
* Cortex Microcontroller Software Interface Standard

9
 Competitive Arena
The Reality
● Competing MCUs are not pin-to-pin
compatible – even though they might use the
same core
● Peripherals and other parts of MCUs are
never implemented in the same way
● Results in different peripheral libraries
● Even though the may comply with a coding standard
● E.g. ARM’s CMSIS
● Different functionality
● Always some effort to port code
● How big depends on the complexity of application and
the peripherals being used
10
 Competitive Arena
The Facts
● ARM MCU vendors products are NOT pin-to-pin,
peripheral or firmware compatible
● Porting to a PIC32 takes the same effort
● If code is developed to be portable between to different
MCUs (like two ARM based ones) it can be just as easily
be ported to a 3rd MCU with different core, like PIC32
● Big part of code development for MCUs is related
to the peripherals
● This is where the work is for porting to another vendors
MCU and it isn’t related to the core

11
 PIC32 is Different by Design

Long-standing relationship with MIPS

MIPS microAptiv core used in PIC32MZ was developed
based heavily on feedback from Microchip!

12
 Common PIC®
MCU Development Platform
PIC32
Integration

dsPIC33
dsPIC30
o ls
To PIC24H
on i es
mm PIC24F rar
b
Co Li
on
PIC18 m
m
Co
PIC16
PIC® microcontrollers
PIC10/12 8 Bit 16 Bit 32 Bit

Performance
13
Integrated Development
Environment

14
 Introducing MPLAB Harmony

• What is MPLAB Harmony?

• An innovative approach to Harmonize Microchip software
solutions
• Flexible, Robust platform that provides a complete framework
for PIC32 firmware development
• Layered and Modular Architecture for Software
Interoperability
• Why do we need it? Flexible
• Portability
• Configurability Re-Usable
MPLAB
Modular

• Modularity Harmony

• Compatibility
• Flexibility
Compatible Interoperable

• Quality

15
 MPLAB Harmony
Eco-System for PIC32
PIC32 Software Development Tools available with MPLAB Harmony

Operating System Abstract Layer

Applications Device Drivers
(OSAL)
 File Systems OSAL Interface  ADC
 Graphics OSAL for freeRTOS  Epson LDC Controller
 TCP/IP & Utilities OSAL for OpenRTOS  Non-Volatile Memory
 USB OSAL for Micrium/µC-  SPI, USART, High-Speed
OS/III USB
 Ethernet Media Controller
3rd Party Software  Ethernet PHY Interface
 Controller-less graphics
 freeRTOS
Development Software  Timer, parallel master port
 OpenRTOS
 MPLAB X IDE  TCP/IP (Interniche) Leading OS Vendors & Software library
 MPLAB XC32  CyaSSL Embedded SSL specialists are developing solutions for
 MAPLAB XC32++  µC-OS/III (Micrium) PIC32

16
 Why PIC32?
● Technical support when you need it
● Making sure the porting of the code goes smoothly
● Broad selection of Microchip & 3rd Party tools and
software
● Peripheral libraries and other software to minimize the
coding efforts
● Free IDE MPLAB X and free XC32 compiler
● Peripheral Pin Select (PPS)*
● Remapping of digital peripherals to different pins
● Reducing PCB changes
● Higher performance
● Ready for future needs *Available on all newer PIC32 products

17
200MHZ / 314DMIPS
PIC32MZ Introduction

18
 PIC32 Roadmap

PIC32MZ PIC32MZ DA
PIC32MZ EC
Platform High Performance
200MHz Embedded
Graphics Family
Connectivity Family
314 DMIPS Low Power

PIC32MX Platform PIC32MK GP PIC32MK DA

50/80 MHz, 66/100 DMIPS
General Purpose Low Cost Graphics
PIC32MX 3,4,5,6,7 Controller Family Family

Gen Purpose & Embedded

Connectivity PIC32MK MC
PIC32MK Platform Motor Control
PIC32MX 1,2 120 MHz, 150 Family
Low Cost Gen Purpose & DMIPS
USB Families

19
 PIC32MZ Features
● Core Running at 200 MHz Delivering 314 DMIPS
● 2 MBytes of System Flash (Dual Panel, Live Update)
● 512 KBytes of System RAM (Two Banks)
● MIPS microAptiv™ Core (1.57 DMIPS/MHz)
● DSP and MCU ASE
● L1 Cache (16 KB Instruction, 4 KB Data)
● MMU with TLB

● Two New External Memory Interfaces

● Up to 64 MB through EBI (Async SRAM/NOR @ 50 MHz)
● Up to 64 MB through SQI (Quad/Serial Flash @ 50 MHz)

● New 12-bit Pipelined ADC (28 Msps)

● 44 Analog Inputs
● 5 dedicated S/Hs and 1 shared S/H
20
 PIC32MZ Features
● New Hardware Security Block
● RNG (True and Pseudo)
● Encryption/Decryption: AES, TDES
● Authentication: SHA-1, SHA-256, MD5 and HMAC

● Flexible Oscillator Module

● Multiple Clock Options and Clock Gating

● 8-Channel DMA (CRC, Pattern Match/Ignore)

● Additional (14) DMAs in High Speed Peripherals (USB, Ethernet,
SQI etc.,)

● Multiple Timers for System Control

● Special Purpose: WDT (Reset), DMT, RTCC (System
Tick/RTOS)
● General Purpose: 9x16-bit timers or 4x32-bit timers (cascaded)
with IC/OC
21
 PIC32MZ Features
● High-Speed Connectivity Interfaces
● USB HS/FS/LS Host, Device and OTG
● 10/100 Ethernet MAC with MII and RMII (100 Mbps)

● Various Industry Standard Communication Interfaces

● 6x4-wire SPI/I2S modules
● 2xCAN modules (1 Mbps)
● 6xUART modules (25 Mbps)
● 5xI2C modules with SMBus support (1 Mbps)
● Various Reset Sources
● POR , BOR, MCLR, SWR, NMI timeout (WDT, DMT events),
Peripheral Soft Resets

● Additional Analog Features

● 2xComparators (32 programmable V refs)
● On-chip temp sensor (±2ºC accuracy)
22
 PIC32MZ Features
● I/O Features
● 5V tolerant pins
● Pin Change Interrupt on all I/Os
● 16-bit Parallel Master Port
● Peripheral Pin Select
● Tri-State, Open-Drain and Pull-up/Pull-down Control

● Commercial and Automotive Grade 1 Qualified

● 2.0V to 3.6V and -40oC to +125oC

● Packages
● 64-QFN/TQFP, 100-TQFP, 124-VTLA, 144-LQFP/TQFP

23
 PIC32MZ EC Family Block Diagram

Ethernet

HS USB
Crypto

CAN 1

CAN 2

DMAC
MAC

SQI
HIGH SPEED BUS MATRIX

Inst Data Pre-fetch Bridge

System Cache Cache
Resources 2 MB Flash 512 KB 12-bit ADC
MIPS®
WDT Dual Panel SRAM 28 Msps, 6 S/H
microAptiveTM
POR Reset Live Update
32-bit CPU + DSP Comparator x2
BOR Reset
PLL Peripheral Bus (SYSCLK)
Xtal Osc

UART 1-6
TIMER 1-9

PWM / OC
PORT G
PORT F

8 MHz Osc

SPI / I2S
PORT
PORT
PORT

PORT
PORT

RTCC
IC 1-9
PMP

I2C
4-5
EBI
A
B
C
D
E

1-9

3-4
32 KHz Osc
JTAG

Peripheral Pin Select (PPS)

24
 PIC32MZ EC
Embedded Connectivity Family
200MHz / 314 DMIPS, Up to 2MB Flash / 512KB RAM

External
Flash Analog Timing Communication Other
Core Packages Data
RAM Modules Resources Modules Modules
Access

2 MB
512 KB
64L TQFP
6 UART
MIPS 1 MB 64L QFN 12-bit ADC
5 I2C Hardware Crypto
microAptiv™ 9x9mm 28 Msps 9 Timers
512KB 6 SPI / I2S Module
6 S/H 9 Input Capture SQI
200 MHz 100L TQFP 24 - 48 Ch 9 output PMP
1 HS USB + PHY PPS
314 DMIPS 124L VTLA Compare EBI
1 MB 1 10/100 EMAC
144L TQFP 2 Analog RTCC
256 KB 0 or 2 ECAN 2.0b
DSP, DMA 144L LQFP Comparators

512 KB
128 KB

25
 PIC32MZ EC Family
Initial Release

Encryption
Flash (MB)

Static EBI
RAM (KB)

Pin count

CAN 2.0b
Compare
#ADC Ch
DMA CH#

ADC S/H
Modules

Ethernet
HS USB
Capture

SPI / I 2S
Analog

Output

Timers
Speed

Comp

RTCC

10/100
UART
I 2C TM
Input
(MHz)

ADC

PMP
Product
PIC32MZ2048ECG144 2 512 144 200 8/12 1 48 6 2 9 9 9 1 6 5 6 1 1   N Y/Y
PIC32MZ2048ECH144 2 512 144 200 8/16 1 48 6 2 9 9 9 1 6 5 6 1 1 2 N Y/Y
PIC32MZ2048ECG124 2 512 124 200 8/12 1 48 6 2 9 9 9 1 6 5 6 1 1   N Y/Y
PIC32MZ2048ECH124 2 512 124 200 8/16 1 48 6 2 9 9 9 1 6 5 6 1 1 2 N Y/Y
PIC32MZ2048ECG100 2 512 100 200 8/12 1 40 6 2 9 9 9 1 6 5 6 1 1   N Y/Y
PIC32MZ2048ECH100 2 512 100 200 8/16 1 40 6 2 9 9 9 1 6 5 6 1 1 2 N Y/Y
PIC32MZ2048ECG064 2 512 64 200 8/12 1 24 6 2 9 9 9 1 4 4 6 1 1   N Y/N
PIC32MZ2048ECH064 2 512 64 200 8/16 1 24 6 2 9 9 9 1 4 4 6 1 1 2 N Y/N
PIC32MZ1024ECG144 1 512 144 200 8/12 1 48 6 2 9 9 9 1 6 5 6 1 1   N Y/Y
PIC32MZ1024ECH144 1 512 144 200 8/16 1 48 6 2 9 9 9 1 6 5 6 1 1 2 N Y/Y
PIC32MZ1024ECG124 1 512 124 200 8/12 1 48 6 2 9 9 9 1 6 5 6 1 1   N Y/Y
PIC32MZ1024ECH124 1 512 124 200 8/16 1 48 6 2 9 9 9 1 6 5 6 1 1 2 N Y/Y
PIC32MZ1024ECG100 1 512 100 200 8/12 1 40 6 2 9 9 9 1 6 5 6 1 1   N Y/Y
PIC32MZ1024ECH100 1 512 100 200 8/16 1 40 6 2 9 9 9 1 6 5 6 1 1 2 N Y/Y
PIC32MZ1024ECG064 1 512 64 200 8/12 1 24 6 2 9 9 9 1 4 4 6 1 1   N Y/N
PIC32MZ1024ECH064 1 512 64 200 8/16 1 24 6 2 9 9 9 1 4 4 6 1 1 2 N Y/N

26
 PIC32MZ EC Family
Initial Release with Crypto Engine

Encryption
Flash (MB)

RAM (KB)

Static EBI
Pin count

CAN 2.0b
#ADC Ch

Compare
DMA CH#

ADC S/H
Modules

Ethernet
HS USB
Capture

SPI / I 2S
Analog

Output

Timers
Speed

Comp

RTCC

10/100
I 2C TM

UART
Input
(MHz)

ADC

PMP
Product
PIC32MZ2048ECM144 2 512 144 200 8/18 1 48 6 2 9 9 9 1 6 5 6 1 1 2 Y Y/Y
PIC32MZ2048ECM124 2 512 124 200 8/18 1 48 6 2 9 9 9 1 6 5 6 1 1 2 Y Y/Y
PIC32MZ2048ECM100 2 512 100 200 8/18 1 40 6 2 9 9 9 1 6 5 6 1 1 2 Y Y/Y
PIC32MZ2048ECM064 2 512 64 200 8/18 1 24 6 2 9 9 9 1 4 4 6 1 1 2 Y Y/N
PIC32MZ1024ECM144 1 512 144 200 8/18 1 48 6 2 9 9 9 1 6 5 6 1 1 2 Y Y/Y
PIC32MZ1024ECM124 1 512 124 200 8/18 1 48 6 2 9 9 9 1 6 5 6 1 1 2 Y Y/Y
PIC32MZ1024ECM100 1 512 100 200 8/18 1 40 6 2 9 9 9 1 6 5 6 1 1 2 Y Y/Y
PIC32MZ1024ECM064 1 512 64 200 8/18 1 24 6 2 9 9 9 1 4 4 6 1 1 2 Y Y/N

27
 Feature Comparison
PIC32MX PIC32MZ
● Up to 80 MHz of Operation ● Up to 200 MHz of Operation
● MIPS M4K Core ● MIPS® microAptiv™ Core
● Pico Cache External to the Core ● L1 Cache, DSP and MCU ASE
● 1x12 KB Boot Flash ● 2x80 KB Boot Flashes
● Up to 512 KB Flash ● Up to 2 MB Flash
● Up to 128 KB RAM ● Up to 512 KB RAM
● 10-bit SAR ADC (1 Msps, 16- ● 12-bit Pipelined ADC (28 Msps,
Channels) 48 Channels)
● USB OTG FS ● First Microchip device with USB
● Automotive Grade 2 Qualified High Speed
(2.3V to 3.6V, -40C to +105C) ● External Memory Interfaces
(EBI/SQI)
● Automotive Grade 1 Qualified
(2.0V to 3.6V, -40C to +125C)

28
CPU
Introduction to PIC32MZ

29
 CPU Block Diagram
2-wire
EJTAG
Debug

Debug/Profiling Decoder

Break Points I-Cache

iFlowtrace microMIPS™ I-Cache
microAptiv™ MPU Core

FDC Controller
Perf. Counters
Sampling
Secure Debug MIPS32®

SYSTEM BUS
GPR MMU BIU
(8 sets) Execution Unit

ALU/Shift
MCU ASE Atomic/Ld St

Enhanced DSP ASE

D-Cache
MDU (32-bit)
Controller
D-Cache
DSP ASE System Control
Coprocessor (CP0)
Power Management

Interrupt I/F System I/F

30
 CPU Comparison
PIC32MX PIC32MZ
● MIPS® M4K Core ● MIPS microAptiv™ (M14KEc)
● MIPS16e® ISA for 16-bit Core
Instructions ● microMIPS® ISA 16 & 32 bit
● 105 DMIPS @ 80 MHz Instructions)
● MDU (MAC) ● 314 DMIPS @200 MHz
● Cache External to the CPU ● Extended MDU (3 additional
(Pico Cache) HI/LO regs)
● No MMU ● L1 Cache (16KB & 4 KB)
● MMU with TLB
● DSP ASE
● MCU ASE

31
 CPU Modules
microAptiv™ Core
● MIPS32® Enhanced Architecture
● MIPS32 Extended Instructions

● Programmable Interrupt Vector Bases

● Atomic Interrupt Enable/Disable (EI/DI instr.)

● 7x GPR Shadow Registers

● microMIPS® ISA:
● Reduced Code Size

● Maintained Performance

● 39x16-bit Instructions

32
 CPU Modules
System Control Coprocessor (CP0)
● Virtual-To-Physical Address Translation
● Cache Protocol Handling
● Exception Control System
● Enabling/Disabling of Interrupts
● Operating Mode Selection

33
 CPU Modules
MCU ASE
● Interrupt Delivery
● Extends Hardware Interrupt sources (6 to 8)
● Supports up to 256 External Interrupt Sources (191
used in PIC32MZ)
● Interrupt Latency Reduction
● Hardware Pre-fetch
● 7 Shadow Registers (7 priority levels)
● Hardware Assisted CP0 State Saving and Update
● IRET Instruction Improves Interrupt Return Time
● Supports Interrupt Chaining

34
 CPU Modules
DSP ASE
● Rev 2 of MIPS DSP ASE
● Over 150 Instructions - 70 SIMD and 38 MAC
● 32-bit Autonomous Multiply and Divide Unit
● 3 Additional HI/LO Registers
● Parallelization of Accumulation routines (FIR Operations,
Convolutions etc.,)
● Operates on 8/16/32-bit Signed/Unsigned
Integer/Fractional Data Types
● Arithmetic Saturation and Overflow Handling
● Zero cycle Overhead Saturation and Rounding
Operations
● DSP Library Support

35
 CPU Modules
L1 Cache
● Accelerated Code Execution and Data Access
● L1 data and Instruction caches
● 16 KB 4-way Set Associative Instruction Cache (I-
Cache)
● 4 KB 4-way Set Associative Data Cache (D-Cache)
● Both Caches
● Support Locking
● Non-Coherent
● Write Policies
● Write-Back with Write-Allocate
● Write-Through with and without Write-Allocate

36
 CPU Modules
L1 Cache
CACHED NOT CACHED

3+ clocks on first and branch instructions

1 clock access
MIPS microAptiv™ MPU Core MIPS microAptiv™ MPU Core

I-Cache D-Cache I-Cache D-Cache

SYSTEM BUS SYSTEM BUS

Pre-fetch Pre-fetch

2MB Flash 512 KB 2MB Flash 512 KB

Live-Update SRAM Live-Update SRAM
(Dual Panel) (Dual Panel)

37
CPU Modules
Cache Map

38
 CPU Modules
MMU with TLB
● Sits Between Execution Unit and Caches
● Virtual to Physical Address Translation
● Useful Feature for OS
● Protection of Memory and Cache Attributes
● Translation Look Aside Buffer (TLB) Based
● 4-Entry Fully Associative ITLB
● 4-Entry Fully Associative DTLB
● 16 Dual-Entry Fully Associative JTLB
● Exception in case of Address Translation
Miss
● Minimum 4 KB Page (Up to 64 Meg)

39
 CPU Modules
Debug
● 12 Software Breakpoints
● 8 Hardware Breakpoints (6 Inst. + 2 Data)
● PC and/or load/store Address Sampling for
Profiling on Real ICE

40
Memory
Introduction to PIC32MZ

41
PIC32MZ
System Bus

42
 Bus Initiators
PIC32MX Initiators PIC32MZ Initiators
● CPU Instruction Bus ● CPU (2)
● CPU Data Bus ● DMA Read (2)
● In-Circuit Debug ● DMA Write (2)
● DMA Controller ● USB
● USB ● Ethernet Read
● CAN ● Ethernet Write
● Ethernet ● CAN (2)
● SQI
● Flash Controller
● Crypto

43
 Bus Targets
PIC32MX Targets PIC32MZ Targets
● Flash ● Flash
● RAM ● RAM (2)
● Peripheral Bus ● EBI Memory
● Peripheral Buses (5)
● USB Slave
● SQI Memory
● Crypto Slave
● RNG

44
 Memory Protection
● In addition to Read/Write Group Permissions,
Target memory can be segmented into
separate parts and permissions
● Can create holes in the memory, hidden from
an application
● Can create separate sections of memory (e.g.
kernel memory and application memory)

45
Memory Protection

46
 Boot Memory
PIC32MX PIC32MZ
● One Boot Region ● Two Boot Regions
● 12 KB Boot Flash ● 80 KB Boot Flash x 2

47
 Live Update
● With two panels of Flash and Boot
Flash it is possible to have two
versions of application in Flash
● Run alternate version if main version
fails
● Bootloader in application or boot Flash
● Erase and program other half while
running application
● Use part of Boot Flash to hold crypto
keys

48
 Error Correction Code (ECC)

● All Flash Memories feature an Error

Correction Code
● Lengthens the life of the Flash memory by
correcting single-bit errors
● When ECC is always on, Flash programming
cannot do 32-bit writes
● Writes are to full 128-bit panel
● Dynamic ECC allows 32-bit writes
● ECC is turned off for 32-bit writes

● ECC is turned back on for 128-bit (quad-word)

writes
49
ECC and Flash Wait States
When ECC is enabled, WAIT states
must be inserted earlier

50
Oscillators
Introduction to PIC32MZ

51
 Oscillator Comparison
PIC32MX PIC32MZ
● 4 Clock Sources (POSC, FRC, ● 5 Clock Sources (POSC, FRC,
SOSC, LPRC) BFRC, SOSC, LPRC)
● 1 Peripheral Bus Clock ● POSC with Wider Input Range
● Limited Clock Grating ● Class B Compliant (BFRC)
● Additional SFRs
● 7 Peripheral Bus Clocks
● Flexible Clock Gating
● REFCLK Block

52
 Oscillators
System & Peripheral
USBPLL USBCLK

UPLLEN UPLLFSEL
POSC POSC PBCLK
PLLICLK SPLL PLLODIV<2:0>

POSC
÷N ×M ÷N SPLL
SPLL
TUN<5:0> PLLIDIV<2:0> PLLRANGE<2:0>
BFRC
PLLMULT<6:0> SYSCLK
FRC ÷N FRCDIV LPRC
INT
FRC Clock Control
FRCDIV<2:0> SOSC
To ADC and Flash
FSCM
FRCDIV
BFRC Event
BFRC
NOSC<2:0>
FCKSM<1:0> COSC<2:0> OSWEN
LPRC LPRC

SOSC SOSC

WDT, RTCC
Timer 1, RTCC

53
 Oscillators
PBCLK

ROSEL<3:0>
REFCLKIx
REFCLKOx
FRC
POSC SPI
ADC
SPLL SQI
BFRC
÷2x(N+M/512)
LPRC
SOSC N= RODIV<4:0>
M=ROTRIM<8:0>

CPU,
Peripherals
PBCLK1

÷n
 PBCLKx
÷n
PBxDIV<6:0>

PBCLK

54
 Oscillators
Bus Clock Matrix

55
I/O Features
Introduction to PIC32MZ

56
Peripheral Bus

57
 I/O Features
● 5V Tolerant Pins
● Selectable Open Drain, Pull-Ups, and
Pull-Downs
● Input Change Notification
● Operation During Sleep and Idle Modes
● 16-bit Parallel Master Port
● Peripheral Pin Select Feature

58
 GPIO Architecture

Read LAT

D Q
TRIS
CLK
LATxCLR
Write TRIS
LATxSET
LATxINV
D Q
LAT
CLK
Write LAT
ATOMIC
Write PORT

DATA BUS

Read PORT

59
 Atomic Bit Manipulation
● Fundamental Register
● LATx

● Three Atomic Registers

● LATxCLR

● LATxSET
● LATxINV

● Efficient
● Avoids the need for re RMW cycle

60
Peripheral Bus

61
 I/O Features
Peripheral Pin Select (PPS)
● One Physical Pin – Multiple Functions
● Available on Fixed Subset of I/Os
● Software Configurable
● Safe Guards Preventing Accidental Spurious
Mapping Changes
Input PPS MUX Output PPS MUX

62
Peripheral Bus

63
 I/O Features
PMP
 Parallel I/O Control PMP Interface Example
 Up to 16 Data Lines

PMWR/PCLK
Up to 16 Address Lines

PMCS0/CS


RGB<15:0
PMDATA/

HSYNC
VSYNC
 Up to 2 Chip Selects

DE
>
 Programmable Read/Write
Strobes
 Address/Data Multiplexing
 Programmable Polarity on
Control Lines (PMCSx, PMRD,
PMWR, PMENB)
 Programmable Wait States
 Fast Bit Manipulation (CLR,
SET, INV)
 Operation During Sleep and
Idle Modes

64
Demo

65
Timers
Introduction to PIC32MZ

66
Peripheral Bus

67
 Timers
Overview
● 1 Sync/Async 16-bit Timer
● 8x 16-bit Sync Timers
● Can be configured as 4x32-bit Sync Timers
● 9x Input Capture Channels
● 9x Output Compare Channels
● 24hr Real Time Clock and Calendar with Leap
Year Correction (RTCC)

68
 Timers
General Purpose Timers
● 1x16-bit Sync/Async Timer
● Selectable Clock Prescaler
● Fast Bit Manipulation (SET/CLR/INV)
● Async Mode with SOSC as RTC
● ADC Event Trigger
● Operation during Sleep and Idle Modes

69
TMR1 16-bits

70
 Timers
General Purpose Timers
● 8x 16-bit / 4x32-bit Sync Timers
 Selectable Clock Pre-scaler
 Fast Bit Manipulation (SET/CLR/INV)
 Time Base for IC and OC (Timer2-Timer7)
 ADC Event Trigger (Timer 3 & Timer 5)
 Operation during Idle mode

71
TMR2-TMR9 16-bits

72
TMR 2/3 –TMR8/9 32-bits

73
 Timers
Input Capture
● 9 Input Capture Channels
● Each Capture Channel can use
● One of 6x 16-bit Timers
● Two of 6x 16-bit Timers configured as 32-bit
● Capture Events
● On Every Edge/4th Rising Edge/16th Rising Edge
● Device Wake-up on Capture Event when in
Sleep
● Interrupt on Each Capture Event
● 4-word FIFO for Capture Values with Optional
Interrupt on Each Word Fill
● Can be a Source of an External Interrupt
74
 Timers
Input Capture

75
 Timers
Output Capture
 9 Output Compare Channels
 16-bit/32-bit Time Base Selection
 PWM Mode
 PWM Fault Detection (Hardware Based)
 Single/Dual Compare Modes
 Programmable Interrupt on Compare
 ADC Event Trigger

76
 Timers
Output Compare

77
Peripheral Bus

78
 RTCC
 Requires a SOSC for Timing Accuracy
 Date and Time Services
 24-hr Format
 One-half a second Period Visibility
 Leap Year correction
 Alarm Repeat (Counter/Indefinite)
 Fractional Second Sync.
 Crystal Frequency Calibration with Auto-
Adjust
 Calibration Range: ±0.66%

79
RTCC

80
Interrupts
Introduction to PIC32MZ

81
 High Performance Interrupts

● PIC32 has a strong architectural focus

on interrupt performance
● Interrupt Control Vector
● Single vector for each source

● Multiple priorities (7) with sub-priorities

(4)
● 7 sets of Shadow Registers

● Dynamic Vector Spacing

82
 Interrupt Module Comparison

PIC32MX PIC32MZ
● Fixed Vector Spacing ● Dynamic Vector Spacing
● Size controlled through VS ● Each vector has an OFFx
register in CP0 register for controlling location
● Minimum of 32 bytes ● Can be as small or large as
● Interrupt Priorities and Sub- needed
Priorities ● Interrupt Priorities and Sub-
● One Shadow Register Set Priorities are the same as
PIC32MX
● Seven Shadow Register Sets

83
 Interrupt Priorities
High Priority
0 7
Vectors - Normal Priority

6
... 4

Queued Sub-Priority
Preemption Priority
5
...
3
4
...

3 2
...
2
1
62
1

63 (Disabled)
0

Low Priority
84
 Preemptive Interrupt
● Higher priorities pre-empt lower priorities
● Return allows next highest priority to become
active
● Priority level stored on the stack
RETURN
P7
p7 INT
RETURN

P4
RETURN

P1

p4 INT p1 INT
P0

85
 Queued Interrupt
● Subsequent interrupts are added to the queue
● Queue is ordered by priority
● Do NOT pre-empt
● Return allows highest level in queue to go next
Queued! RETURN
P4.3
p4.3 INT

P4.2
RETURN
Queued! RETURN

P4.1

p4.2 INT
P0
p4.1 INT

86
DMA
Introduction to PIC32MZ

87
 DMA Engine & Peripherals
● PIC32MZ has a total of 26 DMA engines
● Programmable
● DMA: 8
● Dedicated
● USB: 8

● Ethernet: 2

● CAN: 4 (2 for each channel)

● Crypto: 2

● SQI: 2

88
 DMA Operation Modes
● 5 modes:
● Basic Transfer
● Pattern Match Completion
● Channel Chaining
● Chanel Auto-Enable
● CRC calculation

89
 DMA Pattern Ignore
● New feature with pattern matching
● When using 16-bit pattern match, helps filter
data that may break up pattern

… 0x0D 0x0A …

… 0x0D 0x00 0x0A …

This will be ignored, and match will be made.

90
High Speed Peripherals
Introduction to PIC32MZ

91
 PIC32MZ EC Family Block Diagram

Ethernet

HS USB
Crypto

CAN 1

CAN 2

DMAC
MAC

SQI
HIGH SPEED BUS MATRIX

Inst Data Pre-fetch Bridge

System Cache Cache
Resources 2 MB Flash 512 KB 12-bit ADC
MIPS®
WDT Dual Panel SRAM 28 Msps, 6 S/H
microAptiveTM
POR Reset Live Update
32-bit CPU + DSP Comparator x2
BOR Reset
PLL Peripheral Bus (SYSCLK)
Xtal Osc

UART 1-6
TIMER 1-9

PWM / OC
PORT G
PORT F

8 MHz Osc

SPI / I2S
PORT
PORT
PORT

PORT
PORT

RTCC
IC 1-9
PMP

I2C
4-5
EBI
A
B
C
D
E

1-9

3-4
32 KHz Osc
JTAG

Peripheral Pin Select (PPS)

92
High Speed Peripheral Bus

93
 High-Speed Peripherals
External Bus Interface (EBI)
● Interfaces External Parallel memories
● Async. SRAM or Async. NOR
● Interfaces Non-Memory Devices (in
conjunction with PORT pins)
● Camera Sensors
● LCDs
● Up to 50 MHz of Operation
● 24 Address Lines and 16 Data Lines (x8, x16)
● 4 Chip Selects Supporting up to 64 MB of
Memory
● Flexible Timing Control
● Mapped to KSEG2 by default

94
 High-Speed Peripherals
EBI

EBI Block Diagram EBI Interface Example

WE
Address<23:0>

Async
Async SRAM
CS
RDY
EBIWE

SRAM
EBIA<23:0> OE

EBICS0 Data<15:0>

EBIRDY
PIC32MZ
External Bus
Interface

EBIOE Pixel Clock

EBID<15:0> RGB (16bit)

EBICS1 EN
LCD
LCD

95
 High-Speed Peripherals
USB
● USB 2.0 Host, Device and OTG
● High-Speed (480 Mbps), Full-Speed
(12 Mbps) and Low-Speed (1.5 Mbps)
Support
● Support MCHP USB2.0 Hub Controllers
when New ISP with Hub Class Support is
Available (Q4-13)
● Integrated 8-channel DMA (Faster
Access to System Memories)
● 7 Transmit and 7 Receive End Points
(In Addition to EP0)

96
 High-Speed Peripherals
USB
● Max speed USB
functionality
● Clock PLL – separate USB
independent from the clock’s core
● Integrated transceiver
● 2 integrated DMA channels
Device
● Supported Modes
● Embedded Host Host
● Device PIC32 Dual role
● On-the-Go
● Dual Role 2 DMA

● USB Software Library

available in MLA / MPLAB
Harmony

97
 High-Speed Peripherals
Ethernet
● Integrated Ethernet MAC of 10/100 Mbps
● 2 dedicated DMA channels create less weight
on the CPU 2
● Supports max data speed.. of 100 Mbps
● Typical flow of Mbps only consumes 5 MIPS

● Industry Standard Interface to chips PHY

● Simple connection to Microchip/SMSC LAN
8700 PHY
● PIC32MX6/7 series support both RMII and MII
interfaces

98
High Speed Peripherals - SQI
Introduction to PIC32MZ

99
 What is SQI Flash?
● A flash memory that reads and writes though a 4-bit
multiplexed synchronous serial communication interface
● Enables real low-pin count, high-bandwidth code, and
data applications XiP
● Operation frequency of up to 104 MHz
Host Controller
Clock
SPI /SQI Flash IF

CPU Chip Select

I/O 1 SQl
I/O 2 Flash
Internal
I/O 3
Memory I/O 4

100
 The Bandwidth Problem

SQI 100 MHz

SQI 80 MHz

Parallel x16 70ns

Parallel x8 70ns

SPI 75 MHz

0 50 100 150 200 250 300 350 400

Data Rate (Mbits / sec)
Sustained Data Rate 32 Bytes Sequential Read for XIP

SQI Outperforms both SPI Serial and Parallel Flash

101
 Operation Modes
● SPI (x1)
● Industry standard SPI command set
● Default state at power-up
● SQI (x4)
● 4-bit command, address, data (4-4-4) for all
commands
● All Read and Write commands
● SPI Multi-I/O (x2, x4)
● Read modes support
● Dual bit format (1,1,2) & (1,2,2)
● Quad bit format (1,2,2) & (1,4,4)

102
 High-Speed Peripherals
Serial Quad Interface (SQI)
● Interfaces to Quad Flash and Serial
Flash Memories
● Master Mode of Operation Only
● Up to 50 MHz of Operation
● 3 Transfer Modes
● DMA, XIP and PIO (CPU)
● 3 Data Modes
● SPI Mode 0, Mode3 and Serial Flash Mode

103
 High-Speed Peripherals
SQI
● DMA (Direct Memory Access) Mode
● Higher Throughput Transfer Mode (CPU is off-loaded)
● Buffer Descriptors Perform Data Transfers.
● 256 Bytes of Data Per Descriptor

● Descriptor Chaining

● XIP (eXecute-In-Place) Mode

● Minimal Software Configuration
● Sequence and Protocol Handling by Hardware
● Mapped to KSEG2
● PIO (Programmed Input Output) Mode
● CPU Controls Transaction through SQI
● Heavy Lifting by CPU and System Bus (Throughput)
● Uses Interrupt and Status Bits to Control the Transactions

104
High-Speed Peripherals
SQI Block Diagram

105
 High-Speed Peripherals
SQI Example

SQICS0 CS#

SQICLK SCK

Quad Flash
(SST26VF)
(MOSI)SQID0 SIO0
SIO1

SIO2
SIO3
SQI
SCK
SI

Serial Flash
(SST25VF)
(MISO)SQID1 SO

SQID2 WP#

SQID3 HOLD#

SQICS1 CS#

106
Low Speed Peripherals
Introduction to PIC32MZ

107
 PIC32MZ EC Family Block Diagram

Ethernet

HS USB
Crypto

CAN 1

CAN 2

DMAC
MAC

SQI
HIGH SPEED BUS MATRIX

Inst Data Pre-fetch Bridge

System Cache Cache
Resources 2 MB Flash 512 KB 12-bit ADC
MIPS®
WDT Dual Panel SRAM 28 Msps, 6 S/H
microAptiveTM
POR Reset Live Update
32-bit CPU + DSP Comparator x2
BOR Reset
PLL Peripheral Bus (SYSCLK)
Xtal Osc

UART 1-6
TIMER 1-9

PWM / OC
PORT G
PORT F

8 MHz Osc

SPI / I2S
PORT
PORT
PORT

PORT
PORT

RTCC
IC 1-9
PMP

I2C
4-5
EBI
A
B
C
D
E

1-9

3-4
32 KHz Osc
JTAG

Peripheral Pin Select (PPS)

108
Peripheral Bus

109
 Connecting to the World

● Parallel Master Port (PMP)

● Connects to external memory, graphics, or
another parallel interface chip
● Can use GPIO to extend address range

Graphic
PMP Controllers
Address of up to 64kB
8 o 16 lines of data
2 chip selects Flash Memory

SRAM

110
Peripheral Bus

111
 Low-Speed Peripherals
UART
● Full Duplex, 8-bit and 9- UART LIN Interface Example
bit Data Transmission

LIN Slave
Buffer
● Even, Odd and No Parity

PIC32MZ LIN Master

RX

Support
● One or Two stop bits
TX
● Hardware Auto Baud

LIN Slave
Open Drain
Feature
● Hardware Flow Control

LIN Bus
● Loop Back Mode
LIN Protocol Support

LIN Slave
●
● IrDA® Encoder and Buffer
Decoder
PIC32MZ LIN Slave

RX

LIN Slave
TX

Open Drain

112
 Low-Speed Peripherals
SPI & I2S
 Audio Support I2S Interface Examples
 I2S Protocol

PIC32MZ SPI Master

 Right Justified SCKx BCLK

Audio Codec
 Left Justified
 PCM SSx LRCK

 Up to 50 MHz of Operation
 Master and Slave Modes SDOx DACDAT

 Enhanced Framed SPI

Protocol Support SDIx ADCDAT

 2 FIFOs for Data Handling

 16-byte Transmit FIFO
PIC32MZ SPI Slave
SCKx BCLK
 16-byte Receive FIFO

Audio Codec
 Deep Sleep and Idle Mode SSx
Control LRCK

SDOx DACDAT

SDIx ADCDAT

113
 Low-Speed Peripherals
I2C™
 Master and Slave Modes I2C Interface Example
PIC32MZ I2C Interface
 7-bit and 10-bit Transfers

SDA
SCL
 Clock Synchronization
for Suspend/Resume

(touch
(touch controller)
MTCH6301
MTCH6301
 Multi Master Operation

controller)
 Collision Detection and
Re-arbitration

Accelerometer
Accelerometer
 Address Bit Masking
 SMBus Support

(Serial
(Serial EEPROM)
24LC1026
24LC1026
EEPROM)

(Temp.
(Temp. Sensor)
MCP9843
MCP9843
Sensor)
114
Peripheral Bus

115
 Dual Channel CAN
● Industry-standard
CAN
CAN2.0b Controller
● Up to 1 Mbps 32 Filters
4 Masks
● A RAM system for 2 ch. DMA

message storage without

an integrated DMA 80 MHz System Bus

interface
● Up to 1024 messages can System RAM

be stored on RAM system FIFO 1

1-32
FIFO32
1-32
using 32 configurable Message
Buffers 1-32 FIFOs
Message
Buffers
FIFOs 32 FIFOs x 32 Buffers = 1024 Messages

● Advanced filter to simplify

message processing
116
Low-Speed Peripherals
12Bit ADC
● Five dedicated S&H
● One shared S&H
● Three clock sources
● Six-stage conversion
pipeline
● Six digital comparators
● Six digital filters
● IVref and IVtemp inputs
● Data registers for each
input

117
ADC Filters
● Digital Filters increase
accuracy at the cost of
throughput
● Each filter can be connected
to any of the AN0-AN42 inputs
● Plus IVREF and IVTEMP
● After enabling, the first
conversion is added to the
accumulator
● Subsequent conversions are
added to the accumulator
● Interrupt trigger when all
oversamples are done
● Multiple inputs are interleaved
118
 ADC Calibration
● Before operation, a calibration sequence
must take place
● Source calibration data contained in DEVADC1-
DEVADC5
● Must be copied to AD1CAL1-AD1CAL5
● When ADC is enabled (AD1CON1.ADCEN),
calibration automatically takes place
● AD1CON2.ADCRDY will indicate when
calibration is done
● ADC must be calibrated or result will be
0xFFFF
119
Tools

120
 PIC32 MCU Tools
A complete ecosystem
• Support for the ecosystem grows daily
• Critical tools available from and supported by Microchip
• The third party tool network is even bigger

IDE Languages OS Startup HW Debug

MPLAB X C FreeRTOS MicroStick PICkit3
C++ OpenRTOS chipKIT ICD3
Java Micrium Starter Kits Real ICE
Thread X JTAG Probe

Tools for graphic MPLAB Harmony Code

applications TCP/IP, USB, Wi-Fi, Crypto, Generation
Graphic Library File System, Bootloader, Simulation
Graphic Design Tool Touch, Bluetooth, MFi, MATLAB
ZigBee, Mi-Wi and more… MPLAB X SIM

121
 PIC32MZ EC Starter Kit
● Integrated
debugger/programmer
● USB Powered
● 10/100 Ethernet Development
using PIC32 MCUs
● High Speed USB host, device,
Dual Role and OTG
● 4 MB SQI Flash
● On-line tools & software
download
● PIC32MZ MCU
● Enables addition of PIC32
Expansion Board
● Available as both Crypto &
non-Crypto Version
122
 PIC32 Multimedia
Expansion Board II (MEB II)
● Compact, highly versatile expansion board for developing a wide range
of multimedia applications.
● Includes a 4.3" WQVGA PCAP touch display daughter board and
supports detachable display boards allowing for a variety of
resolutions.
Key Features:
● Works with PIC32 MZ Starter Kit
● 24-bit stereo audio codec
● Integrated 802.11bg wireless module
● Low-cost Bluetooth® HCI transceiver
● Optional EBI SRAM memory
● mTouch™ buttons
● Analog accelerometer
● Analog temperature sensor
● VGA Camera
● PICtail™ Connector

123
Introducing MPLAB HARMONY

124
 Traditional Apps

/* Timer Peripheral Initialization */

● Part Specific T2CONbits.ON = 0;
T2CONbits.TCKPS = 7;
● Register T2CONbits.TCS = 0;
T2CONbits.T32 = 1;
details TMR2 = 0;
PR2 = APP_LED_BLINKING_RATE;
● Hard-Coded T2CONbits.ON = 1;

Values /* Loop forever, blinking the LED. */

while(true)
● Application {
if ( IFS0bits.T3IF )
Specific {
IFS0bits.T3IF = 0;
LATAbits.LATA0 = ~LATAbits.LATA0;
}
}

125
 Consistent Application Code

int main ( void )

PIC32MX110F016B
{
/* Port Pin Initialization */ Peripheral Library
PLIB_PORTS_Write(APP_PORT, APP_PORT_CHANNEL, 0);
PLIB_PORTS_PinDirectionOutputSet(APP_PORT, APP_PORT_CHANNEL, APP_PORT_BIT);
Application
/* Timer Peripheral Initialization */
PLIB_TMR_Stop(APP_TIMER);
TMR INT PORTS
PLIB_TMR_PrescaleSelect(APP_TIMER, APP_TIMER_PRESCALE); PLIB PLIB PLIB
PLIB_TMR_ClockSourceSelect(APP_TIMER, APP_TIMER_CLOCK_SOURC);
PLIB_TMR_Period32BitSet(APP_TIMER, APP_LED_BLINKING_RATE);
PLIB_TMR_Mode32BitEnable(APP_TIMER);
PLIB_TMR_Start(APP_TIMER);

/* Loop forever, blinking the LED. */

while(true)
{
if( PLIB_INT_SourceFlagGet(APP_INT_CONTROLLER, APP_INT_SOURCE) )
{
PLIB_INT_SourceFlagClear(APP_INT_CONTROLLER, APP_INT_SOURCE);
PLIB_PORTS_PinToggle(APP_PORTS, APP_PORT_CHANNEL, APP_PORT_BIT);
}
}
return(EXIT_VALUE);
}

126
 Consistent Application Code

int main ( void )

PIC32MZ2048ECG064
{
/* Port Pin Initialization */ Peripheral Library
PLIB_PORTS_Write(APP_PORT, APP_PORT_CHANNEL, 0);
PLIB_PORTS_PinDirectionOutputSet(APP_PORT, APP_PORT_CHANNEL, APP_PORT_BIT);
Application
/* Timer Peripheral Initialization */
PLIB_TMR_Stop(APP_TIMER);
TMR INT PORTS
PLIB_TMR_PrescaleSelect(APP_TIMER, APP_TIMER_PRESCALE); PLIB PLIB PLIB
PLIB_TMR_ClockSourceSelect(APP_TIMER, APP_TIMER_CLOCK_SOURC);
PLIB_TMR_Period32BitSet(APP_TIMER, APP_LED_BLINKING_RATE);
PLIB_TMR_Mode32BitEnable(APP_TIMER);
PLIB_TMR_Start(APP_TIMER);

/* Loop forever, blinking the LED. */

while(true)
{
if( PLIB_INT_SourceFlagGet(APP_INT_CONTROLLER, APP_INT_SOURCE) )
{
PLIB_INT_SourceFlagClear(APP_INT_CONTROLLER, APP_INT_SOURCE);
PLIB_PORTS_PinToggle(APP_PORTS, APP_PORT_CHANNEL, APP_PORT_BIT);
}
}
return(EXIT_VALUE);
}

127
 Introducing MPLAB® Harmony
● Introduction
● MPLAB® Harmony is a comprehensive, interoperable,
tested software development framework for
Microchip’s PIC32 microcontrollers.
● The framework integrates both internal and 3rd party
middleware, drivers, peripheral libraries and real time
Flexible
operating systems, simplifying and accelerating the
32-bit development process.
Re-Usable Modular
● The MPLAB Harmony framework operates within the MPLAB®
Harmony
MPLAB® X IDE development environment.
● First Line of Support Compatible Interoperable
● First line of support provided by Microchip for all
Harmony components, including third-party solutions
● Comprehensive Web Portal
● Includes Licensing, Resale, Technical Support &
Collateral for Microchip & third-party Harmony
components

128
 Low level peripheral drivers
Specific Device

Application(s)

Plug- Plug-
Driver
in in
Middleware
O Common
RTOS S System Middleware Driver
A Services
L

Driver Driver Driver Driver Driver

RTOS ISP
Configuration Configuration
PLIB PLIB PLIB PLIB PLIB

129
 High Level Peripheral Drivers
Independent Device

Application(s)

Plug- Plug-
Driver
in in
Middleware
O Common
RTOS S System Middleware Driver
A Services
L

Driver Driver Driver Driver Driver

RTOS ISP
Configuration Configuration
PLIB PLIB PLIB PLIB PLIB

130
 Application Library for ALL families!
(8/16/32)

Application(s)

Plug- Plug-
Driver
in in
Middleware
O Common
RTOS S System Middleware Driver
A Services
L

Driver Driver Driver Driver Driver

RTOS ISP
Configuration Configuration
PLIB PLIB PLIB PLIB PLIB

131
 MPLAB Harmony
Modules
MPLAB Harmony v1.00 – Nov ‘13 Harmony – In Development

USB Device TCP/IP File System Bluetooth Class B

Audio Stack Safety
USB Host Wi-Fi g Crypto

Graphics MP3/AAC Peripheral Android/MFi mTouch

GDDX/GRC Decoder Libraries
Math/DSP
Microchip Harmony Libraries Libraries
Future 3rd Party Software
InterNiche freeRTOS Micrium
TCP/IP OpenRTOS µC-OS/III Express Logic Segger
ThreadX Graphics
Harmony Compatible CyaSSL Embedded SSL
3rd Party SW

InterNiche freeRTOS
TCP/IP OpenRTOS
3rd Party SW – Direct Sell & First line Support PIC32MX – Production Release
from Microchip
PIC32MZ – Release Updates
PIC32MX – Beta PIC32MZ – Production
PIC32 Product Family Support –
PIC32 Product Family Support – Hardware Hardware
132
 MPLAB Harmony
Architecture
Application Layer
• Implements the overall desired behavior
• No direct HW access enables easy
porting across Microchip parts

Common System Services

• Manages shared resource modules to
avoid conflicts.
• Provides common functionality to avoid
duplication

Middleware
• Implements complex libraries &
protocols (USB, TCP/IP, Graphics etc) Application(s)
• Provides highly abstracted application
program interface
Plug- Plug-
Device Drivers Driver
O in in
• Provides simple & abstracted interface
Common Middleware
RTOS S
to peripheral
• Manages peripheral access control to System Middleware Driver
avoid conflicts A Services
Peripheral Libraries (PLIB) L
Driver Driver Driver Driver Driver
• Access library that provides low level
direct access to a peripheral
RTOS System
• Provides common functional interface
Configuration Configuration PLIB PLIB PLIB PLIB PLIB
for MCHP cross micro compatibility

133
 MPLAB Harmony
Device Drivers
Responsibilities Application(s)
• Simple Peripheral API Plug- Plug-
Driver
• Initialize / De-initialize O
Common Middleware
in in

• Open / Close RTOS S System

A Services
Middleware Driver
• Read / Write (if appropriate) L
• Device-Specific Functions
Driver Driver Driver Driver Driver

• Peripheral State Machine RTOS System

ConfigurationConfiguration PLIB PLIB PLIB PLIB PLIB

• Multiple Clients
• Multiple HW Instances Configurable
• Polled or Interrupt-Driven
• Access to HW via: • Static or Dynamic
• PLIB – for its own HW • Blocking or Non-Blocking
• SYS service for shared HW • Exclusive Access or Shared
• Other drivers for other HW Access
• Thread Safe using OSAL • Optional Features

134
 MPLAB Harmony
Driver Example

Peripheral State Machine

1. Application Calls Driver SYS Application

2. Driver Starts Operation 5 1

4
3. Driver Waits on Interrupt
(or Int. Flag, if Polled) I2C Driver
4. Interrupt Occurs & Calls State Machine
Driver. (or System Calls
Driver)
5. Driver finishes Operation
(Unblocks or Notifies App) 2
INT 3
I2C PLIB
P-Lib

135
 MPLAB Harmony
Peripheral Libraries
Responsibilities Application(s)
• Functional Interface Plug- Plug-
Driver
• Primitive operations O
Common Middleware
in in

• Exposes all features RTOS S System

A Services
Middleware Driver
• Normalizes bits & registers L

•
Driver Driver Driver Driver Driver
Cross-Micro
RTOS System
Compatibility ConfigurationConfiguration PLIB PLIB PLIB PLIB PLIB

• Common interface for all micros

• Provides direct HW access
Key Points:
• Indexed HW Instance
• Function Look & Feel
• Processor-specific
implementations • No Access Control
• Stateless Macros/In-lines • No State Control
• No Blocking

136
 Non-Modular Libraries
Shared Resource Conflicts TCP/IP
 Multiple libraries try to use

same resource TMR2

 Register accesses may

interfere with each other USB

 May not even build of they
Conflict!
define the same symbols TMR2
 May result in complex

inter-dependencies often Graphics

resolved with #ifdef’s

TMR2

137
 Modularity
Each Module… TCP/IP
 …owns and manages
its own resources, SYS_TMR_Callback();

 …provides a simple
USB
abstracted interface,
 …calls other modules
to use other resources. SYS_TMR_Callback();

Graphics
Eliminates Conflicts! System
Timer
Module
SYS_TMR_Callback();
TMR 2

138
Help

139
 Summary
All in One Eco-System for Microchip’s most comprehensive software development
●

PIC32 environment yet

Where to get MPLAB Download MPLAB Harmony @ Beta Site Link

●

Harmony? Production Site – Live on Nov 18 2013

●

Support User support is provided by Forum @ Beta Site Link

●

Pricing Basic framework is FREE!

●

Select Tools & Libraries in future may be charged

●

One Stop Shop License, Resale, Support (including 3rd party solutions)
●

Easy Migration Architecture allows for easy migration between the broad portfolio
●

of PIC32 parts

Pre tested, proven components requires very less effort to integrate

●

Shorter Development Time in the system

140
 Summary
• Modular architecture allows Drivers and Libraries to work
Improved Code together with minimal effort
Interoperability • Applications can be easily ported to different boards

Faster Time to Market • Integrated single platform enables shorter development time
for Customers • Able to easily add features

Improved • Improves scalability across PIC32 Microchip parts to custom

Compatibility fit customers requirement

• Common SW platform with standard interface ensures

Simplified Support efficient Microchip support
• One stop support for all customer needs

• MPLAB Harmony integrates third party solutions (RTOS,

Enhanced 3 party
rd
Middleware, Drivers etc) into the software framework
seamlessly
software integration

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Resources and Summary

142
Summary
References
www.microchip.com/pic32

143
 Summary
References

www.mips.com

PIC32MX

PIC32MZ

144
Summary
References

PIC32 Family Reference Manual

145
 Summary
● The PIC32 MCU family delivers best-in-class
performance
● Developing with the PIC32 is simple and easy
● Microchip and industry partners have a vast array of
software and tools to reduce your development time
● PIC32 performance enables running major software
stacks concurrently
● Maintained low cost using free software and
inexpensive hardware
● Quick development using off-the-shelf software and
hardware
● For more information, visit
http://www.microchip.com/pic32

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 Focus on the Solution

Free libraries
TCP/IP, USB, Graphics, Audio…

Dev. boards
Starter kits, MEB, ADB, LCCG,…

Free Software Tools

MPLAB X, Graphics Display Design X

147
Thank you!
 LEGAL NOTICE
SOFTWARE:
You may use Microchip software exclusively with Microchip products. Further, use of Microchip software is subject to the copyright notices, disclaimers, and any license
terms accompanying such software, whether set forth at the install of each program or posted in a header or text file.

Notwithstanding the above, certain components of software offered by Microchip and 3rd parties may be covered by “open source” software licenses – which include
licenses that require that the distributor make the software available in source code format. To the extent required by such open source software licenses, the terms of
such license will govern.

NOTICE & DISCLAIMER:

These materials and accompanying information (including, for example, any software, and references to 3rd party companies and 3rd party websites) are for informational
purposes only and provided “AS IS.” Microchip assumes no responsibility for statements made by 3rd party companies, or materials or information that such 3rd parties
may provide.

MICROCHIP DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, INCLUDING ANY IMPLIED WARRANTIES OF NONINFRINGEMENT,
MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY DIRECT OR INDIRECT, SPECIAL,
PUNITIVE, INCIDENTAL, OR CONSEQUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND RELATED TO THESE MATERIALS OR ACCOMPANYING
INFORMATION PROVIDED TO YOU BY MICROCHIP OR OTHER THIRD PARTIES, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBLITY OF SUCH
DAMAGES OR THE DAMAGES ARE FORESEEABLE.

TRADEMARKS:
The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo,
SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,  MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In‑Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient
Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC,
UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

149
EMBARGOED UNTIL November 18, 2013
 What are we Announcing?
● New PIC32 Microcontroller Family offering breakthrough performance,
and high memory and peripheral integration.
● Class-Leading 32-bit MCU Performance With 200 MHz / 330 DMIPS and 3.28
CoreMarks™/MHz
● Over 3x performance of previous generation PIC32 MCUs
● Class-Leading 32-bit MCU Code Density while Maintaining Top Performance –
30% better than competitors
● Class-Leading 32-bit MCU ADC Throughput at 28 Msps
● Up to 2 MB Flash and 512 KB RAM
● Dual-Panel Flash with Live Update
● Highest Integrated Memory of any PIC ® MCU (4x)
● High Integration
● Hi-Speed USB (PIC MCU First)
● 10/100 Ethernet MAC
● 2 CAN 2.0b modules
● 6 UART, 6 SPI / I²S, 5 I²C™
● SQI (PIC MCU First)
● Full-Featured Hardware Crypto Engine
● Crypto Engine with a Random Number Generator (RNG) for data encryption/decryption and
authentication (AES, 3DES, SHA, MD5, and HMAC)

151
 What are we Announcing
(Continued)?
● Compact, affordable Starter kits and Development
Boards – All Available at Launch
● PIC32MZ Embedded Connectivity (EC) Starter Kit (DM320006) -
Complete, turn-key kit ($119.00)
● PIC32MZ EC Starter Kit with Crypto Engine (DM320006-2) -
Complete, turn-key kit ($119.00)
● PIC32MZ2048EC PIM (MA320012)- Explorer 16 Plug In Module
($25.00)
● Multimedia Expansion Board II (DM320005-2) – Integrated
Development and Demonstration Platform for use with Starter
Kit ($299.00—introductory price for first 6 months)
● 168-pin to 132-pin Starter Kit Adapter (AC320006) – Adaptor to
interface PIC32MZ Starter Kit with extensive portfolio of
application-specific daughter boards ($59.00)

152
 Expanding PIC32 Portfolio
PIC32MZ EC
Packages as small as
9x9 mm
330 DMIPS
(64 QFN & 124 VTLA) 1024-2048KB / 512KB
64-144 pins
HS USB, CAN(2),
Ethernet, Crypto, PPS

PIC32MX5/6/7
105 DMIPS
64-512KB / 16-128KB
Features

64-100 pins
USB, Ethernet,
CAN(2)

PIC32MX1/2 PIC32MX3/4
66/83 DMIPS 131 DMIPS
64-128KB / 16-32KB 64-512KB / 16-128KB
28-44 pins 64-100 pins
USB, I2S, CTMU, USB, I2S, CTMU,
PPS PPS

PIC32MX1/2
PIC32MX3/4
66/83 DMIPS
105 DMIPS
16-32KB / 4-8KB
32-512KB / 4-32KB
28-44 pins
64-100 pins
USB, I2S, CTMU,
USB
PPS

66 / 83 DMIPS 105 / 131 DMIPS 330 DMIPS

153
 Target Markets

Markets Application Examples

Consumer Audio High-End Docking Stations, Streaming Audio, Wireless Audio
Factory Automation PLC, I/O Modules, HMI
Building Automation HVAC, Environmental Controls, Security, Fire & Safety
Panels, Access Terminals
Home Automation HVAC, Thermostats, Power Mgmt., Security, Sensors
Power Meters Electrical-Meter Communication Modules
Renewable Energy Control Modules
Automotive – Body Dashboard, Rearview Camera, Infotainment
Appliances Consumer White Goods, Small Appliances
Transportation Dashboard, Fleet Management
Security Control Panels, Keypads, RFID Reader
Cloud Computing Data Aggregator, Access Points

154
 Key Features and Benefits

Key Feature Benefit

Performance to manage multiple communication stacks, manage graphics, perform audio
330 DMIPS Processing
2 MB Live-Update Memory space to store large applications as well as data. Live-update capability enables
Flash true remote field updates while application is running in a fail-safe manner.
Large internal RAM supports multiple protocol stacks operating simultaneously, buffer space
512 KB RAM
supporting audio processing, and Frame Buffers supporting Graphic Displays
MIPS microAptiv™ Class-leading efficiency and Code Density supports doing more with less. Digital Signal
Core Processing Extensions enhance performance of DSP algorithms.
Host / Device / OTG capability coupled with up to 480 MBPS performance greatly speeds
Hi-Speed USB transfer of large files and streaming data
12-bit 28 MSPS ADC Class-leading ADC throughput coupled with 6 sample-and-hold circuits and up to 48
channels supports complex mixed-signal applications
10/100 Ethernet MAC Supports applications needing network and WAN access
Provides Higher throughput for Secure Connectivity applications and offloads processing
Crypto Engine
from the core, freeing up DMIPS for other tasks
SQI Serial Quad Interface supports high-speed interface to external Flash storage

Dual CAN Dual Controller Area Network ports supporting Industrial and Automotive applications

155
 MIPS microAptiv™ Core:
New Features
● High-performance: 1.65 DMIPS / MHz (same as M4K™)
● DSP Engine added (159 new instructions added)
● Cache core
● microMIPS® offers better code size and performance combination
● Optimally mixes in 16/32 instructions
● Performance of MIPS32® ISA (within 2-3%)
● Code size of MIPS16® ISA
● MIPS32 legacy decoder – fully backward compatible
● Reduced interrupt latency (10 cycles)
● Enhanced debug features
● Lower power

156
 MPLAB® X IDE:
Integrated Toolset

157
 Summary
● The new PIC32MZ EC MCU Family brings
breakthrough performance, and high memory and
peripheral integration, supporting advanced
applications:
● 200 MHz / 330 DMIPS and 3.28 CoreMarks™/MHz performance
● Up to 2 MB Flash and 512 KB RAM internal memory with Live
Update
● Up to 48 Channels of 12-bit ADC, operating at 28 Msps
throughput
● Hi-Speed USB, 10/100 Ethernet and Dual CAN
● Optional Hardware Crypto Engine
● Package sizes starting at 9x9 mm (64-pin QFN & 124 VTLA)

158